[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 24 03:02:17 PST 2025


https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/169307


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