[llvm] [RISCV]: Implemented softening of `FCANONICALIZE` (PR #169234)

[via llvm-commits]

https://github.com/kper created https://github.com/llvm/llvm-project/pull/169234

The `ISD::FCANONICALIZE` is mapped to `FMIN` because `-mattr=+d` also maps it to `fmin.d fa0, fa1, fa1`.

Closes https://github.com/llvm/llvm-project/issues/169216

>From a7af5b21388d4941f9008582e081ae8b1312eb63 Mon Sep 17 00:00:00 2001
From: Kevin Per <kevin.per at protonmail.com>
Date: Sun, 23 Nov 2025 21:02:45 +0100
Subject: [PATCH] [RISCV]: Implemented softening of `FCANONICALIZE`

---
 .../SelectionDAG/LegalizeFloatTypes.cpp       |  8 +++
 llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h |  1 +
 llvm/test/CodeGen/RISCV/fcanonicalize.ll      | 64 +++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/fcanonicalize.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 383a025a4d916..d405295229203 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -70,6 +70,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
     case ISD::EXTRACT_VECTOR_ELT:
       R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
     case ISD::FABS:        R = SoftenFloatRes_FABS(N); break;
+    case ISD::FCANONICALIZE:
+      R = SoftenFloatRes_FCANONICALIZE(N); break;
     case ISD::STRICT_FMINNUM:
     case ISD::FMINNUM:     R = SoftenFloatRes_FMINNUM(N); break;
     case ISD::STRICT_FMAXNUM:
@@ -311,6 +313,12 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
   return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatRes_FCANONICALIZE(SDNode *N) {
+  return SoftenFloatRes_Unary(
+      N, GetFPLibCall(N->getValueType(0), RTLIB::FMIN_F32, RTLIB::FMIN_F64,
+                      RTLIB::FMIN_F80, RTLIB::FMIN_F128, RTLIB::FMIN_PPCF128));
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
   if (SDValue SelCC = TLI.createSelectForFMINNUM_FMAXNUM(N, DAG))
     return SoftenFloatRes_SELECT_CC(SelCC.getNode());
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index ede522eff6df3..c90cb7bc88f57 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -585,6 +585,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   SDValue SoftenFloatRes_FASIN(SDNode *N);
   SDValue SoftenFloatRes_FATAN(SDNode *N);
   SDValue SoftenFloatRes_FATAN2(SDNode *N);
+  SDValue SoftenFloatRes_FCANONICALIZE(SDNode *N);
   SDValue SoftenFloatRes_FMINNUM(SDNode *N);
   SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
   SDValue SoftenFloatRes_FMINIMUMNUM(SDNode *N);
diff --git a/llvm/test/CodeGen/RISCV/fcanonicalize.ll b/llvm/test/CodeGen/RISCV/fcanonicalize.ll
new file mode 100644
index 0000000000000..334657bdf92de
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fcanonicalize.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+d < %s | FileCheck -check-prefix=RV64D %s
+
+define double @max(double, double) unnamed_addr #0 {
+; RV64I-LABEL: max:
+; RV64I:       # %bb.0: # %start
+; RV64I-NEXT:    addi sp, sp, -32
+; RV64I-NEXT:    .cfi_def_cfa_offset 32
+; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    .cfi_offset ra, -8
+; RV64I-NEXT:    .cfi_offset s0, -16
+; RV64I-NEXT:    .cfi_offset s1, -24
+; RV64I-NEXT:    .cfi_offset s2, -32
+; RV64I-NEXT:    mv s0, a1
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    call __ltdf2
+; RV64I-NEXT:    srli s2, a0, 63
+; RV64I-NEXT:    mv a0, s1
+; RV64I-NEXT:    mv a1, s1
+; RV64I-NEXT:    call __unorddf2
+; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    or a0, a0, s2
+; RV64I-NEXT:    bnez a0, .LBB0_2
+; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    mv s0, s1
+; RV64I-NEXT:  .LBB0_2: # %start
+; RV64I-NEXT:    mv a0, s0
+; RV64I-NEXT:    call fmin
+; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    .cfi_restore ra
+; RV64I-NEXT:    .cfi_restore s0
+; RV64I-NEXT:    .cfi_restore s1
+; RV64I-NEXT:    .cfi_restore s2
+; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
+; RV64I-NEXT:    ret
+;
+; RV64D-LABEL: max:
+; RV64D:       # %bb.0: # %start
+; RV64D-NEXT:    flt.d a0, fa0, fa1
+; RV64D-NEXT:    feq.d a1, fa0, fa0
+; RV64D-NEXT:    xori a1, a1, 1
+; RV64D-NEXT:    or a0, a1, a0
+; RV64D-NEXT:    bnez a0, .LBB0_2
+; RV64D-NEXT:  # %bb.1: # %start
+; RV64D-NEXT:    fmv.d fa1, fa0
+; RV64D-NEXT:  .LBB0_2: # %start
+; RV64D-NEXT:    fmin.d fa0, fa1, fa1
+; RV64D-NEXT:    ret
+start:
+  %2 = fcmp olt double %0, %1
+  %3 = fcmp uno double %0, 0.000000e+00
+  %or.cond.i.i = or i1 %3, %2
+  %4 = select i1 %or.cond.i.i, double %1, double %0
+  %5 = tail call double @llvm.canonicalize.f64(double %4) #2
+  ret double %5
+}