[llvm] [DAG] foldShiftToAvg - Fixes avgceil[su] pattern matching for sub+xor form (PR #169199)

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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d9bbed3a3..1073cb425 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12029,9 +12029,10 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N, const SDLoc &DL) {
 // legal.
 // 	// If not, bail out to prevent incorrect folding at the wider type.
 // 	// This ensures operations like srhadd are generated at the correct
-// width. 	if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) { 		NarrowVT =
-// cast<VTSDNode>(N0->getOperand(0)->getOperand(1))->getVT(); 		if (Opcode ==
-// ISD::SRL && !TLI.isTypeLegal(NarrowVT)) 			return SDValue();
+// width. 	if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+// NarrowVT = cast<VTSDNode>(N0->getOperand(0)->getOperand(1))->getVT();
+// if (Opcode == ISD::SRL && !TLI.isTypeLegal(NarrowVT))
+// return SDValue();
 // 	}
 
 //   unsigned FloorISD = 0;
@@ -12084,7 +12085,8 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N, const SDLoc &DL) {
 
 // 		if (isAllOnesOrAllOnesSplat(Xor.getOperand(1)) ||
 // 			(ISD::isConstantSplatVector(Xor.getOperand(1).getNode(),
-// SplatVal) && 			SplatVal.trunc(VT.getScalarSizeInBits()).isAllOnes())) {
+// SplatVal) &&
+// SplatVal.trunc(VT.getScalarSizeInBits()).isAllOnes())) {
 // 				// - Can't fold if either op is
 // sign/zero-extended for SRL, as SRL
 // 				//   is unsigned, and shadd patterns are handled
@@ -12095,19 +12097,23 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N, const SDLoc &DL) {
 // 				//   into a series of EXTRACT_SUBVECTORs.
 // Folding each subvector does not
 // 				//   necessarily preserve semantics so they
-// cannot be folded here. 				if (TruncNode && VT.isFixedLengthVector()) { 					if
-// (X.getOpcode() == ISD::SIGN_EXTEND || 							X.getOpcode() == ISD::ZERO_EXTEND ||
-// 							Y.getOpcode() ==
-// ISD::SIGN_EXTEND || 							Y.getOpcode() == ISD::ZERO_EXTEND || VT.getSizeInBits() >
-// 128) 							return SDValue();
+// cannot be folded here. 				if (TruncNode &&
+// VT.isFixedLengthVector()) { 					if
+// (X.getOpcode() == ISD::SIGN_EXTEND ||
+// X.getOpcode() == ISD::ZERO_EXTEND || 							Y.getOpcode() == ISD::SIGN_EXTEND ||
+// Y.getOpcode() == ISD::ZERO_EXTEND || VT.getSizeInBits() > 128)
+// return SDValue();
 // 				}
 
 // 				// If there is no truncate user, ensure the
 // relevant no wrap flag is on
 // 				// the sub so that narrowing the widened result
-// is defined. 				if (Opcode == ISD::SRA && VT == NarrowVT) { 					if (!IsUnsigned &&
-// !Sub->getFlags().hasNoSignedWrap()) 						return SDValue(); 				} else if (IsUnsigned
-// && !Sub->getFlags().hasNoUnsignedWrap()) 					return SDValue();
+// is defined. 				if (Opcode == ISD::SRA && VT ==
+// NarrowVT) { 					if (!IsUnsigned &&
+// !Sub->getFlags().hasNoSignedWrap())
+// return SDValue(); 				} else if (IsUnsigned
+// && !Sub->getFlags().hasNoUnsignedWrap())
+// return SDValue();
 
 // 				// Only fold if the target supports avgceil[su]
 // at the truncated type:
@@ -12126,7 +12132,8 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N, const SDLoc &DL) {
 // support for the VT at the
 // 				// final observable type (TruncVT or VT).
 // 				if (TLI.isOperationLegalOrCustom(CeilISD,
-// TruncVT)) 					return DAG.getNode(CeilISD, DL, VT, Y, X);
+// TruncVT)) 					return DAG.getNode(CeilISD, DL,
+// VT, Y, X);
 // 			}
 // 	}
 
@@ -12214,8 +12221,8 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N, const SDLoc &DL) {
 // 			if ((N00.getOpcode() == ISD::SIGN_EXTEND_INREG ||
 // 					N00.getOpcode() == ISD::SIGN_EXTEND) ||
 // 					(N01.getOpcode() ==
-// ISD::SIGN_EXTEND_INREG || 					N01.getOpcode() == ISD::SIGN_EXTEND)) 				IsUnsigned =
-// false;
+// ISD::SIGN_EXTEND_INREG || 					N01.getOpcode()
+// == ISD::SIGN_EXTEND)) 				IsUnsigned = false;
 
 //     }
 //     FloorISD = (IsUnsigned ? ISD::AVGFLOORU : ISD::AVGFLOORS);

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https://github.com/llvm/llvm-project/pull/169199