[llvm] [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (PR #169182)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/169182

I think we need to keep the SelectionDAG code for volatile load/store so we should support 4 byte alignment when possible.

>From ba96277727cd45c98a74b29e5576db44d6408310 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 22 Nov 2025 10:33:51 -0800
Subject: [PATCH] [RISCV] Support zilsd-4byte-align for i64 load/store in
 SelectionDAG.

I think we need to keep the SelectionDAG code for volatile
load/store so we should support 4 byte alignment when possible.
---
 llvm/lib/Target/RISCV/RISCVSubtarget.h        | 7 +++++++
 llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp | 4 +---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 29df53c6c9893..b659bb96f2f11 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -237,6 +237,13 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 
     return 0;
   }
+
+  Align getZilsdAlign() const {
+    return Align(enableUnalignedScalarMem() ? 1
+                 : allowZilsd4ByteAlign()   ? 4
+                                            : 8);
+  }
+
   unsigned getELen() const {
     assert(hasVInstructions() && "Expected V extension");
     return hasVInstructionsI64() ? 64 : 32;
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 99e83fbb05a73..3b47903c351bf 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -146,9 +146,7 @@ bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
 
   // Check alignment: default is 8-byte, but allow 4-byte with tune feature
   // If unaligned scalar memory is enabled, allow any alignment
-  RequiredAlign = STI->enableUnalignedScalarMem() ? Align(1)
-                  : STI->allowZilsd4ByteAlign()   ? Align(4)
-                                                  : Align(8);
+  RequiredAlign = STI->getZilsdAlign();
   bool Modified = false;
   for (auto &MBB : MF) {
     Modified |= rescheduleLoadStoreInstrs(&MBB);