[llvm] [llvm][RISCV] Make X0 register pair legal in pre-ra pass (PR #169164)

[Brandon Wu via llvm-commits]

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/169164

>From 4e555583569d6c41ef4f451c9cef11611ea4cfb6 Mon Sep 17 00:00:00 2001
From: Brandon Wu <songwu0813 at gmail.com>
Date: Sat, 22 Nov 2025 06:09:16 -0800
Subject: [PATCH 1/2] [llvm][RISCV] Make X0 register pair legal in pre-ra pass

---
 llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp |  3 +-
 .../CodeGen/RISCV/zilsd-ldst-opt-prera.mir    | 38 +++++++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 99e83fbb05a73..480937df9c3df 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -209,9 +209,10 @@ bool RISCVPreAllocZilsdOpt::canFormLdSdPair(MachineInstr *MI0,
 
   // Check that the two destination/source registers are different for
   // load/store respectively.
+  // The only case two destinations/sources can be same is (x0, x0).
   Register FirstReg = MI0->getOperand(0).getReg();
   Register SecondReg = MI1->getOperand(0).getReg();
-  if (FirstReg == SecondReg)
+  if (FirstReg == SecondReg && FirstReg != RISCV::X0)
     return false;
 
   return true;
diff --git a/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir b/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
index dab394d4bc8c4..e5251736db45e 100644
--- a/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
+++ b/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
@@ -19,6 +19,13 @@
     ret void
   }
 
+  define void @basic_store_zero_combine(ptr %0, i32 %1, i32 %2) {
+    store i32 0, ptr %0, align 4
+    %4 = getelementptr inbounds i32, ptr %0, i32 1
+    store i32 0, ptr %4, align 4
+    ret void
+  }
+
   define i32 @basic_load_combine_8_byte_aligned(ptr %0) {
     %2 = load i32, ptr %0, align 8
     %3 = getelementptr inbounds i32, ptr %0, i32 1
@@ -310,6 +317,37 @@ body: |
     SW %2, %0, 4 :: (store (s32))
     PseudoRET
 
+...
+---
+# Basic case: two consecutive 32-bit store 0 that can be combined into SD
+name: basic_store_zero_combine
+alignment: 4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x10', virtual-reg: '%0' }
+body: |
+  bb.0:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: basic_store_zero_combine
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-NEXT: SW $x0, [[COPY]], 0 :: (store (s32))
+    ; CHECK-NEXT: SW $x0, [[COPY]], 4 :: (store (s32))
+    ; CHECK-NEXT: PseudoRET
+    ;
+    ; CHECK-4BYTE-LABEL: name: basic_store_zero_combine
+    ; CHECK-4BYTE: liveins: $x10
+    ; CHECK-4BYTE-NEXT: {{  $}}
+    ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT $x0, $x0, [[COPY]], 0 :: (store (s32))
+    ; CHECK-4BYTE-NEXT: PseudoRET
+    %0:gpr = COPY $x10
+    SW $x0, %0, 0 :: (store (s32))
+    SW $x0, %0, 4 :: (store (s32))
+    PseudoRET
+
 ...
 ---
 name: basic_load_combine_8_byte_aligned

>From e7334f8b3c431060fdeefdeeb87d3f7051d236a3 Mon Sep 17 00:00:00 2001
From: Brandon Wu <songwu0813 at gmail.com>
Date: Sat, 22 Nov 2025 10:10:30 -0800
Subject: [PATCH 2/2] fixup! X0 form

---
 llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp    | 14 ++++++++++++--
 llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir | 13 ++++++++-----
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 480937df9c3df..9724ea4256c32 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -209,11 +209,21 @@ bool RISCVPreAllocZilsdOpt::canFormLdSdPair(MachineInstr *MI0,
 
   // Check that the two destination/source registers are different for
   // load/store respectively.
-  // The only case two destinations/sources can be same is (x0, x0).
+  // The only case two destinations/sources can be same is (x0, x0). This pass
+  // is run before register coalescer so it will be the form of:
+  //   %0 = COPY $x0
+  //   SW %0, %ptr
+  // instead of:
+  //   SW $x0, %ptr
   Register FirstReg = MI0->getOperand(0).getReg();
   Register SecondReg = MI1->getOperand(0).getReg();
-  if (FirstReg == SecondReg && FirstReg != RISCV::X0)
+  if (FirstReg == SecondReg) {
+    const MachineInstr *FirstOpDefInst = MRI->getUniqueVRegDef(FirstReg);
+    if (FirstOpDefInst->isCopy() &&
+        FirstOpDefInst->getOperand(1).getReg() == RISCV::X0)
+      return true;
     return false;
+  }
 
   return true;
 }
diff --git a/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir b/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
index e5251736db45e..4433b4dc615ae 100644
--- a/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
+++ b/llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
@@ -333,19 +333,22 @@ body: |
     ; CHECK: liveins: $x10
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
-    ; CHECK-NEXT: SW $x0, [[COPY]], 0 :: (store (s32))
-    ; CHECK-NEXT: SW $x0, [[COPY]], 4 :: (store (s32))
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32))
+    ; CHECK-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32))
     ; CHECK-NEXT: PseudoRET
     ;
     ; CHECK-4BYTE-LABEL: name: basic_store_zero_combine
     ; CHECK-4BYTE: liveins: $x10
     ; CHECK-4BYTE-NEXT: {{  $}}
     ; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
-    ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT $x0, $x0, [[COPY]], 0 :: (store (s32))
+    ; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-4BYTE-NEXT: PseudoSD_RV32_OPT [[COPY1]], [[COPY1]], [[COPY]], 0 :: (store (s32))
     ; CHECK-4BYTE-NEXT: PseudoRET
     %0:gpr = COPY $x10
-    SW $x0, %0, 0 :: (store (s32))
-    SW $x0, %0, 4 :: (store (s32))
+    %1:gpr = COPY $x0
+    SW %1, %0, 0 :: (store (s32))
+    SW %1, %0, 4 :: (store (s32))
     PseudoRET
 
 ...