[llvm] [NVPTX] Use correct `mul.wide` operand type when matching on `shl` in `combineMulWide` (PR #168986)

[Artem Belevich via llvm-commits]

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@@ -5695,8 +5695,8 @@ static SDValue combineMulWide(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   SDValue RHS = Op.getOperand(1);
   if (Op.getOpcode() == ISD::SHL) {
     const auto ShiftAmt = Op.getConstantOperandVal(1);
-    const auto MulVal = APInt(ToVT.getSizeInBits(), 1) << ShiftAmt;
-    RHS = DCI.DAG.getConstant(MulVal, DL, ToVT);
+    const auto MulVal = APInt(FromVT.getSizeInBits(), 1) << ShiftAmt;
+    RHS = DCI.DAG.getConstant(MulVal, DL, FromVT);
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Artem-B wrote:

It would be great to add a test that would catch such a mismatch.

https://github.com/llvm/llvm-project/pull/168986