[llvm] [RISCV] Combine vslide{up,down} x, poison -> x (PR #169013)

[Philip Reames via llvm-commits]

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@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple riscv32 -mattr=+v < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+v < %s | FileCheck %s
+; RUN: llc -mtriple riscv32 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
+
+define <4 x i32> @splice_v4i32_slidedown(<4 x i32> %a, <4 x i32> %b) #0 {
+; CHECK-LABEL: splice_v4i32_slidedown:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vrgather.vi v9, v8, 3
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preames wrote:

OT: We should probably be preferring vslidedown.vi for case where we have a single element in the resulting shuffle mask.  vrgather.vi forces the use of an extra register where vslidedown.vi doesn't.  (This only works for vslidedown, vslideup does have the register constraint.)

https://github.com/llvm/llvm-project/pull/169013