[llvm] [RISCV] Combine vslide{up,down} x, poison -> x (PR #169013)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 21 00:03:06 PST 2025
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/169013
The motivation for this is that it would be useful to express a vslideup/vslidedown in a target independent way e.g. from the loop vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison, slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of the vs2s being poison. We can optimize this away so that we are just left with a single slideup/slidedown.
>From f22a1e23500b5e8ee17cf1e9d3aefd5a2e98ef1b Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 21 Nov 2025 15:53:46 +0800
Subject: [PATCH 1/2] Precommit tests
---
.../RISCV/rvv/fixed-vectors-vector-splice.ll | 49 +++++++++++++++++
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 52 +++++++++++++++++++
2 files changed, 101 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
new file mode 100644
index 0000000000000..42d1c0321cfd1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple riscv32 -mattr=+v < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+v < %s | FileCheck %s
+; RUN: llc -mtriple riscv32 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
+
+define <4 x i32> @splice_v4i32_slidedown(<4 x i32> %a, <4 x i32> %b) #0 {
+; CHECK-LABEL: splice_v4i32_slidedown:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vrgather.vi v9, v8, 3
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.vector.splice(<4 x i32> %a, <4 x i32> poison, i32 3)
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @splice_4i32_slideup(<4 x i32> %a) #0 {
+; CHECK-LABEL: splice_4i32_slideup:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vrgather.vi v9, v8, 0
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.vector.splice(<4 x i32> poison, <4 x i32> %a, i32 -3)
+ ret <4 x i32> %res
+}
+
+define <8 x i32> @splice_v8i32_slidedown(<8 x i32> %a, <8 x i32> %b) #0 {
+; CHECK-LABEL: splice_v8i32_slidedown:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: ret
+ %res = call <8 x i32> @llvm.vector.splice(<8 x i32> %a, <8 x i32> poison, i32 3)
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @splice_v8i32_slideup(<8 x i32> %a) #0 {
+; CHECK-LABEL: splice_v8i32_slideup:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 3
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %res = call <8 x i32> @llvm.vector.splice(<8 x i32> poison, <8 x i32> %a, i32 -3)
+ ret <8 x i32> %res
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index acc2a97dd5d1f..546cf1a1b141d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -4247,4 +4247,56 @@ define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a
ret <vscale x 8 x double> %res
}
+define <vscale x 2 x i32> @splice_nxv2i32_slidedown(<vscale x 2 x i32> %a) #0 {
+; NOVLDEP-LABEL: splice_nxv2i32_slidedown:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i32_slidedown:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -3
+; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vi v8, v8, 3
+; VLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
+; VLDEP-NEXT: ret
+ %res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> %a, <vscale x 2 x i32> poison, i32 3)
+ ret <vscale x 2 x i32> %res
+}
+
+define <vscale x 2 x i32> @splice_nxv2i32_slideup(<vscale x 2 x i32> %a) #0 {
+; NOVLDEP-LABEL: splice_nxv2i32_slideup:
+; NOVLDEP: # %bb.0:
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: srli a0, a0, 2
+; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; NOVLDEP-NEXT: vslidedown.vx v9, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v9, v8, 3
+; NOVLDEP-NEXT: vmv.v.v v8, v9
+; NOVLDEP-NEXT: ret
+;
+; VLDEP-LABEL: splice_nxv2i32_slideup:
+; VLDEP: # %bb.0:
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: srli a0, a0, 2
+; VLDEP-NEXT: addi a0, a0, -3
+; VLDEP-NEXT: vsetivli zero, 3, e32, m1, ta, ma
+; VLDEP-NEXT: vslidedown.vx v9, v8, a0
+; VLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; VLDEP-NEXT: vslideup.vi v9, v8, 3
+; VLDEP-NEXT: vmv.v.v v8, v9
+; VLDEP-NEXT: ret
+ %res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> poison, <vscale x 2 x i32> %a, i32 -3)
+ ret <vscale x 2 x i32> %res
+}
+
attributes #0 = { vscale_range(2,0) }
>From 12ac3337e5dbe93c55d76629186a42a95e380f4f Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 21 Nov 2025 15:54:47 +0800
Subject: [PATCH 2/2] [RISCV] Combine vslide{up,down} x, poison -> x
The motivation for this is that it would be useful to express a vslideup/vslidedown in a target independent way e.g. from the loop vectorizer.
We can do this today with @llvm.vector.splice by setting one operand to poison:
- A slide down can be achieved with @llvm.vector.splice(%x, poison, slideamt)
- A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt)
E.g.:
splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison>
splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a>
These splices get lowered to a vslideup + vslidedown pair with one of the vs2s being poison. We can optimize this away so that we are just left with a single slideup/slidedown.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 +++
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 34 ++++----------------
2 files changed, 11 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..209e2969046c9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21834,6 +21834,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return N->getOperand(0);
break;
}
+ case RISCVISD::VSLIDEDOWN_VL:
+ case RISCVISD::VSLIDEUP_VL:
+ if (N->getOperand(1)->isUndef())
+ return N->getOperand(0);
+ break;
case RISCVISD::VSLIDE1UP_VL:
case RISCVISD::VFSLIDE1UP_VL: {
using namespace SDPatternMatch;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index 546cf1a1b141d..31936d3a084b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -4252,10 +4252,6 @@ define <vscale x 2 x i32> @splice_nxv2i32_slidedown(<vscale x 2 x i32> %a) #0 {
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
-; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: srli a0, a0, 2
-; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv2i32_slidedown:
@@ -4265,36 +4261,18 @@ define <vscale x 2 x i32> @splice_nxv2i32_slidedown(<vscale x 2 x i32> %a) #0 {
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 3
-; VLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v9, a0
; VLDEP-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> %a, <vscale x 2 x i32> poison, i32 3)
ret <vscale x 2 x i32> %res
}
define <vscale x 2 x i32> @splice_nxv2i32_slideup(<vscale x 2 x i32> %a) #0 {
-; NOVLDEP-LABEL: splice_nxv2i32_slideup:
-; NOVLDEP: # %bb.0:
-; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: srli a0, a0, 2
-; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v9, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v9, v8, 3
-; NOVLDEP-NEXT: vmv.v.v v8, v9
-; NOVLDEP-NEXT: ret
-;
-; VLDEP-LABEL: splice_nxv2i32_slideup:
-; VLDEP: # %bb.0:
-; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: srli a0, a0, 2
-; VLDEP-NEXT: addi a0, a0, -3
-; VLDEP-NEXT: vsetivli zero, 3, e32, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vx v9, v8, a0
-; VLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; VLDEP-NEXT: vslideup.vi v9, v8, 3
-; VLDEP-NEXT: vmv.v.v v8, v9
-; VLDEP-NEXT: ret
+; CHECK-LABEL: splice_nxv2i32_slideup:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v9, v8, 3
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> poison, <vscale x 2 x i32> %a, i32 -3)
ret <vscale x 2 x i32> %res
}
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