[llvm] [ARM] Pattern match Low Overhead Loops pseudos (NFC) (PR #168209)

[Sergei Barannikov via llvm-commits]

s-barannikov wrote:

I can see that compared to before the patch, `t2WhileLoopSetup` has lost `MCID::UnmodeledSideEffects` flag.
I guess this has happened because ARM relies on guessing instruction properties from patterns, see `guessInstructionProperties` in `llvm/include/llvm/Target.td`.

The first difference in MIR can be observed after `MachineCSE` -- it CSEd two `t2WhileLoopSetup` instructions.
At the time ARMBlockPlacement pass is executed, the function differs significantly from what it looked like before the patch. In particular, there is `t2WhileLoopStart` instead of `t2WhileLoopStartLR`.

Here is the implementation of `getWhileLoopStartTargetBB()`:
```
// Return the TargetBB stored in a t2WhileLoopStartLR/t2WhileLoopStartTP.
inline MachineBasicBlock *getWhileLoopStartTargetBB(const MachineInstr &MI) {
  assert(isWhileLoopStart(MI) && "Expected WhileLoopStart!");
  unsigned Op = MI.getOpcode() == ARM::t2WhileLoopStartTP ? 3 : 2;
  return MI.getOperand(Op).getMBB();
}
```

It expects basic block as the operand 2 of both `t2WhileLoopStart` and `t2WhileLoopStartLR`. This is correct for the LR version and wrong for non-LR version -- it should be operand 1. However, according to the comment near `t2WhileLoopStart`, this instruction shouldn't have survived this far. I guess CSEing `t2WhileLoopSetup` broke the pattern transforming `t2WhileLoopStart` into the LR version.


https://github.com/llvm/llvm-project/pull/168209