[llvm] [PowerPC] cost modeling for length type VP intrinsic load/store (PR #168938)
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Thu Nov 20 11:53:29 PST 2025
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git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index f17a7a873..dadf84b1d 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1084,7 +1084,7 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {
}
bool PPCTTIImpl::hasActiveVectorLength() const {
- unsigned CPU = ST->getCPUDirective();
+ unsigned CPU = ST->getCPUDirective();
if (!PPCEVL)
return false;
if (CPU == PPC::DIR_PWR10 || CPU == PPC::DIR_PWR_FUTURE ||
@@ -1094,8 +1094,7 @@ bool PPCTTIImpl::hasActiveVectorLength() const {
}
static inline bool isLegalLoadWithLengthType(EVT VT) {
- if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
- VT != MVT::i8)
+ if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
return false;
return true;
}
@@ -1116,12 +1115,10 @@ bool PPCTTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment,
InstructionCost
PPCTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy,
- Align Alignment,
- unsigned AddressSpace,
+ Align Alignment, unsigned AddressSpace,
TTI::TargetCostKind CostKind) const {
- InstructionCost BaseCost =
- BaseT::getMaskedMemoryOpCost(Opcode, DataTy, Alignment, AddressSpace,
- CostKind);
+ InstructionCost BaseCost = BaseT::getMaskedMemoryOpCost(
+ Opcode, DataTy, Alignment, AddressSpace, CostKind);
if (Opcode != Instruction::Load && Opcode != Instruction::Store)
return BaseCost;
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https://github.com/llvm/llvm-project/pull/168938
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