[llvm] [RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type profile. NFC (PR #168932)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This removes an unnecessary isel pattern for the RV32 HwMode.

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Full diff: https://github.com/llvm/llvm-project/pull/168932.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 764e3c9c58355..51339d66f6de1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1461,7 +1461,7 @@ let Predicates = [HasStdExtP, IsRV32] in {
 // Codegen patterns
 //===----------------------------------------------------------------------===//
 
-def riscv_absw : RVSDNode<"ABSW", SDTIntUnaryOp>;
+def riscv_absw : RVSDNode<"ABSW", SDT_RISCVIntUnaryOpW>;
 
 def SDT_RISCVPASUB : SDTypeProfile<1, 2, [SDTCisVec<0>,
                                           SDTCisInt<0>,

``````````

</details>


https://github.com/llvm/llvm-project/pull/168932