[llvm] [RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type profile. NFC (PR #168932)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/168932

This removes an unnecessary pattern for the RV32 HwMode.

>From bf795aef63a066612f3d75e1c36751ca151eb2d7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 20 Nov 2025 10:49:12 -0800
Subject: [PATCH] [RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type
 profile.

This removes an unnecessary pattern for the RV32 HwMode.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 764e3c9c58355..51339d66f6de1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1461,7 +1461,7 @@ let Predicates = [HasStdExtP, IsRV32] in {
 // Codegen patterns
 //===----------------------------------------------------------------------===//
 
-def riscv_absw : RVSDNode<"ABSW", SDTIntUnaryOp>;
+def riscv_absw : RVSDNode<"ABSW", SDT_RISCVIntUnaryOpW>;
 
 def SDT_RISCVPASUB : SDTypeProfile<1, 2, [SDTCisVec<0>,
                                           SDTCisInt<0>,