[llvm] [ISel] Introduce llvm.clmul intrinsic (PR #168731)

[Piotr Fusik via llvm-commits]

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@@ -10315,6 +10315,25 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N) {
   if (SDValue R = combineShiftOfShiftedLogic(N, DAG))
     return R;
 
+  // Fold clmul(zext(x), zext(y)) >> (BW - 1 | BW) -> clmul(r|h)(x, y).
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
+  SDValue X, Y;
+  if (sd_match(N, m_Srl(m_Clmul(m_ZExt(m_Value(X)), m_ZExt(m_Value(Y))),
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pfusik wrote:

Are the ZEXTs here guaranteed to be from half the VT width types?

https://github.com/llvm/llvm-project/pull/168731