[llvm] [AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned (PR #160547)

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f33c2365c..fbdb14ebe 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2132,8 +2132,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
 
     const MCInstrDesc &Mov64Desc = get(AMDGPU::V_MOV_B64_e32);
-    const TargetRegisterClass *Mov64RC =
-        getRegClass(Mov64Desc, /*OpNum=*/0);
+    const TargetRegisterClass *Mov64RC = getRegClass(Mov64Desc, /*OpNum=*/0);
 
     const MachineOperand &SrcOp = MI.getOperand(1);
     // FIXME: Will this work for 64-bit floating point immediates?
@@ -2149,8 +2148,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       APInt Lo(32, Imm.getLoBits(32).getZExtValue());
       APInt Hi(32, Imm.getHiBits(32).getZExtValue());
       const MCInstrDesc &PkMovDesc = get(AMDGPU::V_PK_MOV_B32);
-      const TargetRegisterClass *PkMovRC =
-          getRegClass(PkMovDesc, /*OpNum=*/0);
+      const TargetRegisterClass *PkMovRC = getRegClass(PkMovDesc, /*OpNum=*/0);
 
       if (ST.hasPkMovB32() && Lo == Hi && isInlineConstant(Lo) &&
           PkMovRC->contains(Dst)) {

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https://github.com/llvm/llvm-project/pull/160547