[llvm] [AMDGPU] Prioritize allocation of low 256 VGPR classes (PR #167978)

[Quentin Colombet via llvm-commits]

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@@ -501,6 +501,17 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
 
   SmallVector<StringLiteral>
   getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
+
+  float
+  getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override {
+    // Prioritize VGPR_32_Lo256 over other classes which may occupy registers
+    // beyond v256.
+    return AMDGPUGenRegisterInfo::getSpillWeightScaleFactor(RC) *
+           ((RC == &AMDGPU::VGPR_32_Lo256RegClass ||
+             RC == &AMDGPU::VReg_64_Lo256_Align2RegClass)
+                ? 2.0
+                : 1.0);
+  }
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qcolombet wrote:

I'm not too thrilled about the "fix", but I understand what we're conveying here.
I don't have a good alternative at the moment.
I let Matt decide, for me that's a good workaround.

https://github.com/llvm/llvm-project/pull/167978