[llvm] ac68dd5 - [RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 18 22:51:23 PST 2025
Author: Alex Bradbury
Date: 2025-11-19T06:51:18Z
New Revision: ac68dd53ed035047fb68abb471d2e1eb8b31cbfd
URL: https://github.com/llvm/llvm-project/commit/ac68dd53ed035047fb68abb471d2e1eb8b31cbfd
DIFF: https://github.com/llvm/llvm-project/commit/ac68dd53ed035047fb68abb471d2e1eb8b31cbfd.diff
LOG: [RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
As suggested in the review for #160536 it would be good to follow up and
port the RISC-V passes to the new pass manager. This PR starts that
task. It provides the bare minimum necessary to run RISCVCodeGenPrepare
with opt -passes=riscv-codegenprepare. The approach used is modeled on
my observations of the AMDGPU backend and the recent work to port the
X86 passes.
The testing approach is to add a `-passes=riscv-foo` RUN line to at
least one test, if an appropriate test exists.
Added:
llvm/lib/Target/RISCV/RISCVPassRegistry.def
Modified:
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 51e8e8574ed15..938c62e4f9f94 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -26,8 +26,16 @@ class RISCVRegisterBankInfo;
class RISCVSubtarget;
class RISCVTargetMachine;
-FunctionPass *createRISCVCodeGenPreparePass();
-void initializeRISCVCodeGenPreparePass(PassRegistry &);
+class RISCVCodeGenPreparePass : public PassInfoMixin<RISCVCodeGenPreparePass> {
+private:
+ const RISCVTargetMachine *TM;
+
+public:
+ RISCVCodeGenPreparePass(const RISCVTargetMachine *TM) : TM(TM) {}
+ PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+};
+FunctionPass *createRISCVCodeGenPrepareLegacyPass();
+void initializeRISCVCodeGenPrepareLegacyPassPass(PassRegistry &);
FunctionPass *createRISCVDeadRegisterDefinitionsPass();
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
index ce349598bd9b1..ab450f9c4a61d 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
@@ -33,20 +33,33 @@ using namespace llvm;
#define PASS_NAME "RISC-V CodeGenPrepare"
namespace {
-
-class RISCVCodeGenPrepare : public FunctionPass,
- public InstVisitor<RISCVCodeGenPrepare, bool> {
+class RISCVCodeGenPrepare : public InstVisitor<RISCVCodeGenPrepare, bool> {
+ Function &F;
const DataLayout *DL;
const DominatorTree *DT;
const RISCVSubtarget *ST;
+public:
+ RISCVCodeGenPrepare(Function &F, const DominatorTree *DT,
+ const RISCVSubtarget *ST)
+ : F(F), DL(&F.getDataLayout()), DT(DT), ST(ST) {}
+ bool run();
+ bool visitInstruction(Instruction &I) { return false; }
+ bool visitAnd(BinaryOperator &BO);
+ bool visitIntrinsicInst(IntrinsicInst &I);
+ bool expandVPStrideLoad(IntrinsicInst &I);
+ bool widenVPMerge(IntrinsicInst &I);
+};
+} // namespace
+
+namespace {
+class RISCVCodeGenPrepareLegacyPass : public FunctionPass {
public:
static char ID;
- RISCVCodeGenPrepare() : FunctionPass(ID) {}
+ RISCVCodeGenPrepareLegacyPass() : FunctionPass(ID) {}
bool runOnFunction(Function &F) override;
-
StringRef getPassName() const override { return PASS_NAME; }
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -54,15 +67,8 @@ class RISCVCodeGenPrepare : public FunctionPass,
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<TargetPassConfig>();
}
-
- bool visitInstruction(Instruction &I) { return false; }
- bool visitAnd(BinaryOperator &BO);
- bool visitIntrinsicInst(IntrinsicInst &I);
- bool expandVPStrideLoad(IntrinsicInst &I);
- bool widenVPMerge(IntrinsicInst &I);
};
-
-} // end anonymous namespace
+} // namespace
// Try to optimize (i64 (and (zext/sext (i32 X), C1))) if C1 has bit 31 set,
// but bits 63:32 are zero. If we know that bit 31 of X is 0, we can fill
@@ -273,17 +279,7 @@ bool RISCVCodeGenPrepare::expandVPStrideLoad(IntrinsicInst &II) {
return true;
}
-bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
- if (skipFunction(F))
- return false;
-
- auto &TPC = getAnalysis<TargetPassConfig>();
- auto &TM = TPC.getTM<RISCVTargetMachine>();
- ST = &TM.getSubtarget<RISCVSubtarget>(F);
-
- DL = &F.getDataLayout();
- DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-
+bool RISCVCodeGenPrepare::run() {
bool MadeChange = false;
for (auto &BB : F)
for (Instruction &I : llvm::make_early_inc_range(BB))
@@ -292,12 +288,40 @@ bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
return MadeChange;
}
-INITIALIZE_PASS_BEGIN(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
+bool RISCVCodeGenPrepareLegacyPass::runOnFunction(Function &F) {
+ if (skipFunction(F))
+ return false;
+
+ auto &TPC = getAnalysis<TargetPassConfig>();
+ auto &TM = TPC.getTM<RISCVTargetMachine>();
+ auto ST = &TM.getSubtarget<RISCVSubtarget>(F);
+ auto DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
+
+ RISCVCodeGenPrepare RVCGP(F, DT, ST);
+ return RVCGP.run();
+}
+
+INITIALIZE_PASS_BEGIN(RISCVCodeGenPrepareLegacyPass, DEBUG_TYPE, PASS_NAME,
+ false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
-INITIALIZE_PASS_END(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
+INITIALIZE_PASS_END(RISCVCodeGenPrepareLegacyPass, DEBUG_TYPE, PASS_NAME, false,
+ false)
-char RISCVCodeGenPrepare::ID = 0;
+char RISCVCodeGenPrepareLegacyPass::ID = 0;
+
+FunctionPass *llvm::createRISCVCodeGenPrepareLegacyPass() {
+ return new RISCVCodeGenPrepareLegacyPass();
+}
-FunctionPass *llvm::createRISCVCodeGenPreparePass() {
- return new RISCVCodeGenPrepare();
+PreservedAnalyses RISCVCodeGenPreparePass::run(Function &F,
+ FunctionAnalysisManager &FAM) {
+ DominatorTree *DT = &FAM.getResult<DominatorTreeAnalysis>(F);
+ auto ST = &TM->getSubtarget<RISCVSubtarget>(F);
+ bool Changed = RISCVCodeGenPrepare(F, DT, ST).run();
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ PreservedAnalyses PA = PreservedAnalyses::none();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
}
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
new file mode 100644
index 0000000000000..29ccf2cff1ca5
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -0,0 +1,20 @@
+//===- RISCVPassRegistry.def - Registry of RISC-V passes --------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is used as the registry of passes that are part of the RISC-V
+// backend.
+//
+//===----------------------------------------------------------------------===//
+
+// NOTE: NO INCLUDE GUARD DESIRED!
+
+#ifndef FUNCTION_PASS
+#define FUNCTION_PASS(NAME, CREATE_PASS)
+#endif
+FUNCTION_PASS("riscv-codegenprepare", RISCVCodeGenPreparePass(this))
+#undef FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 911bd7ee2876f..8f6c0af5de3b4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -123,7 +123,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVLateBranchOptPass(*PR);
initializeRISCVMakeCompressibleOptPass(*PR);
initializeRISCVGatherScatterLoweringPass(*PR);
- initializeRISCVCodeGenPreparePass(*PR);
+ initializeRISCVCodeGenPrepareLegacyPassPass(*PR);
initializeRISCVPostRAExpandPseudoPass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVOptWInstrsPass(*PR);
@@ -461,7 +461,7 @@ void RISCVPassConfig::addIRPasses() {
addPass(createRISCVGatherScatterLoweringPass());
addPass(createInterleavedAccessPass());
- addPass(createRISCVCodeGenPreparePass());
+ addPass(createRISCVCodeGenPrepareLegacyPass());
}
TargetPassConfig::addIRPasses();
@@ -636,6 +636,9 @@ bool RISCVPassConfig::addILPOpts() {
}
void RISCVTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
+#define GET_PASS_REGISTRY "RISCVPassRegistry.def"
+#include "llvm/Passes/TargetPassRegistry.inc"
+
PB.registerLateLoopOptimizationsEPCallback([=](LoopPassManager &LPM,
OptimizationLevel Level) {
if (Level != OptimizationLevel::O0)
diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
index cf5d0f107359a..c25e337777631 100644
--- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -S -riscv-codegenprepare -mtriple=riscv64 | FileCheck %s
+; RUN: opt %s -S -passes=riscv-codegenprepare -mtriple=riscv64 | FileCheck %s
; Make sure we convert the 4294967294 in for.body.preheader.new to -2 based on
; the upper 33 bits being zero by the dominating condition %cmp3.
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