[llvm] [RISCV] Properly lower multiply-accumulate chains containing a constant (PR #168660)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,146 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s
+
+define i32 @madd_scalar(i32 %m00, i32 %m01, i32 %m10, i32 %m11) nounwind {
+; CHECK-LABEL: madd_scalar:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    mul a1, a2, a3
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    addiw a0, a0, 32
+; CHECK-NEXT:    ret
+entry:
+  %mul0 = mul nsw i32 %m00, %m01
+  %mul1 = mul nsw i32 %m10, %m11
+  %add0 = add i32 %mul0, 32
+  %add1 = add i32 %add0, %mul1
+  ret i32 %add1
+}
+
+define <8 x i32> @vmadd_non_constant(<8 x i32> %m00, <8 x i32> %m01, <8 x i32> %m10, <8 x i32> %m11, <8 x i32> %addend) {
+; CHECK-LABEL: vmadd_non_constant:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vmadd.vv v8, v10, v16
+; CHECK-NEXT:    vmacc.vv v8, v14, v12
+; CHECK-NEXT:    ret
+entry:
+  %mul0 = mul nsw <8 x i32> %m00, %m01
+  %mul1 = mul nsw <8 x i32> %m10, %m11
+  %add0 = add <8 x i32> %mul0, %addend
+  %add1 = add <8 x i32> %add0, %mul1
+  ret <8 x i32> %add1
+}
+
+define <vscale x 1 x i32> @vmadd_vscale_no_chain(<vscale x 1 x i32> %m00, <vscale x 1 x i32> %m01) {
+; CHECK-LABEL: vmadd_vscale_no_chain:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vmadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+entry:
+  %vset = tail call i32 @llvm.experimental.get.vector.length.i64(i64 8, i32 1, i1 true)
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topperc wrote:

The `vset` instruction is dead.

https://github.com/llvm/llvm-project/pull/168660