[llvm] [AArch64] Fold scalar-to-vector shuffles into DUP/FMOV (PR #166962)

[via llvm-commits]

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@@ -15666,6 +15654,56 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
     }
   }
 
+  // 128-bit NEON integer vectors:
+  // If BUILD_VECTOR has low half == splat(lane 0) and high half == zero,
+  // build the low half and return SUBREG_TO_REG(0, Lo, dsub).
+  // This avoids INSERT_VECTOR_ELT chains and lets later passes assume the
+  // other lanes are zero.
+  if (VT.isFixedLengthVector() && VT.getSizeInBits() == 128) {
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CarolineConcatto wrote:

Will this work if it is 64 bits vector? Is it valid to have the same for 64 bits vector?

https://github.com/llvm/llvm-project/pull/166962