[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)

[Simon Wallis via llvm-commits]

================
@@ -1790,10 +1817,11 @@ def : InstRW<[N3Write_5c_1M0_1V], (instregex "^INDEX_(IR|RI|RR)_D$")>;
 // Logical
 def : InstRW<[N3Write_2c_1V],
              (instregex "^(AND|EOR|ORR)_ZI",
-                        "^(AND|BIC|EOR|ORR)_ZZZ",
+                        "^(AND|BIC|EOR)_ZZZ",
                         "^EOR(BT|TB)_ZZZ_[BHSD]",
                         "^(AND|BIC|EOR|NOT|ORR)_(ZPmZ|ZPZZ)_[BHSD]",
                         "^NOT_ZPmZ_[BHSD]")>;
+def : InstRW<[N3Write_0or2c_1V], (instregex "^ORR_ZZZ")>;
----------------
simonwallis2 wrote:

Done

https://github.com/llvm/llvm-project/pull/165690