[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_IS_FPCLASS (PR #167575)

[Petar Avramovic via llvm-commits]

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@@ -30,58 +30,132 @@ define amdgpu_kernel void @sgpr_isnan_f32(ptr addrspace(1) %out, float %x) {
 ; GFX7GLISEL-NEXT:    s_mov_b32 s2, -1
 ; GFX7GLISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7GLISEL-NEXT:    v_cmp_class_f32_e64 s[4:5], s3, 3
-; GFX7GLISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
+; GFX7GLISEL-NEXT:    s_or_b64 s[4:5], s[4:5], s[4:5]
+; GFX7GLISEL-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX7GLISEL-NEXT:    s_and_b32 s3, s3, 1
+; GFX7GLISEL-NEXT:    s_cmp_lg_u32 s3, 0
+; GFX7GLISEL-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX7GLISEL-NEXT:    v_mov_b32_e32 v0, s3
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petar-avramovic wrote:

There are some code size regressions because of use of sgprs but it is not an obvious fix, need to decide when to move salu instruction to valu.
Can you add FixMe comment in both tests about code size regression.

https://github.com/llvm/llvm-project/pull/167575