[llvm] 21e0b56 - [AArch64][GlobalISel] Add basic GISel test coverage for lround and llround. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 17 11:47:41 PST 2025
Author: David Green
Date: 2025-11-17T19:47:36Z
New Revision: 21e0b56d7afc2f1af0ad5b728fcc039bfe1d37ff
URL: https://github.com/llvm/llvm-project/commit/21e0b56d7afc2f1af0ad5b728fcc039bfe1d37ff
DIFF: https://github.com/llvm/llvm-project/commit/21e0b56d7afc2f1af0ad5b728fcc039bfe1d37ff.diff
LOG: [AArch64][GlobalISel] Add basic GISel test coverage for lround and llround. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
llvm/test/CodeGen/AArch64/llround-conv.ll
llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
llvm/test/CodeGen/AArch64/lround-conv.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/llround-conv-fp16.ll b/llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
index 4bf65e7d6fd08..cb042757a4a42 100644
--- a/llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
+++ b/llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
@@ -1,6 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-NOFP16,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
define i16 @testmhhs(half %x) {
; CHECK-NOFP16-LABEL: testmhhs:
@@ -55,5 +61,3 @@ entry:
%0 = tail call i64 @llvm.llround.i64.f16(half %x)
ret i64 %0
}
-
-declare i64 @llvm.llround.i64.f16(half) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/llround-conv.ll b/llvm/test/CodeGen/AArch64/llround-conv.ll
index 797136037f0e9..4cc089804ce97 100644
--- a/llvm/test/CodeGen/AArch64/llround-conv.ll
+++ b/llvm/test/CodeGen/AArch64/llround-conv.ll
@@ -1,60 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmswl
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll
-; CHECK-LABEL: testmsws:
-; CHECK: fcvtas x0, s0
-; CHECK: ret
define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, s0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
- %0 = tail call i64 @llvm.llround.f32(float %x)
+ %0 = tail call i64 @llvm.llround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxs:
-; CHECK: fcvtas x0, s0
-; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, s0
+; CHECK-NEXT: ret
entry:
- %0 = tail call i64 @llvm.llround.f32(float %x)
+ %0 = tail call i64 @llvm.llround.i64.f32(float %x)
ret i64 %0
}
-; CHECK-LABEL: testmswd:
-; CHECK: fcvtas x0, d0
-; CHECK: ret
define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, d0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
- %0 = tail call i64 @llvm.llround.f64(double %x)
+ %0 = tail call i64 @llvm.llround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxd:
-; CHECK: fcvtas x0, d0
-; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, d0
+; CHECK-NEXT: ret
entry:
- %0 = tail call i64 @llvm.llround.f64(double %x)
+ %0 = tail call i64 @llvm.llround.i64.f64(double %x)
ret i64 %0
}
-; CHECK-LABEL: testmswl:
-; CHECK: bl llroundl
define i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl llroundl
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
- %0 = tail call i64 @llvm.llround.f128(fp128 %x)
+ %0 = tail call i64 @llvm.llround.i64.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsll:
-; CHECK: b llroundl
define i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: b llroundl
entry:
- %0 = tail call i64 @llvm.llround.f128(fp128 %x)
+ %0 = tail call i64 @llvm.llround.i64.f128(fp128 %x)
ret i64 %0
}
-
-declare i64 @llvm.llround.f32(float) nounwind readnone
-declare i64 @llvm.llround.f64(double) nounwind readnone
-declare i64 @llvm.llround.f128(fp128) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/lround-conv-fp16.ll b/llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
index bf78fd456eac0..a29dea0eb9f9f 100644
--- a/llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
+++ b/llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
@@ -1,6 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-NOFP16,CHECK-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
define i16 @testmhhs(half %x) {
; CHECK-NOFP16-LABEL: testmhhs:
@@ -55,5 +61,3 @@ entry:
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
ret i64 %0
}
-
-declare i64 @llvm.lround.i64.f16(half) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/lround-conv.ll b/llvm/test/CodeGen/AArch64/lround-conv.ll
index 678d3149f20cc..0bf82b538e70c 100644
--- a/llvm/test/CodeGen/AArch64/lround-conv.ll
+++ b/llvm/test/CodeGen/AArch64/lround-conv.ll
@@ -1,60 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmswl
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll
-; CHECK-LABEL: testmsws:
-; CHECK: fcvtas x0, s0
-; CHECK: ret
define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, s0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxs:
-; CHECK: fcvtas x0, s0
-; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
ret i64 %0
}
-; CHECK-LABEL: testmswd:
-; CHECK: fcvtas x0, d0
-; CHECK: ret
define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, d0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxd:
-; CHECK: fcvtas x0, d0
-; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtas x0, d0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
ret i64 %0
}
-; CHECK-LABEL: testmswl:
-; CHECK: bl lroundl
define i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl lroundl
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsll:
-; CHECK: b lroundl
define i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: b lroundl
entry:
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
ret i64 %0
}
-
-declare i64 @llvm.lround.i64.f32(float) nounwind readnone
-declare i64 @llvm.lround.i64.f64(double) nounwind readnone
-declare i64 @llvm.lround.i64.f128(fp128) nounwind readnone
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