[llvm] [RISCV] tt-ascalon-d8 vector scheduling (PR #167066)

[Petr Penzin via llvm-commits]

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@@ -0,0 +1,1009 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
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ppenzin wrote:

Addressed

https://github.com/llvm/llvm-project/pull/167066