[llvm] [AArch64][GlobalISel] Added support for hadd family of intrinsics (PR #163985)
Joshua Rodriguez via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 18 06:05:17 PST 2025
https://github.com/JoshdRod updated https://github.com/llvm/llvm-project/pull/163985
>From d4fd27582fa9d428911d56deff26131917b33661 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 16 Oct 2025 15:47:02 +0000
Subject: [PATCH 01/18] [AArch64][GlobalISel] Added uhadd intrinsic support
GlobalISel now selects uhadd intrinsic, without falling back to SDAG.
Note that GlobalISel-generated code involving uhadd seems to be inefficent when compared to SDAG.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 8 ++++++
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 ++
llvm/test/CodeGen/AArch64/freeze.ll | 25 +++++++++++++------
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 30b7b03f7a69a..a80390011f986 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -239,6 +239,12 @@ def G_USDOT : AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_UHADD : AArch64GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type1:$src2);
+ let hasSideEffects = 0;
+}
+
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
// expands into BSL/BIT/BIF after register allocation.
def G_BSP : AArch64GenericInstruction {
@@ -286,6 +292,8 @@ def : GINodeEquiv<G_UDOT, AArch64udot>;
def : GINodeEquiv<G_SDOT, AArch64sdot>;
def : GINodeEquiv<G_USDOT, AArch64usdot>;
+def : GINodeEquiv<G_UHADD, avgflooru>;
+
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
def : GINodeEquiv<G_AARCH64_PREFETCH, AArch64Prefetch>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 5f93847bc680e..44ed11c396dbd 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1817,6 +1817,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return LowerBinOp(TargetOpcode::G_ABDS);
case Intrinsic::aarch64_neon_uabd:
return LowerBinOp(TargetOpcode::G_ABDU);
+ case Intrinsic::aarch64_neon_uhadd:
+ return LowerBinOp(AArch64::G_UHADD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index fb909fec90434..f5e2ffd7361ce 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,7 +3,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_uhadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_urhadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_shadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_srhadd
@@ -435,13 +434,23 @@ define <8 x i16> @freeze_abds(<8 x i16> %a, <8 x i16> %b) {
}
define <8 x i16> @freeze_uhadd(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: freeze_uhadd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.8h, #15
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_uhadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v2.8h, #15
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_uhadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.8h, #15
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: movi v2.8h, #31
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%m0 = and <8 x i16> %a0, splat (i16 15)
%m1 = and <8 x i16> %a1, splat (i16 15)
%avg = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
>From 279919cf16fbcba23dd8e9f7849076cb0cc744ee Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Fri, 17 Oct 2025 13:13:22 +0000
Subject: [PATCH 02/18] [AArch64][GlobalISel] Added urhadd intrinsic support
GlobalISel now selects urhadd intrinsic, without falling back to SDAG.
Note that GlobalISel-generated code involving urhadd seems to be inefficent when compared to SDAG.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 7 ++++++
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 ++
llvm/test/CodeGen/AArch64/freeze.ll | 25 +++++++++++++------
3 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index a80390011f986..68f921e030429 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -245,6 +245,12 @@ def G_UHADD : AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_URHADD : AArch64GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type1:$src2);
+ let hasSideEffects = 0;
+}
+
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
// expands into BSL/BIT/BIF after register allocation.
def G_BSP : AArch64GenericInstruction {
@@ -293,6 +299,7 @@ def : GINodeEquiv<G_SDOT, AArch64sdot>;
def : GINodeEquiv<G_USDOT, AArch64usdot>;
def : GINodeEquiv<G_UHADD, avgflooru>;
+def : GINodeEquiv<G_URHADD, avgceilu>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 44ed11c396dbd..f579c6f5ba091 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1819,6 +1819,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return LowerBinOp(TargetOpcode::G_ABDU);
case Intrinsic::aarch64_neon_uhadd:
return LowerBinOp(AArch64::G_UHADD);
+ case Intrinsic::aarch64_neon_urhadd:
+ return LowerBinOp(AArch64::G_URHADD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index f5e2ffd7361ce..e2ae046da1467 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,7 +3,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_urhadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_shadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_srhadd
@@ -460,13 +459,23 @@ define <8 x i16> @freeze_uhadd(<8 x i16> %a0, <8 x i16> %a1) {
}
define <8 x i16> @freeze_urhadd(<8 x i16> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: freeze_urhadd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.8h, #15
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_urhadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v2.8h, #15
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_urhadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.8h, #15
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: movi v2.8h, #31
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%m0 = and <8 x i16> %a0, splat (i16 15)
%m1 = and <8 x i16> %a1, splat (i16 15)
%avg = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
>From faf2d20728f9cf3fdb9ba16fdd8ca601511caa66 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Fri, 17 Oct 2025 15:06:58 +0000
Subject: [PATCH 03/18] [AArch64][GlobalISel] Added shadd intrinsic support
GlobalISel now selects shadd intrinsic, without falling back to SDAG. Note
that GlobalISel-generated code involving shadd seems to be inefficent when
compared to SDAG.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 7 ++++++
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 ++
llvm/test/CodeGen/AArch64/freeze.ll | 22 +++++++++++++------
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 68f921e030429..2c2c403d96d72 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -251,6 +251,12 @@ def G_URHADD : AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_SHADD : AArch64GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type1:$src2);
+ let hasSideEffects = 0;
+}
+
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
// expands into BSL/BIT/BIF after register allocation.
def G_BSP : AArch64GenericInstruction {
@@ -300,6 +306,7 @@ def : GINodeEquiv<G_USDOT, AArch64usdot>;
def : GINodeEquiv<G_UHADD, avgflooru>;
def : GINodeEquiv<G_URHADD, avgceilu>;
+def : GINodeEquiv<G_SHADD, avgfloors>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index f579c6f5ba091..14f592b895c9e 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1821,6 +1821,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return LowerBinOp(AArch64::G_UHADD);
case Intrinsic::aarch64_neon_urhadd:
return LowerBinOp(AArch64::G_URHADD);
+ case Intrinsic::aarch64_neon_shadd:
+ return LowerBinOp(AArch64::G_SHADD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index e2ae046da1467..dffd89143d16b 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,7 +3,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_shadd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_srhadd
%struct.T = type { i32, i32 }
@@ -485,12 +484,21 @@ define <8 x i16> @freeze_urhadd(<8 x i16> %a0, <8 x i16> %a1) {
}
define <8 x i16> @freeze_shadd(<8 x i8> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: freeze_shadd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: sshr v1.8h, v1.8h, #8
-; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_shadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #8
+; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_shadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshr v1.8h, v1.8h, #8
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
+; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #8
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = ashr <8 x i16> %a1, splat (i16 8)
%avg = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
>From 701522aa4ff39827737b89af902131cd591da5c0 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Fri, 17 Oct 2025 15:46:32 +0000
Subject: [PATCH 04/18] [AArch64][GlobalISel] Added srhadd intrinsic support
GlobalISel now selects srhadd intrinsic, without falling back to SDAG. Note
that GlobalISel-generated code involving uhadd seems to be inefficent when
compared to SDAG.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 7 ++++++
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 ++
llvm/test/CodeGen/AArch64/freeze.ll | 22 +++++++++++++------
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 2c2c403d96d72..e44e31845380a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -257,6 +257,12 @@ def G_SHADD : AArch64GenericInstruction {
let hasSideEffects = 0;
}
+def G_SRHADD : AArch64GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type1:$src2);
+ let hasSideEffects = 0;
+}
+
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
// expands into BSL/BIT/BIF after register allocation.
def G_BSP : AArch64GenericInstruction {
@@ -307,6 +313,7 @@ def : GINodeEquiv<G_USDOT, AArch64usdot>;
def : GINodeEquiv<G_UHADD, avgflooru>;
def : GINodeEquiv<G_URHADD, avgceilu>;
def : GINodeEquiv<G_SHADD, avgfloors>;
+def : GINodeEquiv<G_SRHADD, avgceils>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 14f592b895c9e..c8d31bbbc8b9a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1823,6 +1823,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return LowerBinOp(AArch64::G_URHADD);
case Intrinsic::aarch64_neon_shadd:
return LowerBinOp(AArch64::G_SHADD);
+ case Intrinsic::aarch64_neon_srhadd:
+ return LowerBinOp(AArch64::G_SRHADD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index dffd89143d16b..136ac8b0a2aa1 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,7 +3,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_srhadd
%struct.T = type { i32, i32 }
@@ -509,12 +508,21 @@ define <8 x i16> @freeze_shadd(<8 x i8> %a0, <8 x i16> %a1) {
}
define <8 x i16> @freeze_srhadd(<8 x i8> %a0, <8 x i16> %a1) {
-; CHECK-LABEL: freeze_srhadd:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: sshr v1.8h, v1.8h, #8
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_srhadd:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #8
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_srhadd:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshr v1.8h, v1.8h, #8
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8
+; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #8
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = ashr <8 x i16> %a1, splat (i16 8)
%avg = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
>From 09b24f5afc26f983b1f8d15e7fb96ac9bfdba7b8 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Fri, 17 Oct 2025 15:48:31 +0000
Subject: [PATCH 05/18] [AArch64][GlobalISel] Modified llc test to check
generation from both SDAG and GISel Note that GlobalISel-generated code
involving the hadd family of intrinsics seems to be inefficent when compared
to SDAG.
---
.../AArch64/aarch64-known-bits-hadd.ll | 171 +++++++++++++-----
1 file changed, 123 insertions(+), 48 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
index f900f0209a108..a6fbaf01c5476 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
@@ -7,11 +8,20 @@ declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: haddu_zext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_zext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_zext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -20,11 +30,20 @@ define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: rhaddu_zext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhaddu_zext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhaddu_zext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -33,11 +52,20 @@ define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: hadds_zext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_zext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_zext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -46,12 +74,21 @@ define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: shaddu_zext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shaddu_zext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shaddu_zext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -62,13 +99,22 @@ define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
; ; negative tests
define <8 x i16> @haddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: haddu_sext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: bic v0.8h, #254, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: haddu_sext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: haddu_sext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = sext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -77,13 +123,22 @@ define <8 x i16> @haddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @urhadd_sext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: urhadd_sext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: sshll v1.8h, v1.8b, #0
-; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: bic v0.8h, #254, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_sext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_sext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = sext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -92,12 +147,21 @@ define <8 x i16> @urhadd_sext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @hadds_sext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: hadds_sext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: bic v0.8h, #254, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadds_sext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadds_sext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = sext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
@@ -106,15 +170,26 @@ define <8 x i16> @hadds_sext(<8 x i8> %a0, <8 x i8> %a1) {
}
define <8 x i16> @shaddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
-; CHECK-LABEL: shaddu_sext:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: sshll v0.8h, v0.8b, #0
-; CHECK-NEXT: bic v0.8h, #254, lsl #8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shaddu_sext:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: bic v0.8h, #254, lsl #8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shaddu_sext:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: mvni v2.8h, #254, lsl #8
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%x0 = sext <8 x i8> %a0 to <8 x i16>
%x1 = sext <8 x i8> %a1 to <8 x i16>
%hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
ret <8 x i16> %res
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From f48cbfec7e7dd36f8248993e96849e7380dd4606 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 21 Oct 2025 14:36:01 +0000
Subject: [PATCH 06/18] [AArch64][GlobalISel] Modified gMIR instruction names
to match SDAG equivalents.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 16 ++++++++--------
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 8 ++++----
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index e44e31845380a..d055e28f41e35 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -239,25 +239,25 @@ def G_USDOT : AArch64GenericInstruction {
let hasSideEffects = 0;
}
-def G_UHADD : AArch64GenericInstruction {
+def G_AVGFLOORU : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
-def G_URHADD : AArch64GenericInstruction {
+def G_AVGCEILU : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
-def G_SHADD : AArch64GenericInstruction {
+def G_AVGFLOORS : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
}
-def G_SRHADD : AArch64GenericInstruction {
+def G_AVGCEILS : AArch64GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
let hasSideEffects = 0;
@@ -310,10 +310,10 @@ def : GINodeEquiv<G_UDOT, AArch64udot>;
def : GINodeEquiv<G_SDOT, AArch64sdot>;
def : GINodeEquiv<G_USDOT, AArch64usdot>;
-def : GINodeEquiv<G_UHADD, avgflooru>;
-def : GINodeEquiv<G_URHADD, avgceilu>;
-def : GINodeEquiv<G_SHADD, avgfloors>;
-def : GINodeEquiv<G_SRHADD, avgceils>;
+def : GINodeEquiv<G_AVGFLOORU, avgflooru>;
+def : GINodeEquiv<G_AVGCEILU, avgceilu>;
+def : GINodeEquiv<G_AVGFLOORS, avgfloors>;
+def : GINodeEquiv<G_AVGCEILS, avgceils>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index c8d31bbbc8b9a..204f4b2b4c2de 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1818,13 +1818,13 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_uabd:
return LowerBinOp(TargetOpcode::G_ABDU);
case Intrinsic::aarch64_neon_uhadd:
- return LowerBinOp(AArch64::G_UHADD);
+ return LowerBinOp(AArch64::G_AVGFLOORU);
case Intrinsic::aarch64_neon_urhadd:
- return LowerBinOp(AArch64::G_URHADD);
+ return LowerBinOp(AArch64::G_AVGCEILU);
case Intrinsic::aarch64_neon_shadd:
- return LowerBinOp(AArch64::G_SHADD);
+ return LowerBinOp(AArch64::G_AVGFLOORS);
case Intrinsic::aarch64_neon_srhadd:
- return LowerBinOp(AArch64::G_SRHADD);
+ return LowerBinOp(AArch64::G_AVGCEILS);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
>From cc40eb7f9968628348959186a5ff7780c4207c83 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Mon, 27 Oct 2025 13:55:11 +0000
Subject: [PATCH 07/18] [AArch64][GlobalISel] Converted intrinsics to
machine-independent form
---
llvm/include/llvm/Support/TargetOpcodes.def | 11 ++++++++
llvm/include/llvm/Target/GenericOpcodes.td | 28 +++++++++++++++++++
.../Target/GlobalISel/SelectionDAGCompat.td | 4 +++
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 24 ----------------
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 10 +++----
.../GlobalISel/legalizer-info-validation.mir | 20 +++++++++++++
.../match-table-cxx.td | 2 +-
.../GlobalISelEmitter/GlobalISelEmitter.td | 2 +-
llvm/test/TableGen/get-named-operand-idx.td | 3 +-
9 files changed, 72 insertions(+), 32 deletions(-)
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index e55314568d683..d7a2e899ffd6f 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -295,6 +295,17 @@ HANDLE_TARGET_OPCODE(G_ABDS)
/// Generic absolute difference unsigned instruction.
HANDLE_TARGET_OPCODE(G_ABDU)
+/// Generic vector average with truncate unsigned instruction.
+HANDLE_TARGET_OPCODE(G_AVGFLOORU)
+
+/// Generic vector average with round unsigned instruction.
+HANDLE_TARGET_OPCODE(G_AVGCEILU)
+
+/// Generic vector average with truncate signed instruction.
+HANDLE_TARGET_OPCODE(G_AVGFLOORS)
+
+/// Generic vector average with round signed instruction.
+HANDLE_TARGET_OPCODE(G_AVGCEILS)
HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e3f995d53484f..b847e0425cf2b 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -423,6 +423,34 @@ def G_ABDU : GenericInstruction {
let isCommutable = true;
}
+// Generic vector average truncated unsigned.
+def G_AVGFLOORU : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+// Generic vector average rounded unsigned.
+def G_AVGCEILU : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+// Generic vector average truncated signed.
+def G_AVGFLOORS : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
+// Generic vector average rounded signed.
+def G_AVGCEILS : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
+
/// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
/// fshl(X,Y,Z): (X << (Z % bitwidth)) | (Y >> (bitwidth - (Z % bitwidth)))
def G_FSHL : GenericInstruction {
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index c0d480294dd8b..137b291d25d35 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -83,6 +83,10 @@ def : GINodeEquiv<G_LSHR, srl>;
def : GINodeEquiv<G_ASHR, sra>;
def : GINodeEquiv<G_ABDS, abds>;
def : GINodeEquiv<G_ABDU, abdu>;
+def : GINodeEquiv<G_AVGFLOORU, avgflooru>;
+def : GINodeEquiv<G_AVGCEILU, avgceilu>;
+def : GINodeEquiv<G_AVGFLOORS, avgfloors>;
+def : GINodeEquiv<G_AVGCEILS, avgceils>;
def : GINodeEquiv<G_SADDSAT, saddsat>;
def : GINodeEquiv<G_UADDSAT, uaddsat>;
def : GINodeEquiv<G_SSUBSAT, ssubsat>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index d055e28f41e35..7791eda6cd14a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -239,30 +239,6 @@ def G_USDOT : AArch64GenericInstruction {
let hasSideEffects = 0;
}
-def G_AVGFLOORU : AArch64GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
-}
-
-def G_AVGCEILU : AArch64GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
-}
-
-def G_AVGFLOORS : AArch64GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
-}
-
-def G_AVGCEILS : AArch64GenericInstruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
-}
-
// Generic instruction for the BSP pseudo. It is expanded into BSP, which
// expands into BSL/BIT/BIF after register allocation.
def G_BSP : AArch64GenericInstruction {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 204f4b2b4c2de..2e64b7ba0bd5a 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -289,7 +289,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0)
.lower();
- getActionDefinitionsBuilder({G_ABDS, G_ABDU})
+ getActionDefinitionsBuilder({G_ABDS, G_ABDU, G_AVGFLOORU, G_AVGCEILU, G_AVGFLOORS, G_AVGCEILS})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lower();
@@ -1818,13 +1818,13 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_uabd:
return LowerBinOp(TargetOpcode::G_ABDU);
case Intrinsic::aarch64_neon_uhadd:
- return LowerBinOp(AArch64::G_AVGFLOORU);
+ return LowerBinOp(TargetOpcode::G_AVGFLOORU);
case Intrinsic::aarch64_neon_urhadd:
- return LowerBinOp(AArch64::G_AVGCEILU);
+ return LowerBinOp(TargetOpcode::G_AVGCEILU);
case Intrinsic::aarch64_neon_shadd:
- return LowerBinOp(AArch64::G_AVGFLOORS);
+ return LowerBinOp(TargetOpcode::G_AVGFLOORS);
case Intrinsic::aarch64_neon_srhadd:
- return LowerBinOp(AArch64::G_AVGCEILS);
+ return LowerBinOp(TargetOpcode::G_AVGCEILS);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 896603d6eb20d..800b575dc7920 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -79,6 +79,26 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
+# DEBUG-NEXT: G_AVGFLOORU (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_AVGCEILU (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_AVGFLOORS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_AVGCEILS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: {{[0-9]+}}, OK
# DEBUG-NEXT: .. the first uncovered imm index: {{[0-9]+}}, OK
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
index 18960b43ab97d..df645c28ace9b 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-cxx.td
@@ -96,7 +96,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(99), GIMT_Encode2(211), /*)*//*default:*//*Label 5*/ GIMT_Encode4(524),
+// CHECK-NEXT: /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(103), GIMT_Encode2(215), /*)*//*default:*//*Label 5*/ GIMT_Encode4(524),
// CHECK-NEXT: /* 10 */ /*TargetOpcode::G_STORE*//*Label 0*/ GIMT_Encode4(458), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
// CHECK-NEXT: /* 182 */ /*TargetOpcode::G_SEXT*//*Label 1*/ GIMT_Encode4(476), GIMT_Encode4(0),
// CHECK-NEXT: /* 190 */ /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4(488), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index fdabc53a3ff3b..64ca63da3b6f0 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -535,7 +535,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O-NEXT: GIM_Reject,
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R00O-NEXT: GIM_Reject,
-// R00O-NEXT: }; // Size: 1902 bytes
+// R00O-NEXT: }; // Size: 1918 bytes
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
[(set GPR32:$dst,
diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td
index e6f6331cd9c48..59693eba50bdc 100644
--- a/llvm/test/TableGen/get-named-operand-idx.td
+++ b/llvm/test/TableGen/get-named-operand-idx.td
@@ -89,7 +89,8 @@ def InstD : InstBase {
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2, 0,
+// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+// CHECK-NEXT: 1, 2, 2, 0,
// CHECK-NEXT: };
// CHECK-NEXT: return InstructionIndex[Opcode];
// CHECK-NEXT: }
>From bc312fc63d46163f9e5c1acc6c97d3c511cbe86c Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 28 Oct 2025 09:17:55 +0000
Subject: [PATCH 08/18] [AArch64][GlobalISel] Fixed formatting
---
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 2e64b7ba0bd5a..942455e1942b8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -289,7 +289,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0)
.lower();
- getActionDefinitionsBuilder({G_ABDS, G_ABDU, G_AVGFLOORU, G_AVGCEILU, G_AVGFLOORS, G_AVGCEILS})
+ getActionDefinitionsBuilder(
+ {G_ABDS, G_ABDU, G_AVGFLOORU, G_AVGCEILU, G_AVGFLOORS, G_AVGCEILS})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lower();
>From dc04caaac14bb8be0f937b5cafe2e57b97b08bac Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Tue, 4 Nov 2025 09:19:02 +0000
Subject: [PATCH 09/18] [AArch64][GlobalISel] Renamed GISel nodes for
consistency
---
llvm/include/llvm/Support/TargetOpcodes.def | 8 ++++----
llvm/include/llvm/Target/GenericOpcodes.td | 8 ++++----
.../llvm/Target/GlobalISel/SelectionDAGCompat.td | 8 ++++----
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 8 ++++----
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 10 +++++-----
.../AArch64/GlobalISel/legalizer-info-validation.mir | 8 ++++----
6 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index d7a2e899ffd6f..0d43dce5d6357 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -296,16 +296,16 @@ HANDLE_TARGET_OPCODE(G_ABDS)
HANDLE_TARGET_OPCODE(G_ABDU)
/// Generic vector average with truncate unsigned instruction.
-HANDLE_TARGET_OPCODE(G_AVGFLOORU)
+HANDLE_TARGET_OPCODE(G_UAVGFLOOR)
/// Generic vector average with round unsigned instruction.
-HANDLE_TARGET_OPCODE(G_AVGCEILU)
+HANDLE_TARGET_OPCODE(G_UAVGCEIL)
/// Generic vector average with truncate signed instruction.
-HANDLE_TARGET_OPCODE(G_AVGFLOORS)
+HANDLE_TARGET_OPCODE(G_SAVGFLOOR)
/// Generic vector average with round signed instruction.
-HANDLE_TARGET_OPCODE(G_AVGCEILS)
+HANDLE_TARGET_OPCODE(G_SAVGCEIL)
HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index b847e0425cf2b..1b65b8b73527d 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -424,28 +424,28 @@ def G_ABDU : GenericInstruction {
}
// Generic vector average truncated unsigned.
-def G_AVGFLOORU : GenericInstruction {
+def G_UAVGFLOOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = 0;
}
// Generic vector average rounded unsigned.
-def G_AVGCEILU : GenericInstruction {
+def G_UAVGCEIL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = 0;
}
// Generic vector average truncated signed.
-def G_AVGFLOORS : GenericInstruction {
+def G_SAVGFLOOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = 0;
}
// Generic vector average rounded signed.
-def G_AVGCEILS : GenericInstruction {
+def G_SAVGCEIL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = 0;
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 137b291d25d35..a69e089779315 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -83,10 +83,10 @@ def : GINodeEquiv<G_LSHR, srl>;
def : GINodeEquiv<G_ASHR, sra>;
def : GINodeEquiv<G_ABDS, abds>;
def : GINodeEquiv<G_ABDU, abdu>;
-def : GINodeEquiv<G_AVGFLOORU, avgflooru>;
-def : GINodeEquiv<G_AVGCEILU, avgceilu>;
-def : GINodeEquiv<G_AVGFLOORS, avgfloors>;
-def : GINodeEquiv<G_AVGCEILS, avgceils>;
+def : GINodeEquiv<G_UAVGFLOOR, avgflooru>;
+def : GINodeEquiv<G_UAVGCEIL, avgceilu>;
+def : GINodeEquiv<G_SAVGFLOOR, avgfloors>;
+def : GINodeEquiv<G_SAVGCEIL, avgceils>;
def : GINodeEquiv<G_SADDSAT, saddsat>;
def : GINodeEquiv<G_UADDSAT, uaddsat>;
def : GINodeEquiv<G_SSUBSAT, ssubsat>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 7791eda6cd14a..dffff27ce94aa 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -286,10 +286,10 @@ def : GINodeEquiv<G_UDOT, AArch64udot>;
def : GINodeEquiv<G_SDOT, AArch64sdot>;
def : GINodeEquiv<G_USDOT, AArch64usdot>;
-def : GINodeEquiv<G_AVGFLOORU, avgflooru>;
-def : GINodeEquiv<G_AVGCEILU, avgceilu>;
-def : GINodeEquiv<G_AVGFLOORS, avgfloors>;
-def : GINodeEquiv<G_AVGCEILS, avgceils>;
+def : GINodeEquiv<G_UAVGFLOOR, avgflooru>;
+def : GINodeEquiv<G_UAVGCEIL, avgceilu>;
+def : GINodeEquiv<G_SAVGFLOOR, avgfloors>;
+def : GINodeEquiv<G_SAVGCEIL, avgceils>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 942455e1942b8..6af3fd9c65984 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -290,7 +290,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.lower();
getActionDefinitionsBuilder(
- {G_ABDS, G_ABDU, G_AVGFLOORU, G_AVGCEILU, G_AVGFLOORS, G_AVGCEILS})
+ {G_ABDS, G_ABDU, G_UAVGFLOOR, G_UAVGCEIL, G_SAVGFLOOR, G_SAVGCEIL})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lower();
@@ -1819,13 +1819,13 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_uabd:
return LowerBinOp(TargetOpcode::G_ABDU);
case Intrinsic::aarch64_neon_uhadd:
- return LowerBinOp(TargetOpcode::G_AVGFLOORU);
+ return LowerBinOp(TargetOpcode::G_UAVGFLOOR);
case Intrinsic::aarch64_neon_urhadd:
- return LowerBinOp(TargetOpcode::G_AVGCEILU);
+ return LowerBinOp(TargetOpcode::G_UAVGCEIL);
case Intrinsic::aarch64_neon_shadd:
- return LowerBinOp(TargetOpcode::G_AVGFLOORS);
+ return LowerBinOp(TargetOpcode::G_SAVGFLOOR);
case Intrinsic::aarch64_neon_srhadd:
- return LowerBinOp(TargetOpcode::G_AVGCEILS);
+ return LowerBinOp(TargetOpcode::G_SAVGCEIL);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 800b575dc7920..7edebd576d268 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -79,22 +79,22 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_AVGFLOORU (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_UAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_AVGCEILU (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_UAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_AVGFLOORS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_SAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
-# DEBUG-NEXT: G_AVGCEILS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: G_SAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
>From 61d7a971cdfb605c43c5d76269cf6cf84f798bd2 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Wed, 5 Nov 2025 09:57:54 +0000
Subject: [PATCH 10/18] [GlobalISel] Added documentation for gMIR instructions
into GenericOpcode.rst
---
llvm/docs/GlobalISel/GenericOpcode.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 661a11537cf57..72cb8c6efca10 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -511,6 +511,19 @@ Compute the absolute difference (signed and unsigned), e.g. trunc(abs(ext(x)-ext
%0:_(s33) = G_ABDS %2, %3
%1:_(s33) = G_ABDU %4, %5
+G_UAVGFLOOR, G_UAVGCEIL, G_SAVGFLOOR, G_SAVGCEIL
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Computes the average of corresponding elements in two vectors (signed and unsigned).
+Resulting vector contains values that are either rounded or truncated. e.g. trunc(shr(ext(a)+ext(b))).
+
+.. code-block:: none
+
+ %0:_(<4 x i16>) = G_UAVGFLOOR %4:_(<4 x i16>), %5:_(<4 x i16>)
+ %1:_(<4 x i16>) = G_UAVGCEIL %6:_(<4 x i16>), %7:_(<4 x i16>)
+ %2:_(<4 x i16>) = G_SAVGFLOOR %8:_(<4 x i16>), %9:_(<4 x i16>)
+ %3:_(<4 x i16>) = G_SAVGCEIL %10:_(<4 x i16>), %11:_(<4 x i16>)
+
Floating Point Operations
-------------------------
>From f11c039a8aa23277f5efe35033b9bd392a9af56e Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Wed, 5 Nov 2025 10:56:50 +0000
Subject: [PATCH 11/18] [AArch64][GlobalISel] Modified trunc-avg-fold.ll to
separately test SDAG and GISel generated code
Test file contains only CHECK-SD and CHECK-GI prefixes, as shared CHECK prefix is not needed.
---
llvm/test/CodeGen/AArch64/trunc-avg-fold.ll | 69 +++++++++++++++------
1 file changed, 50 insertions(+), 19 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll b/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
index 54fcae4ba28b7..0a72bbccf0ed2 100644
--- a/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
+++ b/llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
@@ -1,11 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK-SD
+; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon -global-isel < %s | FileCheck %s --check-prefixes=CHECK-GI
define <8 x i8> @avgceil_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: avgceil_u_i8_to_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: avgceil_u_i8_to_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: avgceil_u_i8_to_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
%a16 = zext <8 x i8> %a to <8 x i16>
%b16 = zext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
@@ -15,10 +24,18 @@ define <8 x i8> @avgceil_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
define <8 x i8> @test_avgceil_s(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_avgceil_s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_avgceil_s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_avgceil_s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
%a16 = sext <8 x i8> %a to <8 x i16>
%b16 = sext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
@@ -27,10 +44,18 @@ define <8 x i8> @test_avgceil_s(<8 x i8> %a, <8 x i8> %b) {
}
define <8 x i8> @avgfloor_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: avgfloor_u_i8_to_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: avgfloor_u_i8_to_i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: avgfloor_u_i8_to_i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
%a16 = zext <8 x i8> %a to <8 x i16>
%b16 = zext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
@@ -39,15 +64,21 @@ define <8 x i8> @avgfloor_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
}
define <8 x i8> @test_avgfloor_s(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-LABEL: test_avgfloor_s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: test_avgfloor_s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_avgfloor_s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
%a16 = sext <8 x i8> %a to <8 x i16>
%b16 = sext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
%res = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %res
}
-
-
>From 2f2dd5fd41df79c89846de3d4e3bce19f844d4d1 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Wed, 5 Nov 2025 16:28:01 +0000
Subject: [PATCH 12/18] [AArch64][GlobalISel] Modified arm64-vhadd.ll to
separately test SDAG and GISel generated code
---
llvm/test/CodeGen/AArch64/arm64-vhadd.ll | 1599 ++++++++++++++++------
1 file changed, 1162 insertions(+), 437 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
index a505b42e3423a..09ea9eeb03914 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -1,5 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for ext_via_i19
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srhadd_v2i32_trunc
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urhadd_v2i32_trunc
define <8 x i8> @shadd8b(ptr nocapture readonly %A, ptr nocapture readonly %B) {
; CHECK-LABEL: shadd8b:
@@ -327,11 +332,20 @@ define <4 x i32> @urhadd4s(ptr nocapture readonly %A, ptr nocapture readonly %B)
}
define void @testLowerToSRHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD8b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #1
+; CHECK-GI-NEXT: saddl.8h v0, v0, v1
+; CHECK-GI-NEXT: add.8h v0, v0, v2
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i8> %src1 to <8 x i16>
%sextsrc2 = sext <8 x i8> %src2 to <8 x i16>
%add1 = add nsw <8 x i16> %sextsrc1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -343,11 +357,20 @@ define void @testLowerToSRHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture w
}
define void @testLowerToSRHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD4h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v2, #1
+; CHECK-GI-NEXT: saddl.4s v0, v0, v1
+; CHECK-GI-NEXT: add.4s v0, v0, v2
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i16> %src1 to <4 x i32>
%sextsrc2 = sext <4 x i16> %src2 to <4 x i32>
%add1 = add nsw <4 x i32> %sextsrc1, <i32 1, i32 1, i32 1, i32 1>
@@ -359,11 +382,21 @@ define void @testLowerToSRHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture
}
define void @testLowerToSRHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD2s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI26_0
+; CHECK-GI-NEXT: saddl.2d v0, v0, v1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]
+; CHECK-GI-NEXT: add.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <2 x i32> %src1 to <2 x i64>
%sextsrc2 = sext <2 x i32> %src2 to <2 x i64>
%add1 = add nsw <2 x i64> %sextsrc1, <i64 1, i64 1>
@@ -375,11 +408,23 @@ define void @testLowerToSRHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture
}
define void @testLowerToSRHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD16b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #1
+; CHECK-GI-NEXT: saddl.8h v3, v0, v1
+; CHECK-GI-NEXT: saddl2.8h v0, v0, v1
+; CHECK-GI-NEXT: add.8h v1, v3, v2
+; CHECK-GI-NEXT: add.8h v0, v0, v2
+; CHECK-GI-NEXT: shrn.8b v1, v1, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <16 x i8> %src1 to <16 x i16>
%sextsrc2 = sext <16 x i8> %src2 to <16 x i16>
%add1 = add nsw <16 x i16> %sextsrc1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -391,11 +436,23 @@ define void @testLowerToSRHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocaptur
}
define void @testLowerToSRHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v2, #1
+; CHECK-GI-NEXT: saddl.4s v3, v0, v1
+; CHECK-GI-NEXT: saddl2.4s v0, v0, v1
+; CHECK-GI-NEXT: add.4s v1, v3, v2
+; CHECK-GI-NEXT: add.4s v0, v0, v2
+; CHECK-GI-NEXT: shrn.4h v1, v1, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%sextsrc2 = sext <8 x i16> %src2 to <8 x i32>
%add1 = add nsw <8 x i32> %sextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -407,11 +464,24 @@ define void @testLowerToSRHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture
}
define void @testLowerToSRHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSRHADD4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSRHADD4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSRHADD4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI29_0
+; CHECK-GI-NEXT: saddl.2d v2, v0, v1
+; CHECK-GI-NEXT: saddl2.2d v0, v0, v1
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI29_0]
+; CHECK-GI-NEXT: add.2d v1, v2, v3
+; CHECK-GI-NEXT: add.2d v0, v0, v3
+; CHECK-GI-NEXT: shrn.2s v1, v1, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%sextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add1 = add nsw <4 x i64> %sextsrc1, <i64 1, i64 1, i64 1, i64 1>
@@ -423,11 +493,18 @@ define void @testLowerToSRHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture
}
define void @testLowerToSHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD8b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i8> %src1 to <8 x i16>
%sextsrc2 = sext <8 x i8> %src2 to <8 x i16>
%add = add nsw <8 x i16> %sextsrc1, %sextsrc2
@@ -438,11 +515,18 @@ define void @testLowerToSHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture wr
}
define void @testLowerToSHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD4h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.4s v0, v0, v1
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i16> %src1 to <4 x i32>
%sextsrc2 = sext <4 x i16> %src2 to <4 x i32>
%add = add nsw <4 x i32> %sextsrc1, %sextsrc2
@@ -453,11 +537,18 @@ define void @testLowerToSHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture
}
define void @testLowerToSHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD2s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <2 x i32> %src1 to <2 x i64>
%sextsrc2 = sext <2 x i32> %src2 to <2 x i64>
%add = add nsw <2 x i64> %sextsrc1, %sextsrc2
@@ -468,11 +559,20 @@ define void @testLowerToSHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture
}
define void @testLowerToSHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD16b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.8h v2, v0, v1
+; CHECK-GI-NEXT: saddl2.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v1, v2, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <16 x i8> %src1 to <16 x i16>
%sextsrc2 = sext <16 x i8> %src2 to <16 x i16>
%add = add nsw <16 x i16> %sextsrc1, %sextsrc2
@@ -483,11 +583,20 @@ define void @testLowerToSHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture
}
define void @testLowerToSHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.4s v2, v0, v1
+; CHECK-GI-NEXT: saddl2.4s v0, v0, v1
+; CHECK-GI-NEXT: shrn.4h v1, v2, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%sextsrc2 = sext <8 x i16> %src2 to <8 x i32>
%add = add nsw <8 x i32> %sextsrc1, %sextsrc2
@@ -498,11 +607,20 @@ define void @testLowerToSHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture
}
define void @testLowerToSHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.2d v2, v0, v1
+; CHECK-GI-NEXT: saddl2.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v1, v2, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%sextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add = add nsw <4 x i64> %sextsrc1, %sextsrc2
@@ -513,11 +631,20 @@ define void @testLowerToSHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture
}
define void @testLowerToURHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD8b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #1
+; CHECK-GI-NEXT: uaddl.8h v0, v0, v1
+; CHECK-GI-NEXT: add.8h v0, v0, v2
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i8> %src1 to <8 x i16>
%zextsrc2 = zext <8 x i8> %src2 to <8 x i16>
%add1 = add nuw nsw <8 x i16> %zextsrc1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -529,11 +656,20 @@ define void @testLowerToURHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture w
}
define void @testLowerToURHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD4h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v2, #1
+; CHECK-GI-NEXT: uaddl.4s v0, v0, v1
+; CHECK-GI-NEXT: add.4s v0, v0, v2
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
%add1 = add nuw nsw <4 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1>
@@ -545,11 +681,21 @@ define void @testLowerToURHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture
}
define void @testLowerToURHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD2s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI38_0
+; CHECK-GI-NEXT: uaddl.2d v0, v0, v1
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI38_0]
+; CHECK-GI-NEXT: add.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i32> %src1 to <2 x i64>
%zextsrc2 = zext <2 x i32> %src2 to <2 x i64>
%add1 = add nuw nsw <2 x i64> %zextsrc1, <i64 1, i64 1>
@@ -561,11 +707,23 @@ define void @testLowerToURHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture
}
define void @testLowerToURHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD16b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #1
+; CHECK-GI-NEXT: uaddl.8h v3, v0, v1
+; CHECK-GI-NEXT: uaddl2.8h v0, v0, v1
+; CHECK-GI-NEXT: add.8h v1, v3, v2
+; CHECK-GI-NEXT: add.8h v0, v0, v2
+; CHECK-GI-NEXT: shrn.8b v1, v1, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <16 x i8> %src1 to <16 x i16>
%zextsrc2 = zext <16 x i8> %src2 to <16 x i16>
%add1 = add nuw nsw <16 x i16> %zextsrc1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -577,11 +735,23 @@ define void @testLowerToURHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocaptur
}
define void @testLowerToURHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v2, #1
+; CHECK-GI-NEXT: uaddl.4s v3, v0, v1
+; CHECK-GI-NEXT: uaddl2.4s v0, v0, v1
+; CHECK-GI-NEXT: add.4s v1, v3, v2
+; CHECK-GI-NEXT: add.4s v0, v0, v2
+; CHECK-GI-NEXT: shrn.4h v1, v1, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> %src2 to <8 x i32>
%add1 = add nuw nsw <8 x i32> %zextsrc1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -593,11 +763,24 @@ define void @testLowerToURHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture
}
define void @testLowerToURHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToURHADD4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToURHADD4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToURHADD4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI41_0
+; CHECK-GI-NEXT: uaddl.2d v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.2d v0, v0, v1
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI41_0]
+; CHECK-GI-NEXT: add.2d v1, v2, v3
+; CHECK-GI-NEXT: add.2d v0, v0, v3
+; CHECK-GI-NEXT: shrn.2s v1, v1, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
%add1 = add nuw nsw <4 x i64> %zextsrc1, <i64 1, i64 1, i64 1, i64 1>
@@ -609,11 +792,18 @@ define void @testLowerToURHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture
}
define void @testLowerToUHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD8b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i8> %src1 to <8 x i16>
%zextsrc2 = zext <8 x i8> %src2 to <8 x i16>
%add = add nuw nsw <8 x i16> %zextsrc1, %zextsrc2
@@ -624,11 +814,18 @@ define void @testLowerToUHADD8b(<8 x i8> %src1, <8 x i8> %src2, ptr nocapture wr
}
define void @testLowerToUHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD4h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.4s v0, v0, v1
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
%add = add nuw nsw <4 x i32> %zextsrc1, %zextsrc2
@@ -639,11 +836,18 @@ define void @testLowerToUHADD4h(<4 x i16> %src1, <4 x i16> %src2, ptr nocapture
}
define void @testLowerToUHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD2s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i32> %src1 to <2 x i64>
%zextsrc2 = zext <2 x i32> %src2 to <2 x i64>
%add = add nuw nsw <2 x i64> %zextsrc1, %zextsrc2
@@ -654,11 +858,20 @@ define void @testLowerToUHADD2s(<2 x i32> %src1, <2 x i32> %src2, ptr nocapture
}
define void @testLowerToUHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD16b:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.8h v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v1, v2, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <16 x i8> %src1 to <16 x i16>
%zextsrc2 = zext <16 x i8> %src2 to <16 x i16>
%add = add nuw nsw <16 x i16> %zextsrc1, %zextsrc2
@@ -669,11 +882,20 @@ define void @testLowerToUHADD16b(<16 x i8> %src1, <16 x i8> %src2, ptr nocapture
}
define void @testLowerToUHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD8h:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.4s v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.4s v0, v0, v1
+; CHECK-GI-NEXT: shrn.4h v1, v2, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> %src2 to <8 x i32>
%add = add nuw nsw <8 x i32> %zextsrc1, %zextsrc2
@@ -684,11 +906,20 @@ define void @testLowerToUHADD8h(<8 x i16> %src1, <8 x i16> %src2, ptr nocapture
}
define void @testLowerToUHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD4s:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.2d v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.2d v0, v0, v1
+; CHECK-GI-NEXT: shrn.2s v1, v2, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
%add = add nuw nsw <4 x i64> %zextsrc1, %zextsrc2
@@ -699,11 +930,17 @@ define void @testLowerToUHADD4s(<4 x i32> %src1, <4 x i32> %src2, ptr nocapture
}
define <4 x i32> @hadd16_sext_asr(<4 x i16> %src1, <4 x i16> %src2) {
-; CHECK-LABEL: hadd16_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.4h v0, v0, v1
-; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd16_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.4h v0, v0, v1
+; CHECK-SD-NEXT: sshll.4s v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd16_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.4s v0, v0, v1
+; CHECK-GI-NEXT: sshr.4s v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i16> %src1 to <4 x i32>
%zextsrc2 = sext <4 x i16> %src2 to <4 x i32>
%add = add nsw <4 x i32> %zextsrc1, %zextsrc2
@@ -712,11 +949,17 @@ define <4 x i32> @hadd16_sext_asr(<4 x i16> %src1, <4 x i16> %src2) {
}
define <4 x i32> @hadd16_zext_asr(<4 x i16> %src1, <4 x i16> %src2) {
-; CHECK-LABEL: hadd16_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd16_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ushll.4s v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd16_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.4s v0, v0, v1
+; CHECK-GI-NEXT: ushr.4s v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
%add = add nuw nsw <4 x i32> %zextsrc1, %zextsrc2
@@ -738,11 +981,17 @@ define <4 x i32> @hadd16_sext_lsr(<4 x i16> %src1, <4 x i16> %src2) {
}
define <4 x i32> @hadd16_zext_lsr(<4 x i16> %src1, <4 x i16> %src2) {
-; CHECK-LABEL: hadd16_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd16_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ushll.4s v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd16_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.4s v0, v0, v1
+; CHECK-GI-NEXT: ushr.4s v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
%zextsrc2 = zext <4 x i16> %src2 to <4 x i32>
%add = add nuw nsw <4 x i32> %zextsrc1, %zextsrc2
@@ -751,12 +1000,20 @@ define <4 x i32> @hadd16_zext_lsr(<4 x i16> %src1, <4 x i16> %src2) {
}
define <4 x i64> @hadd32_sext_asr(<4 x i32> %src1, <4 x i32> %src2) {
-; CHECK-LABEL: hadd32_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shadd.4s v0, v0, v1
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd32_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shadd.4s v0, v0, v1
+; CHECK-SD-NEXT: sshll2.2d v1, v0, #0
+; CHECK-SD-NEXT: sshll.2d v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd32_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.2d v2, v0, v1
+; CHECK-GI-NEXT: saddl2.2d v1, v0, v1
+; CHECK-GI-NEXT: sshr.2d v0, v2, #1
+; CHECK-GI-NEXT: sshr.2d v1, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add = add nsw <4 x i64> %zextsrc1, %zextsrc2
@@ -765,12 +1022,20 @@ define <4 x i64> @hadd32_sext_asr(<4 x i32> %src1, <4 x i32> %src2) {
}
define <4 x i64> @hadd32_zext_asr(<4 x i32> %src1, <4 x i32> %src2) {
-; CHECK-LABEL: hadd32_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4s v0, v0, v1
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd32_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: ushll2.2d v1, v0, #0
+; CHECK-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd32_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.2d v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.2d v1, v0, v1
+; CHECK-GI-NEXT: ushr.2d v0, v2, #1
+; CHECK-GI-NEXT: ushr.2d v1, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
%add = add nuw nsw <4 x i64> %zextsrc1, %zextsrc2
@@ -779,13 +1044,21 @@ define <4 x i64> @hadd32_zext_asr(<4 x i32> %src1, <4 x i32> %src2) {
}
define <4 x i64> @hadd32_sext_lsr(<4 x i32> %src1, <4 x i32> %src2) {
-; CHECK-LABEL: hadd32_sext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: saddl.2d v2, v0, v1
-; CHECK-NEXT: saddl2.2d v0, v0, v1
-; CHECK-NEXT: ushr.2d v1, v0, #1
-; CHECK-NEXT: ushr.2d v0, v2, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd32_sext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: saddl.2d v2, v0, v1
+; CHECK-SD-NEXT: saddl2.2d v0, v0, v1
+; CHECK-SD-NEXT: ushr.2d v1, v0, #1
+; CHECK-SD-NEXT: ushr.2d v0, v2, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd32_sext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: saddl.2d v2, v0, v1
+; CHECK-GI-NEXT: saddl2.2d v1, v0, v1
+; CHECK-GI-NEXT: ushr.2d v0, v2, #1
+; CHECK-GI-NEXT: ushr.2d v1, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add = add nsw <4 x i64> %zextsrc1, %zextsrc2
@@ -794,12 +1067,20 @@ define <4 x i64> @hadd32_sext_lsr(<4 x i32> %src1, <4 x i32> %src2) {
}
define <4 x i64> @hadd32_zext_lsr(<4 x i32> %src1, <4 x i32> %src2) {
-; CHECK-LABEL: hadd32_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uhadd.4s v0, v0, v1
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd32_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: ushll2.2d v1, v0, #0
+; CHECK-SD-NEXT: ushll.2d v0, v0, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd32_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: uaddl.2d v2, v0, v1
+; CHECK-GI-NEXT: uaddl2.2d v1, v0, v1
+; CHECK-GI-NEXT: ushr.2d v0, v2, #1
+; CHECK-GI-NEXT: ushr.2d v1, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
%zextsrc2 = zext <4 x i32> %src2 to <4 x i64>
%add = add nuw nsw <4 x i64> %zextsrc1, %zextsrc2
@@ -808,14 +1089,23 @@ define <4 x i64> @hadd32_zext_lsr(<4 x i32> %src1, <4 x i32> %src2) {
}
define <4 x i16> @hadd8_sext_asr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: hadd8_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.4h v1, v1, #8
-; CHECK-NEXT: shl.4h v0, v0, #8
-; CHECK-NEXT: sshr.4h v1, v1, #8
-; CHECK-NEXT: sshr.4h v0, v0, #8
-; CHECK-NEXT: shadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.4h v1, v1, #8
+; CHECK-SD-NEXT: shl.4h v0, v0, #8
+; CHECK-SD-NEXT: sshr.4h v1, v1, #8
+; CHECK-SD-NEXT: sshr.4h v0, v0, #8
+; CHECK-SD-NEXT: shadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.4h v1, v1, #8
+; CHECK-GI-NEXT: shl.4h v0, v0, #8
+; CHECK-GI-NEXT: sshr.4h v1, v1, #8
+; CHECK-GI-NEXT: ssra.4h v1, v0, #8
+; CHECK-GI-NEXT: sshr.4h v0, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
%add = add nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -824,12 +1114,21 @@ define <4 x i16> @hadd8_sext_asr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @hadd8_zext_asr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: hadd8_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
-; CHECK-NEXT: bic.4h v0, #255, lsl #8
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-SD-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: add.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
%add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -838,14 +1137,23 @@ define <4 x i16> @hadd8_zext_asr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @hadd8_sext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: hadd8_sext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.4h v0, v0, #8
-; CHECK-NEXT: shl.4h v1, v1, #8
-; CHECK-NEXT: sshr.4h v0, v0, #8
-; CHECK-NEXT: ssra.4h v0, v1, #8
-; CHECK-NEXT: ushr.4h v0, v0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8_sext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.4h v0, v0, #8
+; CHECK-SD-NEXT: shl.4h v1, v1, #8
+; CHECK-SD-NEXT: sshr.4h v0, v0, #8
+; CHECK-SD-NEXT: ssra.4h v0, v1, #8
+; CHECK-SD-NEXT: ushr.4h v0, v0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8_sext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.4h v1, v1, #8
+; CHECK-GI-NEXT: shl.4h v0, v0, #8
+; CHECK-GI-NEXT: sshr.4h v1, v1, #8
+; CHECK-GI-NEXT: ssra.4h v1, v0, #8
+; CHECK-GI-NEXT: ushr.4h v0, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
%add = add nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -854,12 +1162,21 @@ define <4 x i16> @hadd8_sext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @hadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: hadd8_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
-; CHECK-NEXT: bic.4h v0, #255, lsl #8
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-SD-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: add.4h v0, v0, v1
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
%add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -868,14 +1185,30 @@ define <4 x i16> @hadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <2 x i16> @hadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: hadd8x2_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.2s v1, v1, #24
-; CHECK-NEXT: shl.2s v0, v0, #24
-; CHECK-NEXT: sshr.2s v1, v1, #24
-; CHECK-NEXT: sshr.2s v0, v0, #24
-; CHECK-NEXT: shadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8x2_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.2s v1, v1, #24
+; CHECK-SD-NEXT: shl.2s v0, v0, #24
+; CHECK-SD-NEXT: sshr.2s v1, v1, #24
+; CHECK-SD-NEXT: sshr.2s v0, v0, #24
+; CHECK-SD-NEXT: shadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8x2_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.2s v1, v1, #24
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: shl.2s v0, v0, #24
+; CHECK-GI-NEXT: fmov s2, w8
+; CHECK-GI-NEXT: sshr.2s v1, v1, #24
+; CHECK-GI-NEXT: mov.h v2[1], w8
+; CHECK-GI-NEXT: ssra.2s v1, v0, #24
+; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
+; CHECK-GI-NEXT: neg.4h v1, v2
+; CHECK-GI-NEXT: sshl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
%add = add nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -884,13 +1217,29 @@ define <2 x i16> @hadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @hadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: hadd8x2_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-NEXT: and.8b v1, v1, v2
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: uhadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8x2_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-SD-NEXT: and.8b v1, v1, v2
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: uhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8x2_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: fmov s2, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v1
+; CHECK-GI-NEXT: mov.h v2[1], w8
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: neg.4h v1, v2
+; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
%add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -899,16 +1248,32 @@ define <2 x i16> @hadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @hadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: hadd8x2_sext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.2s v0, v0, #24
-; CHECK-NEXT: shl.2s v1, v1, #24
-; CHECK-NEXT: movi d2, #0x00ffff0000ffff
-; CHECK-NEXT: sshr.2s v0, v0, #24
-; CHECK-NEXT: ssra.2s v0, v1, #24
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: ushr.2s v0, v0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8x2_sext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.2s v0, v0, #24
+; CHECK-SD-NEXT: shl.2s v1, v1, #24
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: sshr.2s v0, v0, #24
+; CHECK-SD-NEXT: ssra.2s v0, v1, #24
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: ushr.2s v0, v0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8x2_sext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.2s v1, v1, #24
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: shl.2s v0, v0, #24
+; CHECK-GI-NEXT: fmov s2, w8
+; CHECK-GI-NEXT: sshr.2s v1, v1, #24
+; CHECK-GI-NEXT: mov.h v2[1], w8
+; CHECK-GI-NEXT: ssra.2s v1, v0, #24
+; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
+; CHECK-GI-NEXT: neg.4h v1, v2
+; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
%add = add nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -917,13 +1282,29 @@ define <2 x i16> @hadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @hadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: hadd8x2_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-NEXT: and.8b v1, v1, v2
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: uhadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: hadd8x2_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-SD-NEXT: and.8b v1, v1, v2
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: uhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: hadd8x2_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: fmov s2, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v1
+; CHECK-GI-NEXT: mov.h v2[1], w8
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: neg.4h v1, v2
+; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
%add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -932,14 +1313,25 @@ define <2 x i16> @hadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <4 x i16> @rhadd8_sext_asr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: rhadd8_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.4h v1, v1, #8
-; CHECK-NEXT: shl.4h v0, v0, #8
-; CHECK-NEXT: sshr.4h v1, v1, #8
-; CHECK-NEXT: sshr.4h v0, v0, #8
-; CHECK-NEXT: srhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.4h v1, v1, #8
+; CHECK-SD-NEXT: shl.4h v0, v0, #8
+; CHECK-SD-NEXT: sshr.4h v1, v1, #8
+; CHECK-SD-NEXT: sshr.4h v0, v0, #8
+; CHECK-SD-NEXT: srhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.4h v1, v1, #8
+; CHECK-GI-NEXT: shl.4h v0, v0, #8
+; CHECK-GI-NEXT: movi.4h v2, #1
+; CHECK-GI-NEXT: sshr.4h v1, v1, #8
+; CHECK-GI-NEXT: ssra.4h v1, v0, #8
+; CHECK-GI-NEXT: add.4h v0, v1, v2
+; CHECK-GI-NEXT: sshr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
%add = add nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -949,12 +1341,23 @@ define <4 x i16> @rhadd8_sext_asr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @rhadd8_zext_asr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: rhadd8_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
-; CHECK-NEXT: bic.4h v0, #255, lsl #8
-; CHECK-NEXT: urhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-SD-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-SD-NEXT: urhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: movi.4h v2, #1
+; CHECK-GI-NEXT: add.4h v0, v0, v1
+; CHECK-GI-NEXT: add.4h v0, v0, v2
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
%add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -964,16 +1367,27 @@ define <4 x i16> @rhadd8_zext_asr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @rhadd8_sext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: rhadd8_sext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.4h v0, v0, #8
-; CHECK-NEXT: shl.4h v1, v1, #8
-; CHECK-NEXT: movi.4h v2, #1
-; CHECK-NEXT: sshr.4h v0, v0, #8
-; CHECK-NEXT: ssra.4h v0, v1, #8
-; CHECK-NEXT: add.4h v0, v0, v2
-; CHECK-NEXT: ushr.4h v0, v0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8_sext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.4h v0, v0, #8
+; CHECK-SD-NEXT: shl.4h v1, v1, #8
+; CHECK-SD-NEXT: movi.4h v2, #1
+; CHECK-SD-NEXT: sshr.4h v0, v0, #8
+; CHECK-SD-NEXT: ssra.4h v0, v1, #8
+; CHECK-SD-NEXT: add.4h v0, v0, v2
+; CHECK-SD-NEXT: ushr.4h v0, v0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8_sext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.4h v1, v1, #8
+; CHECK-GI-NEXT: shl.4h v0, v0, #8
+; CHECK-GI-NEXT: movi.4h v2, #1
+; CHECK-GI-NEXT: sshr.4h v1, v1, #8
+; CHECK-GI-NEXT: ssra.4h v1, v0, #8
+; CHECK-GI-NEXT: add.4h v0, v1, v2
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
%add = add nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -983,12 +1397,23 @@ define <4 x i16> @rhadd8_sext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <4 x i16> @rhadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
-; CHECK-LABEL: rhadd8_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
-; CHECK-NEXT: bic.4h v0, #255, lsl #8
-; CHECK-NEXT: urhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-SD-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-SD-NEXT: urhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: movi.4h v2, #1
+; CHECK-GI-NEXT: add.4h v0, v0, v1
+; CHECK-GI-NEXT: add.4h v0, v0, v2
+; CHECK-GI-NEXT: ushr.4h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
%zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
%add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
@@ -998,14 +1423,32 @@ define <4 x i16> @rhadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
}
define <2 x i16> @rhadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: rhadd8x2_sext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.2s v1, v1, #24
-; CHECK-NEXT: shl.2s v0, v0, #24
-; CHECK-NEXT: sshr.2s v1, v1, #24
-; CHECK-NEXT: sshr.2s v0, v0, #24
-; CHECK-NEXT: srhadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8x2_sext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.2s v1, v1, #24
+; CHECK-SD-NEXT: shl.2s v0, v0, #24
+; CHECK-SD-NEXT: sshr.2s v1, v1, #24
+; CHECK-SD-NEXT: sshr.2s v0, v0, #24
+; CHECK-SD-NEXT: srhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8x2_sext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.2s v1, v1, #24
+; CHECK-GI-NEXT: shl.2s v0, v0, #24
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: dup.2s v2, w8
+; CHECK-GI-NEXT: sshr.2s v1, v1, #24
+; CHECK-GI-NEXT: ssra.2s v1, v0, #24
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov.h v0[1], w8
+; CHECK-GI-NEXT: add.2s v1, v1, v2
+; CHECK-GI-NEXT: uzp1.4h v1, v1, v0
+; CHECK-GI-NEXT: neg.4h v0, v0
+; CHECK-GI-NEXT: sshl.4h v0, v1, v0
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
%add = add nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -1015,13 +1458,31 @@ define <2 x i16> @rhadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @rhadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: rhadd8x2_zext_asr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-NEXT: and.8b v1, v1, v2
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: urhadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8x2_zext_asr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-SD-NEXT: and.8b v1, v1, v2
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: urhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8x2_zext_asr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: dup.2s v2, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v1
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v2
+; CHECK-GI-NEXT: mov.h v1[1], w8
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: neg.4h v1, v1
+; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
%add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -1031,18 +1492,36 @@ define <2 x i16> @rhadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @rhadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: rhadd8x2_sext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shl.2s v0, v0, #24
-; CHECK-NEXT: shl.2s v1, v1, #24
-; CHECK-NEXT: movi d2, #0x00ffff0000ffff
-; CHECK-NEXT: sshr.2s v0, v0, #24
-; CHECK-NEXT: sshr.2s v1, v1, #24
-; CHECK-NEXT: mvn.8b v0, v0
-; CHECK-NEXT: sub.2s v0, v1, v0
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: ushr.2s v0, v0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8x2_sext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shl.2s v0, v0, #24
+; CHECK-SD-NEXT: shl.2s v1, v1, #24
+; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-SD-NEXT: sshr.2s v0, v0, #24
+; CHECK-SD-NEXT: sshr.2s v1, v1, #24
+; CHECK-SD-NEXT: mvn.8b v0, v0
+; CHECK-SD-NEXT: sub.2s v0, v1, v0
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: ushr.2s v0, v0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8x2_sext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: shl.2s v1, v1, #24
+; CHECK-GI-NEXT: shl.2s v0, v0, #24
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: dup.2s v2, w8
+; CHECK-GI-NEXT: sshr.2s v1, v1, #24
+; CHECK-GI-NEXT: ssra.2s v1, v0, #24
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov.h v0[1], w8
+; CHECK-GI-NEXT: add.2s v1, v1, v2
+; CHECK-GI-NEXT: uzp1.4h v1, v1, v0
+; CHECK-GI-NEXT: neg.4h v0, v0
+; CHECK-GI-NEXT: ushl.4h v0, v1, v0
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
%add = add nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -1052,13 +1531,31 @@ define <2 x i16> @rhadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
}
define <2 x i16> @rhadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
-; CHECK-LABEL: rhadd8x2_zext_lsr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi d2, #0x0000ff000000ff
-; CHECK-NEXT: and.8b v1, v1, v2
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: urhadd.2s v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: rhadd8x2_zext_lsr:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-SD-NEXT: and.8b v1, v1, v2
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: urhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: rhadd8x2_zext_lsr:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: and.8b v0, v0, v2
+; CHECK-GI-NEXT: and.8b v1, v1, v2
+; CHECK-GI-NEXT: dup.2s v2, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v1
+; CHECK-GI-NEXT: fmov s1, w8
+; CHECK-GI-NEXT: add.2s v0, v0, v2
+; CHECK-GI-NEXT: mov.h v1[1], w8
+; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
+; CHECK-GI-NEXT: neg.4h v1, v1
+; CHECK-GI-NEXT: ushl.4h v0, v0, v1
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
%add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
@@ -1069,12 +1566,20 @@ define <2 x i16> @rhadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
define void @testLowerToSHADD8b_c(<8 x i8> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD8b_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8b v1, #10
-; CHECK-NEXT: shadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD8b_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8b v1, #10
+; CHECK-SD-NEXT: shadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD8b_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v1, #10
+; CHECK-GI-NEXT: saddw.8h v0, v1, v0
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i8> %src1 to <8 x i16>
%add = add nsw <8 x i16> %sextsrc1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
%resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1084,12 +1589,20 @@ define void @testLowerToSHADD8b_c(<8 x i8> %src1, ptr nocapture writeonly %dest)
}
define void @testLowerToSHADD4h_c(<4 x i16> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD4h_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.4h v1, #10
-; CHECK-NEXT: shadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD4h_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.4h v1, #10
+; CHECK-SD-NEXT: shadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD4h_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v1, #10
+; CHECK-GI-NEXT: saddw.4s v0, v1, v0
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i16> %src1 to <4 x i32>
%add = add nsw <4 x i32> %sextsrc1, <i32 10, i32 10, i32 10, i32 10>
%resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
@@ -1099,12 +1612,21 @@ define void @testLowerToSHADD4h_c(<4 x i16> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToSHADD2s_c(<2 x i32> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD2s_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.2s v1, #10
-; CHECK-NEXT: shadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD2s_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.2s v1, #10
+; CHECK-SD-NEXT: shadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD2s_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI74_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI74_0]
+; CHECK-GI-NEXT: saddw.2d v0, v1, v0
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <2 x i32> %src1 to <2 x i64>
%add = add nsw <2 x i64> %sextsrc1, <i64 10, i64 10>
%resulti16 = lshr <2 x i64> %add, <i64 1, i64 1>
@@ -1114,12 +1636,22 @@ define void @testLowerToSHADD2s_c(<2 x i32> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToSHADD16b_c(<16 x i8> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD16b_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.16b v1, #10
-; CHECK-NEXT: shadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD16b_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.16b v1, #10
+; CHECK-SD-NEXT: shadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD16b_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v1, #10
+; CHECK-GI-NEXT: saddw.8h v2, v1, v0
+; CHECK-GI-NEXT: saddw2.8h v0, v1, v0
+; CHECK-GI-NEXT: shrn.8b v1, v2, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <16 x i8> %src1 to <16 x i16>
%add = add nsw <16 x i16> %sextsrc1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
%resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1129,12 +1661,22 @@ define void @testLowerToSHADD16b_c(<16 x i8> %src1, ptr nocapture writeonly %des
}
define void @testLowerToSHADD8h_c(<8 x i16> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD8h_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8h v1, #10
-; CHECK-NEXT: shadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD8h_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8h v1, #10
+; CHECK-SD-NEXT: shadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD8h_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v1, #10
+; CHECK-GI-NEXT: saddw.4s v2, v1, v0
+; CHECK-GI-NEXT: saddw2.4s v0, v1, v0
+; CHECK-GI-NEXT: shrn.4h v1, v2, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%add = add nsw <8 x i32> %sextsrc1, <i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1144,12 +1686,23 @@ define void @testLowerToSHADD8h_c(<8 x i16> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToSHADD4s_c(<4 x i32> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToSHADD4s_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.4s v1, #10
-; CHECK-NEXT: shadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToSHADD4s_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.4s v1, #10
+; CHECK-SD-NEXT: shadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToSHADD4s_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI77_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI77_0]
+; CHECK-GI-NEXT: saddw.2d v2, v1, v0
+; CHECK-GI-NEXT: saddw2.2d v0, v1, v0
+; CHECK-GI-NEXT: shrn.2s v1, v2, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%sextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%add = add nsw <4 x i64> %sextsrc1, <i64 10, i64 10, i64 10, i64 10>
%resulti16 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
@@ -1159,12 +1712,20 @@ define void @testLowerToSHADD4s_c(<4 x i32> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToUHADD8b_c(<8 x i8> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD8b_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8b v1, #10
-; CHECK-NEXT: uhadd.8b v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD8b_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8b v1, #10
+; CHECK-SD-NEXT: uhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD8b_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v1, #10
+; CHECK-GI-NEXT: uaddw.8h v0, v1, v0
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i8> %src1 to <8 x i16>
%add = add nuw nsw <8 x i16> %zextsrc1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
%resulti16 = lshr <8 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1174,12 +1735,20 @@ define void @testLowerToUHADD8b_c(<8 x i8> %src1, ptr nocapture writeonly %dest)
}
define void @testLowerToUHADD4h_c(<4 x i16> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD4h_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.4h v1, #10
-; CHECK-NEXT: uhadd.4h v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD4h_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.4h v1, #10
+; CHECK-SD-NEXT: uhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD4h_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v1, #10
+; CHECK-GI-NEXT: uaddw.4s v0, v1, v0
+; CHECK-GI-NEXT: shrn.4h v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i16> %src1 to <4 x i32>
%add = add nuw nsw <4 x i32> %zextsrc1, <i32 10, i32 10, i32 10, i32 10>
%resulti16 = lshr <4 x i32> %add, <i32 1, i32 1, i32 1, i32 1>
@@ -1189,12 +1758,21 @@ define void @testLowerToUHADD4h_c(<4 x i16> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToUHADD2s_c(<2 x i32> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD2s_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.2s v1, #10
-; CHECK-NEXT: uhadd.2s v0, v0, v1
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD2s_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.2s v1, #10
+; CHECK-SD-NEXT: uhadd.2s v0, v0, v1
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD2s_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI80_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI80_0]
+; CHECK-GI-NEXT: uaddw.2d v0, v1, v0
+; CHECK-GI-NEXT: shrn.2s v0, v0, #1
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i32> %src1 to <2 x i64>
%add = add nuw nsw <2 x i64> %zextsrc1, <i64 10, i64 10>
%resulti16 = lshr <2 x i64> %add, <i64 1, i64 1>
@@ -1204,12 +1782,22 @@ define void @testLowerToUHADD2s_c(<2 x i32> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToUHADD16b_c(<16 x i8> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD16b_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.16b v1, #10
-; CHECK-NEXT: uhadd.16b v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD16b_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.16b v1, #10
+; CHECK-SD-NEXT: uhadd.16b v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD16b_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v1, #10
+; CHECK-GI-NEXT: uaddw.8h v2, v1, v0
+; CHECK-GI-NEXT: uaddw2.8h v0, v1, v0
+; CHECK-GI-NEXT: shrn.8b v1, v2, #1
+; CHECK-GI-NEXT: shrn2.16b v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <16 x i8> %src1 to <16 x i16>
%add = add nuw nsw <16 x i16> %zextsrc1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
%resulti16 = lshr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -1219,12 +1807,22 @@ define void @testLowerToUHADD16b_c(<16 x i8> %src1, ptr nocapture writeonly %des
}
define void @testLowerToUHADD8h_c(<8 x i16> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD8h_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8h v1, #10
-; CHECK-NEXT: uhadd.8h v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD8h_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8h v1, #10
+; CHECK-SD-NEXT: uhadd.8h v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD8h_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.4s v1, #10
+; CHECK-GI-NEXT: uaddw.4s v2, v1, v0
+; CHECK-GI-NEXT: uaddw2.4s v0, v1, v0
+; CHECK-GI-NEXT: shrn.4h v1, v2, #1
+; CHECK-GI-NEXT: shrn2.8h v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%add = add nuw nsw <8 x i32> %zextsrc1, <i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -1234,12 +1832,23 @@ define void @testLowerToUHADD8h_c(<8 x i16> %src1, ptr nocapture writeonly %dest
}
define void @testLowerToUHADD4s_c(<4 x i32> %src1, ptr nocapture writeonly %dest) {
-; CHECK-LABEL: testLowerToUHADD4s_c:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.4s v1, #10
-; CHECK-NEXT: uhadd.4s v0, v0, v1
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: testLowerToUHADD4s_c:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.4s v1, #10
+; CHECK-SD-NEXT: uhadd.4s v0, v0, v1
+; CHECK-SD-NEXT: str q0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: testLowerToUHADD4s_c:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI83_0
+; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI83_0]
+; CHECK-GI-NEXT: uaddw.2d v2, v1, v0
+; CHECK-GI-NEXT: uaddw2.2d v0, v1, v0
+; CHECK-GI-NEXT: shrn.2s v1, v2, #1
+; CHECK-GI-NEXT: shrn2.4s v1, v0, #1
+; CHECK-GI-NEXT: str q1, [x0]
+; CHECK-GI-NEXT: ret
%zextsrc1 = zext <4 x i32> %src1 to <4 x i64>
%add = add nuw nsw <4 x i64> %zextsrc1, <i64 10, i64 10, i64 10, i64 10>
%resulti16 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
@@ -1249,13 +1858,21 @@ define void @testLowerToUHADD4s_c(<4 x i32> %src1, ptr nocapture writeonly %dest
}
define <8 x i8> @andmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) {
-; CHECK-LABEL: andmaskv8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8b v2, #7
-; CHECK-NEXT: xtn.8b v0, v0
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: uhadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: andmaskv8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8b v2, #7
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: uhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: andmaskv8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #7
+; CHECK-GI-NEXT: and.16b v0, v0, v2
+; CHECK-GI-NEXT: uaddw.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = zext <8 x i8> %src2 to <8 x i16>
%add = add nuw nsw <8 x i16> %zextsrc1, %zextsrc2
@@ -1265,13 +1882,24 @@ define <8 x i8> @andmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) {
}
define <16 x i8> @andmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) {
-; CHECK-LABEL: andmaskv16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.16b v3, #7
-; CHECK-NEXT: uzp1.16b v0, v0, v1
-; CHECK-NEXT: and.16b v0, v0, v3
-; CHECK-NEXT: uhadd.16b v0, v0, v2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: andmaskv16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.16b v3, #7
+; CHECK-SD-NEXT: uzp1.16b v0, v0, v1
+; CHECK-SD-NEXT: and.16b v0, v0, v3
+; CHECK-SD-NEXT: uhadd.16b v0, v0, v2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: andmaskv16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v3, #7
+; CHECK-GI-NEXT: and.16b v0, v0, v3
+; CHECK-GI-NEXT: and.16b v1, v1, v3
+; CHECK-GI-NEXT: uaddw.8h v0, v0, v2
+; CHECK-GI-NEXT: uaddw2.8h v1, v1, v2
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: shrn2.16b v0, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = zext <16 x i8> %src2 to <16 x i16>
%add = add nuw nsw <16 x i16> %zextsrc1, %zextsrc2
@@ -1281,16 +1909,30 @@ define <16 x i8> @andmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) {
}
define <16 x i8> @andmask2v16i8(<16 x i16> %src1, <16 x i16> %src2) {
-; CHECK-LABEL: andmask2v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1.16b v2, v2, v3
-; CHECK-NEXT: movi.16b v3, #3
-; CHECK-NEXT: uzp1.16b v0, v0, v1
-; CHECK-NEXT: movi.16b v1, #7
-; CHECK-NEXT: and.16b v2, v2, v3
-; CHECK-NEXT: and.16b v0, v0, v1
-; CHECK-NEXT: uhadd.16b v0, v0, v2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: andmask2v16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1.16b v2, v2, v3
+; CHECK-SD-NEXT: movi.16b v3, #3
+; CHECK-SD-NEXT: uzp1.16b v0, v0, v1
+; CHECK-SD-NEXT: movi.16b v1, #7
+; CHECK-SD-NEXT: and.16b v2, v2, v3
+; CHECK-SD-NEXT: and.16b v0, v0, v1
+; CHECK-SD-NEXT: uhadd.16b v0, v0, v2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: andmask2v16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v4, #7
+; CHECK-GI-NEXT: movi.8h v5, #3
+; CHECK-GI-NEXT: and.16b v0, v0, v4
+; CHECK-GI-NEXT: and.16b v2, v2, v5
+; CHECK-GI-NEXT: and.16b v1, v1, v4
+; CHECK-GI-NEXT: and.16b v3, v3, v5
+; CHECK-GI-NEXT: add.8h v0, v0, v2
+; CHECK-GI-NEXT: add.8h v1, v1, v3
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: shrn2.16b v0, v1, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = and <16 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <16 x i16> %src2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%add = add nuw nsw <16 x i16> %zextsrc1, %zextsrc2
@@ -1300,14 +1942,24 @@ define <16 x i8> @andmask2v16i8(<16 x i16> %src1, <16 x i16> %src2) {
}
define <8 x i8> @andmask2v8i8(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: andmask2v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8b v2, #7
-; CHECK-NEXT: xtn.8b v0, v0
-; CHECK-NEXT: xtn.8b v1, v1
-; CHECK-NEXT: and.8b v0, v0, v2
-; CHECK-NEXT: uhadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: andmask2v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8b v2, #7
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: xtn.8b v1, v1
+; CHECK-SD-NEXT: and.8b v0, v0, v2
+; CHECK-SD-NEXT: uhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: andmask2v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #7
+; CHECK-GI-NEXT: movi.2d v3, #0xff00ff00ff00ff
+; CHECK-GI-NEXT: and.16b v0, v0, v2
+; CHECK-GI-NEXT: and.16b v1, v1, v3
+; CHECK-GI-NEXT: add.8h v0, v0, v1
+; CHECK-GI-NEXT: shrn.8b v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <8 x i16> %src2, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%add = add nuw nsw <8 x i16> %zextsrc1, %zextsrc2
@@ -1317,13 +1969,23 @@ define <8 x i8> @andmask2v8i8(<8 x i16> %src1, <8 x i16> %src2) {
}
define <8 x i16> @andmask3v8i8(<8 x i16> %src1, <8 x i16> %src2) {
-; CHECK-LABEL: andmask3v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi.8h v2, #7
-; CHECK-NEXT: bic.8h v1, #254, lsl #8
-; CHECK-NEXT: and.16b v0, v0, v2
-; CHECK-NEXT: uhadd.8h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: andmask3v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi.8h v2, #7
+; CHECK-SD-NEXT: bic.8h v1, #254, lsl #8
+; CHECK-SD-NEXT: and.16b v0, v0, v2
+; CHECK-SD-NEXT: uhadd.8h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: andmask3v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.8h v2, #7
+; CHECK-GI-NEXT: mvni.8h v3, #254, lsl #8
+; CHECK-GI-NEXT: and.16b v1, v1, v3
+; CHECK-GI-NEXT: and.16b v0, v0, v2
+; CHECK-GI-NEXT: add.8h v0, v0, v1
+; CHECK-GI-NEXT: ushr.8h v0, v0, #1
+; CHECK-GI-NEXT: ret
%zextsrc1 = and <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%zextsrc2 = and <8 x i16> %src2, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
%add = add nuw nsw <8 x i16> %zextsrc1, %zextsrc2
@@ -1332,13 +1994,23 @@ define <8 x i16> @andmask3v8i8(<8 x i16> %src1, <8 x i16> %src2) {
}
define <16 x i8> @sextmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) {
-; CHECK-LABEL: sextmaskv16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr.8h v1, v1, #11
-; CHECK-NEXT: sshr.8h v0, v0, #11
-; CHECK-NEXT: uzp1.16b v0, v0, v1
-; CHECK-NEXT: shadd.16b v0, v0, v2
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sextmaskv16i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr.8h v1, v1, #11
+; CHECK-SD-NEXT: sshr.8h v0, v0, #11
+; CHECK-SD-NEXT: uzp1.16b v0, v0, v1
+; CHECK-SD-NEXT: shadd.16b v0, v0, v2
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sextmaskv16i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v3, v2, #0
+; CHECK-GI-NEXT: sshr.8h v1, v1, #11
+; CHECK-GI-NEXT: ssra.8h v3, v0, #11
+; CHECK-GI-NEXT: saddw2.8h v1, v1, v2
+; CHECK-GI-NEXT: shrn.8b v0, v3, #1
+; CHECK-GI-NEXT: shrn2.16b v0, v1, #1
+; CHECK-GI-NEXT: ret
%sextsrc1 = ashr <16 x i16> %src1, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
%sextsrc2 = sext <16 x i8> %src2 to <16 x i16>
%add = add nsw <16 x i16> %sextsrc1, %sextsrc2
@@ -1348,12 +2020,19 @@ define <16 x i8> @sextmaskv16i8(<16 x i16> %src1, <16 x i8> %src2) {
}
define <8 x i8> @sextmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) {
-; CHECK-LABEL: sextmaskv8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sshr.8h v0, v0, #11
-; CHECK-NEXT: xtn.8b v0, v0
-; CHECK-NEXT: shadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sextmaskv8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sshr.8h v0, v0, #11
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: shadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sextmaskv8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v1, v1, #0
+; CHECK-GI-NEXT: ssra.8h v1, v0, #11
+; CHECK-GI-NEXT: shrn.8b v0, v1, #1
+; CHECK-GI-NEXT: ret
%sextsrc1 = ashr <8 x i16> %src1, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
%sextsrc2 = sext <8 x i8> %src2 to <8 x i16>
%add = add nsw <8 x i16> %sextsrc1, %sextsrc2
@@ -1363,11 +2042,18 @@ define <8 x i8> @sextmaskv8i8(<8 x i16> %src1, <8 x i8> %src2) {
}
define <8 x i8> @sextmask2v8i8(<8 x i16> %src1, <8 x i8> %src2) {
-; CHECK-LABEL: sextmask2v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: shrn.8b v0, v0, #8
-; CHECK-NEXT: shadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sextmask2v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: shrn.8b v0, v0, #8
+; CHECK-SD-NEXT: shadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sextmask2v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v1, v1, #0
+; CHECK-GI-NEXT: ssra.8h v1, v0, #8
+; CHECK-GI-NEXT: shrn.8b v0, v1, #1
+; CHECK-GI-NEXT: ret
%sextsrc1 = ashr <8 x i16> %src1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%sextsrc2 = sext <8 x i8> %src2 to <8 x i16>
%add = add nsw <8 x i16> %sextsrc1, %sextsrc2
@@ -1377,13 +2063,20 @@ define <8 x i8> @sextmask2v8i8(<8 x i16> %src1, <8 x i8> %src2) {
}
define <8 x i8> @sextmask3v8i8(<8 x i16> %src1, <8 x i8> %src2) {
-; CHECK-LABEL: sextmask3v8i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushr.8h v0, v0, #7
-; CHECK-NEXT: sshll.8h v1, v1, #0
-; CHECK-NEXT: shadd.8h v0, v0, v1
-; CHECK-NEXT: xtn.8b v0, v0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sextmask3v8i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ushr.8h v0, v0, #7
+; CHECK-SD-NEXT: sshll.8h v1, v1, #0
+; CHECK-SD-NEXT: shadd.8h v0, v0, v1
+; CHECK-SD-NEXT: xtn.8b v0, v0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sextmask3v8i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v1, v1, #0
+; CHECK-GI-NEXT: ssra.8h v1, v0, #7
+; CHECK-GI-NEXT: shrn.8b v0, v1, #1
+; CHECK-GI-NEXT: ret
%1 = ashr <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
%sextsrc2 = sext <8 x i8> %src2 to <8 x i16>
%add = add nsw <8 x i16> %1, %sextsrc2
@@ -1409,10 +2102,18 @@ define <4 x i16> @ext_via_i19(<4 x i16> %a) {
}
define <8 x i8> @srhadd_v8i8_trunc(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: srhadd_v8i8_trunc:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v8i8_trunc:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v8i8_trunc:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.8h v0, v0, #0
+; CHECK-GI-NEXT: sshll.8h v1, v1, #0
+; CHECK-GI-NEXT: urhadd.8h v0, v0, v1
+; CHECK-GI-NEXT: xtn.8b v0, v0
+; CHECK-GI-NEXT: ret
%s0s = sext <8 x i8> %s0 to <8 x i16>
%s1s = sext <8 x i8> %s1 to <8 x i16>
%s = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %s0s, <8 x i16> %s1s)
@@ -1421,10 +2122,18 @@ define <8 x i8> @srhadd_v8i8_trunc(<8 x i8> %s0, <8 x i8> %s1) {
}
define <4 x i16> @srhadd_v4i16_trunc(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: srhadd_v4i16_trunc:
-; CHECK: // %bb.0:
-; CHECK-NEXT: srhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srhadd_v4i16_trunc:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: srhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srhadd_v4i16_trunc:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: sshll.4s v0, v0, #0
+; CHECK-GI-NEXT: sshll.4s v1, v1, #0
+; CHECK-GI-NEXT: urhadd.4s v0, v0, v1
+; CHECK-GI-NEXT: xtn.4h v0, v0
+; CHECK-GI-NEXT: ret
%s0s = sext <4 x i16> %s0 to <4 x i32>
%s1s = sext <4 x i16> %s1 to <4 x i32>
%s = call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %s0s, <4 x i32> %s1s)
@@ -1451,10 +2160,18 @@ define <2 x i32> @srhadd_v2i32_trunc(<2 x i32> %s0, <2 x i32> %s1) {
}
define <8 x i8> @urhadd_v8i8_trunc(<8 x i8> %s0, <8 x i8> %s1) {
-; CHECK-LABEL: urhadd_v8i8_trunc:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.8b v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v8i8_trunc:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.8b v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v8i8_trunc:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.8h v0, v0, #0
+; CHECK-GI-NEXT: ushll.8h v1, v1, #0
+; CHECK-GI-NEXT: srhadd.8h v0, v0, v1
+; CHECK-GI-NEXT: xtn.8b v0, v0
+; CHECK-GI-NEXT: ret
%s0s = zext <8 x i8> %s0 to <8 x i16>
%s1s = zext <8 x i8> %s1 to <8 x i16>
%s = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %s0s, <8 x i16> %s1s)
@@ -1463,10 +2180,18 @@ define <8 x i8> @urhadd_v8i8_trunc(<8 x i8> %s0, <8 x i8> %s1) {
}
define <4 x i16> @urhadd_v4i16_trunc(<4 x i16> %s0, <4 x i16> %s1) {
-; CHECK-LABEL: urhadd_v4i16_trunc:
-; CHECK: // %bb.0:
-; CHECK-NEXT: urhadd.4h v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urhadd_v4i16_trunc:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: urhadd.4h v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urhadd_v4i16_trunc:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll.4s v0, v0, #0
+; CHECK-GI-NEXT: ushll.4s v1, v1, #0
+; CHECK-GI-NEXT: srhadd.4s v0, v0, v1
+; CHECK-GI-NEXT: xtn.4h v0, v0
+; CHECK-GI-NEXT: ret
%s0s = zext <4 x i16> %s0 to <4 x i32>
%s1s = zext <4 x i16> %s1 to <4 x i32>
%s = call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %s0s, <4 x i32> %s1s)
>From 812a78c1aecff3e04e8d3334616876800ab6bb41 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 6 Nov 2025 10:28:07 +0000
Subject: [PATCH 13/18] [AArch64][GlobalISel] Removed redundant
AArch64-specific GI node definitions
Now that avg(floor/ceil)(u/s) are generic intrinsics, with GI node definitions in the generic SelectionDAGCompat.td, the AArch64-specific defintions have been removed.
---
llvm/lib/Target/AArch64/AArch64InstrGISel.td | 5 -----
1 file changed, 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index dffff27ce94aa..30b7b03f7a69a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -286,11 +286,6 @@ def : GINodeEquiv<G_UDOT, AArch64udot>;
def : GINodeEquiv<G_SDOT, AArch64sdot>;
def : GINodeEquiv<G_USDOT, AArch64usdot>;
-def : GINodeEquiv<G_UAVGFLOOR, avgflooru>;
-def : GINodeEquiv<G_UAVGCEIL, avgceilu>;
-def : GINodeEquiv<G_SAVGFLOOR, avgfloors>;
-def : GINodeEquiv<G_SAVGCEIL, avgceils>;
-
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
def : GINodeEquiv<G_AARCH64_PREFETCH, AArch64Prefetch>;
>From 000badb11d827bb241735f22d32e12d4c6f65679 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 6 Nov 2025 10:34:48 +0000
Subject: [PATCH 14/18] [AArch64][GlobalISel] Fixed typo in Generic Opcode
example
---
llvm/docs/GlobalISel/GenericOpcode.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 72cb8c6efca10..329d9d13ebddd 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -515,7 +515,7 @@ G_UAVGFLOOR, G_UAVGCEIL, G_SAVGFLOOR, G_SAVGCEIL
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Computes the average of corresponding elements in two vectors (signed and unsigned).
-Resulting vector contains values that are either rounded or truncated. e.g. trunc(shr(ext(a)+ext(b))).
+Resulting vector contains values that are either rounded or truncated. e.g. trunc(shr(add(ext(a),ext(b)),1)).
.. code-block:: none
>From 4afac538d8172d7e94bad0fb6a0c9b83b69cadc8 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <josh.rodriguez at arm.com>
Date: Thu, 6 Nov 2025 17:04:57 +0000
Subject: [PATCH 15/18] [RISCV][GlobalISel] Added intrinsics to
legalizer-info-validation.mir
Test has been modified to include the new generic hadd intrinsics. hadd intrinsics do not lower on RISC-V.
Also fixed formatting on above lines in test.
---
.../GlobalISel/legalizer-info-validation.mir | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index da7546e12e58b..5379681b1a065 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -73,13 +73,29 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+#
+# DEBUG-NEXT: G_UAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
#
-# DEBUG-NEXT:G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
-# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_UAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+#
+# DEBUG-NEXT: G_SAVGFLOOR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+#
+# DEBUG-NEXT: G_SAVGCEIL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
#
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
>From 0c30de5c3e4966e698aadd2d7b9e1236bd0b4323 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <Josh.Rodriguez at arm.com>
Date: Tue, 11 Nov 2025 17:25:33 +0000
Subject: [PATCH 16/18] [X86][GlobalISel] Patched vocabs-basic.ll test
First of 3 tests that need changing due to implementation of new generic intrinsics.
---
.../test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt | 4 ++++
.../MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
index 000c67efb1de7..190424cf1d65a 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
@@ -490,6 +490,8 @@ Key: G_ROTR: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
+Key: G_SAVGCEIL: [ 0.00 0.00 ]
+Key: G_SAVGFLOOR: [ 0.00 0.00 ]
Key: G_SBFX: [ 0.00 0.00 ]
Key: G_SCMP: [ 0.00 0.00 ]
Key: G_SDIV: [ 0.00 0.00 ]
@@ -539,6 +541,8 @@ Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
+Key: G_UAVGCEIL: [ 0.00 0.00 ]
+Key: G_UAVGFLOOR: [ 0.00 0.00 ]
Key: G_UBFX: [ 0.00 0.00 ]
Key: G_UBSANTRAP: [ 0.00 0.00 ]
Key: G_UCMP: [ 0.00 0.00 ]
diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
index bb72886f73bfd..b570aa7c7d83c 100644
--- a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
+++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
@@ -490,6 +490,8 @@ Key: G_ROTR: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
+Key: G_SAVGCEIL: [ 0.00 0.00 ]
+Key: G_SAVGFLOOR: [ 0.00 0.00 ]
Key: G_SBFX: [ 0.00 0.00 ]
Key: G_SCMP: [ 0.00 0.00 ]
Key: G_SDIV: [ 0.00 0.00 ]
@@ -539,6 +541,8 @@ Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
+Key: G_UAVGCEIL: [ 0.00 0.00 ]
+Key: G_UAVGFLOOR: [ 0.00 0.00 ]
Key: G_UBFX: [ 0.00 0.00 ]
Key: G_UBSANTRAP: [ 0.00 0.00 ]
Key: G_UCMP: [ 0.00 0.00 ]
>From 729a7ada15b5cf5c97ee6409c1743c359aa007b0 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <Josh.Rodriguez at arm.com>
Date: Tue, 18 Nov 2025 10:26:32 +0000
Subject: [PATCH 17/18] [X86][GlobalISel] Patched entities.mir test
Second of 3 tests that need chaning due to implementation of new generic intrinsics
---
.../output/reference_x86_entities.txt | 13324 ++++++++--------
1 file changed, 6664 insertions(+), 6660 deletions(-)
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
index dbbbbc746a769..20ee83953c3e7 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt
@@ -1,4 +1,4 @@
-7151
+7155
AAA 0
AAD 1
AADD 2
@@ -491,6662 +491,6666 @@ G_ROTR 488
G_SADDE 489
G_SADDO 490
G_SADDSAT 491
-G_SBFX 492
-G_SCMP 493
-G_SDIV 494
-G_SDIVFIX 495
-G_SDIVFIXSAT 496
-G_SDIVREM 497
-G_SELECT 498
-G_SET_FPENV 499
-G_SET_FPMODE 500
-G_SET_ROUNDING 501
-G_SEXT 502
-G_SEXTLOAD 503
-G_SEXT_INREG 504
-G_SHL 505
-G_SHUFFLE_VECTOR 506
-G_SITOFP 507
-G_SMAX 508
-G_SMIN 509
-G_SMULFIX 510
-G_SMULFIXSAT 511
-G_SMULH 512
-G_SMULO 513
-G_SPLAT_VECTOR 514
-G_SREM 515
-G_SSHLSAT 516
-G_SSUBE 517
-G_SSUBO 518
-G_SSUBSAT 519
-G_STACKRESTORE 520
-G_STACKSAVE 521
-G_STEP_VECTOR 522
-G_STORE 523
-G_STRICT_FADD 524
-G_STRICT_FDIV 525
-G_STRICT_FLDEXP 526
-G_STRICT_FMA 527
-G_STRICT_FMUL 528
-G_STRICT_FREM 529
-G_STRICT_FSQRT 530
-G_STRICT_FSUB 531
-G_SUB 532
-G_TRAP 533
-G_TRUNC 534
-G_TRUNC_SSAT_S 535
-G_TRUNC_SSAT_U 536
-G_TRUNC_USAT_U 537
-G_UADDE 538
-G_UADDO 539
-G_UADDSAT 540
-G_UBFX 541
-G_UBSANTRAP 542
-G_UCMP 543
-G_UDIV 544
-G_UDIVFIX 545
-G_UDIVFIXSAT 546
-G_UDIVREM 547
-G_UITOFP 548
-G_UMAX 549
-G_UMIN 550
-G_UMULFIX 551
-G_UMULFIXSAT 552
-G_UMULH 553
-G_UMULO 554
-G_UNMERGE_VALUES 555
-G_UREM 556
-G_USHLSAT 557
-G_USUBE 558
-G_USUBO 559
-G_USUBSAT 560
-G_VAARG 561
-G_VASTART 562
-G_VECREDUCE_ADD 563
-G_VECREDUCE_AND 564
-G_VECREDUCE_FADD 565
-G_VECREDUCE_FMAX 566
-G_VECREDUCE_FMAXIMUM 567
-G_VECREDUCE_FMIN 568
-G_VECREDUCE_FMINIMUM 569
-G_VECREDUCE_FMUL 570
-G_VECREDUCE_MUL 571
-G_VECREDUCE_OR 572
-G_VECREDUCE_SEQ_FADD 573
-G_VECREDUCE_SEQ_FMUL 574
-G_VECREDUCE_SMAX 575
-G_VECREDUCE_SMIN 576
-G_VECREDUCE_UMAX 577
-G_VECREDUCE_UMIN 578
-G_VECREDUCE_XOR 579
-G_VECTOR_COMPRESS 580
-G_VSCALE 581
-G_WRITE_REGISTER 582
-G_XOR 583
-G_ZEXT 584
-G_ZEXTLOAD 585
-HADDPDrm 586
-HADDPDrr 587
-HADDPSrm 588
-HADDPSrr 589
-HLT 590
-HRESET 591
-HSUBPDrm 592
-HSUBPDrr 593
-HSUBPSrm 594
-HSUBPSrr 595
-ICALL_BRANCH_FUNNEL 596
-IDIV 597
-ILD_F 598
-ILD_Fp 599
-IMPLICIT_DEF 600
-IMUL 601
-IMULZU 602
-IN 603
-INC 604
-INCSSPD 605
-INCSSPQ 606
-INDIRECT_THUNK_CALL 607
-INDIRECT_THUNK_TCRETURN 608
-INIT_UNDEF 609
-INLINEASM 610
-INLINEASM_BR 611
-INSB 612
-INSERTPSrmi 613
-INSERTPSrri 614
-INSERTQ 615
-INSERTQI 616
-INSERT_SUBREG 617
-INSL 618
-INSW 619
-INT 620
-INTO 621
-INVD 622
-INVEPT 623
-INVLPG 624
-INVLPGA 625
-INVLPGB 626
-INVPCID 627
-INVVPID 628
-IRET 629
-ISTT_FP 630
-ISTT_Fp 631
-IST_F 632
-IST_FP 633
-IST_Fp 634
-Int_eh_sjlj_setup_dispatch 635
-JCC 636
-JCXZ 637
-JECXZ 638
-JMP 639
-JMPABS 640
-JRCXZ 641
-JUMP_TABLE_DEBUG_INFO 642
-KADDBkk 643
-KADDDkk 644
-KADDQkk 645
-KADDWkk 646
-KANDBkk 647
-KANDDkk 648
-KANDNBkk 649
-KANDNDkk 650
-KANDNQkk 651
-KANDNWkk 652
-KANDQkk 653
-KANDWkk 654
-KCFI_CHECK 655
-KILL 656
-KMOVBkk 657
-KMOVBkk_EVEX 658
-KMOVBkm 659
-KMOVBkm_EVEX 660
-KMOVBkr 661
-KMOVBkr_EVEX 662
-KMOVBmk 663
-KMOVBmk_EVEX 664
-KMOVBrk 665
-KMOVBrk_EVEX 666
-KMOVDkk 667
-KMOVDkk_EVEX 668
-KMOVDkm 669
-KMOVDkm_EVEX 670
-KMOVDkr 671
-KMOVDkr_EVEX 672
-KMOVDmk 673
-KMOVDmk_EVEX 674
-KMOVDrk 675
-KMOVDrk_EVEX 676
-KMOVQkk 677
-KMOVQkk_EVEX 678
-KMOVQkm 679
-KMOVQkm_EVEX 680
-KMOVQkr 681
-KMOVQkr_EVEX 682
-KMOVQmk 683
-KMOVQmk_EVEX 684
-KMOVQrk 685
-KMOVQrk_EVEX 686
-KMOVWkk 687
-KMOVWkk_EVEX 688
-KMOVWkm 689
-KMOVWkm_EVEX 690
-KMOVWkr 691
-KMOVWkr_EVEX 692
-KMOVWmk 693
-KMOVWmk_EVEX 694
-KMOVWrk 695
-KMOVWrk_EVEX 696
-KNOTBkk 697
-KNOTDkk 698
-KNOTQkk 699
-KNOTWkk 700
-KORBkk 701
-KORDkk 702
-KORQkk 703
-KORTESTBkk 704
-KORTESTDkk 705
-KORTESTQkk 706
-KORTESTWkk 707
-KORWkk 708
-KSET 709
-KSHIFTLBki 710
-KSHIFTLDki 711
-KSHIFTLQki 712
-KSHIFTLWki 713
-KSHIFTRBki 714
-KSHIFTRDki 715
-KSHIFTRQki 716
-KSHIFTRWki 717
-KTESTBkk 718
-KTESTDkk 719
-KTESTQkk 720
-KTESTWkk 721
-KUNPCKBWkk 722
-KUNPCKDQkk 723
-KUNPCKWDkk 724
-KXNORBkk 725
-KXNORDkk 726
-KXNORQkk 727
-KXNORWkk 728
-KXORBkk 729
-KXORDkk 730
-KXORQkk 731
-KXORWkk 732
-LAHF 733
-LAR 734
-LCMPXCHG 735
-LDDQUrm 736
-LDMXCSR 737
-LDS 738
-LDTILECFG 739
-LDTILECFG_EVEX 740
-LD_F 741
-LD_Fp 742
-LD_Frr 743
-LEA 744
-LEAVE 745
-LES 746
-LFENCE 747
-LFS 748
-LGDT 749
-LGS 750
-LIDT 751
-LIFETIME_END 752
-LIFETIME_START 753
-LKGS 754
-LLDT 755
-LLWPCB 756
-LMSW 757
-LOADIWKEY 758
-LOAD_STACK_GUARD 759
-LOCAL_ESCAPE 760
-LOCK_ADD 761
-LOCK_AND 762
-LOCK_BTC 763
-LOCK_BTC_RM 764
-LOCK_BTR 765
-LOCK_BTR_RM 766
-LOCK_BTS 767
-LOCK_BTS_RM 768
-LOCK_DEC 769
-LOCK_INC 770
-LOCK_OR 771
-LOCK_PREFIX 772
-LOCK_SUB 773
-LOCK_XOR 774
-LODSB 775
-LODSL 776
-LODSQ 777
-LODSW 778
-LOOP 779
-LOOPE 780
-LOOPNE 781
-LRET 782
-LRETI 783
-LSL 784
-LSS 785
-LTRm 786
-LTRr 787
-LWPINS 788
-LWPVAL 789
-LXADD 790
-LZCNT 791
-MASKMOVDQU 792
-MASKPAIR 793
-MAXCPDrm 794
-MAXCPDrr 795
-MAXCPSrm 796
-MAXCPSrr 797
-MAXCSDrm 798
-MAXCSDrr 799
-MAXCSSrm 800
-MAXCSSrr 801
-MAXPDrm 802
-MAXPDrr 803
-MAXPSrm 804
-MAXPSrr 805
-MAXSDrm 806
-MAXSDrm_Int 807
-MAXSDrr 808
-MAXSDrr_Int 809
-MAXSSrm 810
-MAXSSrm_Int 811
-MAXSSrr 812
-MAXSSrr_Int 813
-MEMBARRIER 814
-MFENCE 815
-MINCPDrm 816
-MINCPDrr 817
-MINCPSrm 818
-MINCPSrr 819
-MINCSDrm 820
-MINCSDrr 821
-MINCSSrm 822
-MINCSSrr 823
-MINPDrm 824
-MINPDrr 825
-MINPSrm 826
-MINPSrr 827
-MINSDrm 828
-MINSDrm_Int 829
-MINSDrr 830
-MINSDrr_Int 831
-MINSSrm 832
-MINSSrm_Int 833
-MINSSrr 834
-MINSSrr_Int 835
-MMX_CVTPD 836
-MMX_CVTPI 837
-MMX_CVTPS 838
-MMX_CVTTPD 839
-MMX_CVTTPS 840
-MMX_EMMS 841
-MMX_MASKMOVQ 842
-MMX_MOVD 843
-MMX_MOVDQ 844
-MMX_MOVFR 845
-MMX_MOVNTQmr 846
-MMX_MOVQ 847
-MMX_PABSBrm 848
-MMX_PABSBrr 849
-MMX_PABSDrm 850
-MMX_PABSDrr 851
-MMX_PABSWrm 852
-MMX_PABSWrr 853
-MMX_PACKSSDWrm 854
-MMX_PACKSSDWrr 855
-MMX_PACKSSWBrm 856
-MMX_PACKSSWBrr 857
-MMX_PACKUSWBrm 858
-MMX_PACKUSWBrr 859
-MMX_PADDBrm 860
-MMX_PADDBrr 861
-MMX_PADDDrm 862
-MMX_PADDDrr 863
-MMX_PADDQrm 864
-MMX_PADDQrr 865
-MMX_PADDSBrm 866
-MMX_PADDSBrr 867
-MMX_PADDSWrm 868
-MMX_PADDSWrr 869
-MMX_PADDUSBrm 870
-MMX_PADDUSBrr 871
-MMX_PADDUSWrm 872
-MMX_PADDUSWrr 873
-MMX_PADDWrm 874
-MMX_PADDWrr 875
-MMX_PALIGNRrmi 876
-MMX_PALIGNRrri 877
-MMX_PANDNrm 878
-MMX_PANDNrr 879
-MMX_PANDrm 880
-MMX_PANDrr 881
-MMX_PAVGBrm 882
-MMX_PAVGBrr 883
-MMX_PAVGWrm 884
-MMX_PAVGWrr 885
-MMX_PCMPEQBrm 886
-MMX_PCMPEQBrr 887
-MMX_PCMPEQDrm 888
-MMX_PCMPEQDrr 889
-MMX_PCMPEQWrm 890
-MMX_PCMPEQWrr 891
-MMX_PCMPGTBrm 892
-MMX_PCMPGTBrr 893
-MMX_PCMPGTDrm 894
-MMX_PCMPGTDrr 895
-MMX_PCMPGTWrm 896
-MMX_PCMPGTWrr 897
-MMX_PEXTRWrri 898
-MMX_PHADDDrm 899
-MMX_PHADDDrr 900
-MMX_PHADDSWrm 901
-MMX_PHADDSWrr 902
-MMX_PHADDWrm 903
-MMX_PHADDWrr 904
-MMX_PHSUBDrm 905
-MMX_PHSUBDrr 906
-MMX_PHSUBSWrm 907
-MMX_PHSUBSWrr 908
-MMX_PHSUBWrm 909
-MMX_PHSUBWrr 910
-MMX_PINSRWrmi 911
-MMX_PINSRWrri 912
-MMX_PMADDUBSWrm 913
-MMX_PMADDUBSWrr 914
-MMX_PMADDWDrm 915
-MMX_PMADDWDrr 916
-MMX_PMAXSWrm 917
-MMX_PMAXSWrr 918
-MMX_PMAXUBrm 919
-MMX_PMAXUBrr 920
-MMX_PMINSWrm 921
-MMX_PMINSWrr 922
-MMX_PMINUBrm 923
-MMX_PMINUBrr 924
-MMX_PMOVMSKBrr 925
-MMX_PMULHRSWrm 926
-MMX_PMULHRSWrr 927
-MMX_PMULHUWrm 928
-MMX_PMULHUWrr 929
-MMX_PMULHWrm 930
-MMX_PMULHWrr 931
-MMX_PMULLWrm 932
-MMX_PMULLWrr 933
-MMX_PMULUDQrm 934
-MMX_PMULUDQrr 935
-MMX_PORrm 936
-MMX_PORrr 937
-MMX_PSADBWrm 938
-MMX_PSADBWrr 939
-MMX_PSHUFBrm 940
-MMX_PSHUFBrr 941
-MMX_PSHUFWmi 942
-MMX_PSHUFWri 943
-MMX_PSIGNBrm 944
-MMX_PSIGNBrr 945
-MMX_PSIGNDrm 946
-MMX_PSIGNDrr 947
-MMX_PSIGNWrm 948
-MMX_PSIGNWrr 949
-MMX_PSLLDri 950
-MMX_PSLLDrm 951
-MMX_PSLLDrr 952
-MMX_PSLLQri 953
-MMX_PSLLQrm 954
-MMX_PSLLQrr 955
-MMX_PSLLWri 956
-MMX_PSLLWrm 957
-MMX_PSLLWrr 958
-MMX_PSRADri 959
-MMX_PSRADrm 960
-MMX_PSRADrr 961
-MMX_PSRAWri 962
-MMX_PSRAWrm 963
-MMX_PSRAWrr 964
-MMX_PSRLDri 965
-MMX_PSRLDrm 966
-MMX_PSRLDrr 967
-MMX_PSRLQri 968
-MMX_PSRLQrm 969
-MMX_PSRLQrr 970
-MMX_PSRLWri 971
-MMX_PSRLWrm 972
-MMX_PSRLWrr 973
-MMX_PSUBBrm 974
-MMX_PSUBBrr 975
-MMX_PSUBDrm 976
-MMX_PSUBDrr 977
-MMX_PSUBQrm 978
-MMX_PSUBQrr 979
-MMX_PSUBSBrm 980
-MMX_PSUBSBrr 981
-MMX_PSUBSWrm 982
-MMX_PSUBSWrr 983
-MMX_PSUBUSBrm 984
-MMX_PSUBUSBrr 985
-MMX_PSUBUSWrm 986
-MMX_PSUBUSWrr 987
-MMX_PSUBWrm 988
-MMX_PSUBWrr 989
-MMX_PUNPCKHBWrm 990
-MMX_PUNPCKHBWrr 991
-MMX_PUNPCKHDQrm 992
-MMX_PUNPCKHDQrr 993
-MMX_PUNPCKHWDrm 994
-MMX_PUNPCKHWDrr 995
-MMX_PUNPCKLBWrm 996
-MMX_PUNPCKLBWrr 997
-MMX_PUNPCKLDQrm 998
-MMX_PUNPCKLDQrr 999
-MMX_PUNPCKLWDrm 1000
-MMX_PUNPCKLWDrr 1001
-MMX_PXORrm 1002
-MMX_PXORrr 1003
-MMX_SET 1004
-MONITOR 1005
-MONITORX 1006
-MONTMUL 1007
-MORESTACK_RET 1008
-MORESTACK_RET_RESTORE_R 1009
-MOV 1010
-MOVAPDmr 1011
-MOVAPDrm 1012
-MOVAPDrr 1013
-MOVAPDrr_REV 1014
-MOVAPSmr 1015
-MOVAPSrm 1016
-MOVAPSrr 1017
-MOVAPSrr_REV 1018
-MOVBE 1019
-MOVDDUPrm 1020
-MOVDDUPrr 1021
-MOVDI 1022
-MOVDIR 1023
-MOVDIRI 1024
-MOVDQAmr 1025
-MOVDQArm 1026
-MOVDQArr 1027
-MOVDQArr_REV 1028
-MOVDQUmr 1029
-MOVDQUrm 1030
-MOVDQUrr 1031
-MOVDQUrr_REV 1032
-MOVHLPSrr 1033
-MOVHPDmr 1034
-MOVHPDrm 1035
-MOVHPSmr 1036
-MOVHPSrm 1037
-MOVLHPSrr 1038
-MOVLPDmr 1039
-MOVLPDrm 1040
-MOVLPSmr 1041
-MOVLPSrm 1042
-MOVMSKPDrr 1043
-MOVMSKPSrr 1044
-MOVNTDQArm 1045
-MOVNTDQmr 1046
-MOVNTI 1047
-MOVNTImr 1048
-MOVNTPDmr 1049
-MOVNTPSmr 1050
-MOVNTSD 1051
-MOVNTSS 1052
-MOVPC 1053
-MOVPDI 1054
-MOVPQI 1055
-MOVPQIto 1056
-MOVQI 1057
-MOVRS 1058
-MOVSB 1059
-MOVSDmr 1060
-MOVSDrm 1061
-MOVSDrm_alt 1062
-MOVSDrr 1063
-MOVSDrr_REV 1064
-MOVSDto 1065
-MOVSHDUPrm 1066
-MOVSHDUPrr 1067
-MOVSHPmr 1068
-MOVSHPrm 1069
-MOVSL 1070
-MOVSLDUPrm 1071
-MOVSLDUPrr 1072
-MOVSQ 1073
-MOVSS 1074
-MOVSSmr 1075
-MOVSSrm 1076
-MOVSSrm_alt 1077
-MOVSSrr 1078
-MOVSSrr_REV 1079
-MOVSW 1080
-MOVSX 1081
-MOVUPDmr 1082
-MOVUPDrm 1083
-MOVUPDrr 1084
-MOVUPDrr_REV 1085
-MOVUPSmr 1086
-MOVUPSrm 1087
-MOVUPSrr 1088
-MOVUPSrr_REV 1089
-MOVZPQILo 1090
-MOVZX 1091
-MPSADBWrmi 1092
-MPSADBWrri 1093
-MUL 1094
-MULPDrm 1095
-MULPDrr 1096
-MULPSrm 1097
-MULPSrr 1098
-MULSDrm 1099
-MULSDrm_Int 1100
-MULSDrr 1101
-MULSDrr_Int 1102
-MULSSrm 1103
-MULSSrm_Int 1104
-MULSSrr 1105
-MULSSrr_Int 1106
-MULX 1107
-MUL_F 1108
-MUL_FI 1109
-MUL_FPrST 1110
-MUL_FST 1111
-MUL_Fp 1112
-MUL_FpI 1113
-MUL_FrST 1114
-MWAITX 1115
-MWAITX_SAVE_RBX 1116
-MWAITXrrr 1117
-MWAITrr 1118
-NEG 1119
-NOOP 1120
-NOOPL 1121
-NOOPLr 1122
-NOOPQ 1123
-NOOPQr 1124
-NOOPW 1125
-NOOPWr 1126
-NOT 1127
-OR 1128
-ORPDrm 1129
-ORPDrr 1130
-ORPSrm 1131
-ORPSrr 1132
-OUT 1133
-OUTSB 1134
-OUTSL 1135
-OUTSW 1136
-PABSBrm 1137
-PABSBrr 1138
-PABSDrm 1139
-PABSDrr 1140
-PABSWrm 1141
-PABSWrr 1142
-PACKSSDWrm 1143
-PACKSSDWrr 1144
-PACKSSWBrm 1145
-PACKSSWBrr 1146
-PACKUSDWrm 1147
-PACKUSDWrr 1148
-PACKUSWBrm 1149
-PACKUSWBrr 1150
-PADDBrm 1151
-PADDBrr 1152
-PADDDrm 1153
-PADDDrr 1154
-PADDQrm 1155
-PADDQrr 1156
-PADDSBrm 1157
-PADDSBrr 1158
-PADDSWrm 1159
-PADDSWrr 1160
-PADDUSBrm 1161
-PADDUSBrr 1162
-PADDUSWrm 1163
-PADDUSWrr 1164
-PADDWrm 1165
-PADDWrr 1166
-PALIGNRrmi 1167
-PALIGNRrri 1168
-PANDNrm 1169
-PANDNrr 1170
-PANDrm 1171
-PANDrr 1172
-PATCHABLE_EVENT_CALL 1173
-PATCHABLE_FUNCTION_ENTER 1174
-PATCHABLE_FUNCTION_EXIT 1175
-PATCHABLE_OP 1176
-PATCHABLE_RET 1177
-PATCHABLE_TAIL_CALL 1178
-PATCHABLE_TYPED_EVENT_CALL 1179
-PATCHPOINT 1180
-PAUSE 1181
-PAVGBrm 1182
-PAVGBrr 1183
-PAVGUSBrm 1184
-PAVGUSBrr 1185
-PAVGWrm 1186
-PAVGWrr 1187
-PBLENDVBrm 1188
-PBLENDVBrr 1189
-PBLENDWrmi 1190
-PBLENDWrri 1191
-PBNDKB 1192
-PCLMULQDQrmi 1193
-PCLMULQDQrri 1194
-PCMPEQBrm 1195
-PCMPEQBrr 1196
-PCMPEQDrm 1197
-PCMPEQDrr 1198
-PCMPEQQrm 1199
-PCMPEQQrr 1200
-PCMPEQWrm 1201
-PCMPEQWrr 1202
-PCMPESTRIrmi 1203
-PCMPESTRIrri 1204
-PCMPESTRMrmi 1205
-PCMPESTRMrri 1206
-PCMPGTBrm 1207
-PCMPGTBrr 1208
-PCMPGTDrm 1209
-PCMPGTDrr 1210
-PCMPGTQrm 1211
-PCMPGTQrr 1212
-PCMPGTWrm 1213
-PCMPGTWrr 1214
-PCMPISTRIrmi 1215
-PCMPISTRIrri 1216
-PCMPISTRMrmi 1217
-PCMPISTRMrri 1218
-PCONFIG 1219
-PDEP 1220
-PEXT 1221
-PEXTRBmri 1222
-PEXTRBrri 1223
-PEXTRDmri 1224
-PEXTRDrri 1225
-PEXTRQmri 1226
-PEXTRQrri 1227
-PEXTRWmri 1228
-PEXTRWrri 1229
-PEXTRWrri_REV 1230
-PF 1231
-PFACCrm 1232
-PFACCrr 1233
-PFADDrm 1234
-PFADDrr 1235
-PFCMPEQrm 1236
-PFCMPEQrr 1237
-PFCMPGErm 1238
-PFCMPGErr 1239
-PFCMPGTrm 1240
-PFCMPGTrr 1241
-PFMAXrm 1242
-PFMAXrr 1243
-PFMINrm 1244
-PFMINrr 1245
-PFMULrm 1246
-PFMULrr 1247
-PFNACCrm 1248
-PFNACCrr 1249
-PFPNACCrm 1250
-PFPNACCrr 1251
-PFRCPIT 1252
-PFRCPrm 1253
-PFRCPrr 1254
-PFRSQIT 1255
-PFRSQRTrm 1256
-PFRSQRTrr 1257
-PFSUBRrm 1258
-PFSUBRrr 1259
-PFSUBrm 1260
-PFSUBrr 1261
-PHADDDrm 1262
-PHADDDrr 1263
-PHADDSWrm 1264
-PHADDSWrr 1265
-PHADDWrm 1266
-PHADDWrr 1267
-PHI 1268
-PHMINPOSUWrm 1269
-PHMINPOSUWrr 1270
-PHSUBDrm 1271
-PHSUBDrr 1272
-PHSUBSWrm 1273
-PHSUBSWrr 1274
-PHSUBWrm 1275
-PHSUBWrr 1276
-PI 1277
-PINSRBrmi 1278
-PINSRBrri 1279
-PINSRDrmi 1280
-PINSRDrri 1281
-PINSRQrmi 1282
-PINSRQrri 1283
-PINSRWrmi 1284
-PINSRWrri 1285
-PLDTILECFGV 1286
-PLEA 1287
-PMADDUBSWrm 1288
-PMADDUBSWrr 1289
-PMADDWDrm 1290
-PMADDWDrr 1291
-PMAXSBrm 1292
-PMAXSBrr 1293
-PMAXSDrm 1294
-PMAXSDrr 1295
-PMAXSWrm 1296
-PMAXSWrr 1297
-PMAXUBrm 1298
-PMAXUBrr 1299
-PMAXUDrm 1300
-PMAXUDrr 1301
-PMAXUWrm 1302
-PMAXUWrr 1303
-PMINSBrm 1304
-PMINSBrr 1305
-PMINSDrm 1306
-PMINSDrr 1307
-PMINSWrm 1308
-PMINSWrr 1309
-PMINUBrm 1310
-PMINUBrr 1311
-PMINUDrm 1312
-PMINUDrr 1313
-PMINUWrm 1314
-PMINUWrr 1315
-PMOVMSKBrr 1316
-PMOVSXBDrm 1317
-PMOVSXBDrr 1318
-PMOVSXBQrm 1319
-PMOVSXBQrr 1320
-PMOVSXBWrm 1321
-PMOVSXBWrr 1322
-PMOVSXDQrm 1323
-PMOVSXDQrr 1324
-PMOVSXWDrm 1325
-PMOVSXWDrr 1326
-PMOVSXWQrm 1327
-PMOVSXWQrr 1328
-PMOVZXBDrm 1329
-PMOVZXBDrr 1330
-PMOVZXBQrm 1331
-PMOVZXBQrr 1332
-PMOVZXBWrm 1333
-PMOVZXBWrr 1334
-PMOVZXDQrm 1335
-PMOVZXDQrr 1336
-PMOVZXWDrm 1337
-PMOVZXWDrr 1338
-PMOVZXWQrm 1339
-PMOVZXWQrr 1340
-PMULDQrm 1341
-PMULDQrr 1342
-PMULHRSWrm 1343
-PMULHRSWrr 1344
-PMULHRWrm 1345
-PMULHRWrr 1346
-PMULHUWrm 1347
-PMULHUWrr 1348
-PMULHWrm 1349
-PMULHWrr 1350
-PMULLDrm 1351
-PMULLDrr 1352
-PMULLWrm 1353
-PMULLWrr 1354
-PMULUDQrm 1355
-PMULUDQrr 1356
-POP 1357
-POPA 1358
-POPCNT 1359
-POPDS 1360
-POPES 1361
-POPF 1362
-POPFS 1363
-POPGS 1364
-POPP 1365
-POPSS 1366
-PORrm 1367
-PORrr 1368
-PREALLOCATED_ARG 1369
-PREALLOCATED_SETUP 1370
-PREFETCH 1371
-PREFETCHIT 1372
-PREFETCHNTA 1373
-PREFETCHRST 1374
-PREFETCHT 1375
-PREFETCHW 1376
-PREFETCHWT 1377
-PROBED_ALLOCA 1378
-PSADBWrm 1379
-PSADBWrr 1380
-PSEUDO_PROBE 1381
-PSHUFBrm 1382
-PSHUFBrr 1383
-PSHUFDmi 1384
-PSHUFDri 1385
-PSHUFHWmi 1386
-PSHUFHWri 1387
-PSHUFLWmi 1388
-PSHUFLWri 1389
-PSIGNBrm 1390
-PSIGNBrr 1391
-PSIGNDrm 1392
-PSIGNDrr 1393
-PSIGNWrm 1394
-PSIGNWrr 1395
-PSLLDQri 1396
-PSLLDri 1397
-PSLLDrm 1398
-PSLLDrr 1399
-PSLLQri 1400
-PSLLQrm 1401
-PSLLQrr 1402
-PSLLWri 1403
-PSLLWrm 1404
-PSLLWrr 1405
-PSMASH 1406
-PSRADri 1407
-PSRADrm 1408
-PSRADrr 1409
-PSRAWri 1410
-PSRAWrm 1411
-PSRAWrr 1412
-PSRLDQri 1413
-PSRLDri 1414
-PSRLDrm 1415
-PSRLDrr 1416
-PSRLQri 1417
-PSRLQrm 1418
-PSRLQrr 1419
-PSRLWri 1420
-PSRLWrm 1421
-PSRLWrr 1422
-PSUBBrm 1423
-PSUBBrr 1424
-PSUBDrm 1425
-PSUBDrr 1426
-PSUBQrm 1427
-PSUBQrr 1428
-PSUBSBrm 1429
-PSUBSBrr 1430
-PSUBSWrm 1431
-PSUBSWrr 1432
-PSUBUSBrm 1433
-PSUBUSBrr 1434
-PSUBUSWrm 1435
-PSUBUSWrr 1436
-PSUBWrm 1437
-PSUBWrr 1438
-PSWAPDrm 1439
-PSWAPDrr 1440
-PTCMMIMFP 1441
-PTCMMRLFP 1442
-PTCVTROWD 1443
-PTCVTROWPS 1444
-PTDPBF 1445
-PTDPBHF 1446
-PTDPBSSD 1447
-PTDPBSSDV 1448
-PTDPBSUD 1449
-PTDPBSUDV 1450
-PTDPBUSD 1451
-PTDPBUSDV 1452
-PTDPBUUD 1453
-PTDPBUUDV 1454
-PTDPFP 1455
-PTDPHBF 1456
-PTDPHF 1457
-PTESTrm 1458
-PTESTrr 1459
-PTILELOADD 1460
-PTILELOADDRS 1461
-PTILELOADDRST 1462
-PTILELOADDRSV 1463
-PTILELOADDT 1464
-PTILELOADDV 1465
-PTILEMOVROWrre 1466
-PTILEMOVROWrreV 1467
-PTILEMOVROWrri 1468
-PTILEMOVROWrriV 1469
-PTILESTORED 1470
-PTILESTOREDV 1471
-PTILEZERO 1472
-PTILEZEROV 1473
-PTMMULTF 1474
-PTWRITE 1475
-PTWRITEm 1476
-PTWRITEr 1477
-PUNPCKHBWrm 1478
-PUNPCKHBWrr 1479
-PUNPCKHDQrm 1480
-PUNPCKHDQrr 1481
-PUNPCKHQDQrm 1482
-PUNPCKHQDQrr 1483
-PUNPCKHWDrm 1484
-PUNPCKHWDrr 1485
-PUNPCKLBWrm 1486
-PUNPCKLBWrr 1487
-PUNPCKLDQrm 1488
-PUNPCKLDQrr 1489
-PUNPCKLQDQrm 1490
-PUNPCKLQDQrr 1491
-PUNPCKLWDrm 1492
-PUNPCKLWDrr 1493
-PUSH 1494
-PUSHA 1495
-PUSHCS 1496
-PUSHDS 1497
-PUSHES 1498
-PUSHF 1499
-PUSHFS 1500
-PUSHGS 1501
-PUSHP 1502
-PUSHSS 1503
-PVALIDATE 1504
-PXORrm 1505
-PXORrr 1506
-RCL 1507
-RCPPSm 1508
-RCPPSr 1509
-RCPSSm 1510
-RCPSSm_Int 1511
-RCPSSr 1512
-RCPSSr_Int 1513
-RCR 1514
-RDFLAGS 1515
-RDFSBASE 1516
-RDGSBASE 1517
-RDMSR 1518
-RDMSRLIST 1519
-RDMSRri 1520
-RDMSRri_EVEX 1521
-RDPID 1522
-RDPKRUr 1523
-RDPMC 1524
-RDPRU 1525
-RDRAND 1526
-RDSEED 1527
-RDSSPD 1528
-RDSSPQ 1529
-RDTSC 1530
-RDTSCP 1531
-REG_SEQUENCE 1532
-REPNE_PREFIX 1533
-REP_MOVSB 1534
-REP_MOVSD 1535
-REP_MOVSQ 1536
-REP_MOVSW 1537
-REP_PREFIX 1538
-REP_STOSB 1539
-REP_STOSD 1540
-REP_STOSQ 1541
-REP_STOSW 1542
-RET 1543
-RETI 1544
-REX 1545
-RMPADJUST 1546
-RMPQUERY 1547
-RMPUPDATE 1548
-ROL 1549
-ROR 1550
-RORX 1551
-ROUNDPDmi 1552
-ROUNDPDri 1553
-ROUNDPSmi 1554
-ROUNDPSri 1555
-ROUNDSDmi 1556
-ROUNDSDmi_Int 1557
-ROUNDSDri 1558
-ROUNDSDri_Int 1559
-ROUNDSSmi 1560
-ROUNDSSmi_Int 1561
-ROUNDSSri 1562
-ROUNDSSri_Int 1563
-RSM 1564
-RSQRTPSm 1565
-RSQRTPSr 1566
-RSQRTSSm 1567
-RSQRTSSm_Int 1568
-RSQRTSSr 1569
-RSQRTSSr_Int 1570
-RSTORSSP 1571
-SAHF 1572
-SALC 1573
-SAR 1574
-SARX 1575
-SAVEPREVSSP 1576
-SBB 1577
-SCASB 1578
-SCASL 1579
-SCASQ 1580
-SCASW 1581
-SEAMCALL 1582
-SEAMOPS 1583
-SEAMRET 1584
-SEG_ALLOCA 1585
-SEH_BeginEpilogue 1586
-SEH_EndEpilogue 1587
-SEH_EndPrologue 1588
-SEH_PushFrame 1589
-SEH_PushReg 1590
-SEH_SaveReg 1591
-SEH_SaveXMM 1592
-SEH_SetFrame 1593
-SEH_StackAlign 1594
-SEH_StackAlloc 1595
-SEH_UnwindV 1596
-SEH_UnwindVersion 1597
-SENDUIPI 1598
-SERIALIZE 1599
-SETB_C 1600
-SETCCm 1601
-SETCCm_EVEX 1602
-SETCCr 1603
-SETCCr_EVEX 1604
-SETSSBSY 1605
-SETZUCCm 1606
-SETZUCCr 1607
-SFENCE 1608
-SGDT 1609
-SHA 1610
-SHL 1611
-SHLD 1612
-SHLDROT 1613
-SHLX 1614
-SHR 1615
-SHRD 1616
-SHRDROT 1617
-SHRX 1618
-SHUFPDrmi 1619
-SHUFPDrri 1620
-SHUFPSrmi 1621
-SHUFPSrri 1622
-SIDT 1623
-SKINIT 1624
-SLDT 1625
-SLWPCB 1626
-SMSW 1627
-SQRTPDm 1628
-SQRTPDr 1629
-SQRTPSm 1630
-SQRTPSr 1631
-SQRTSDm 1632
-SQRTSDm_Int 1633
-SQRTSDr 1634
-SQRTSDr_Int 1635
-SQRTSSm 1636
-SQRTSSm_Int 1637
-SQRTSSr 1638
-SQRTSSr_Int 1639
-SQRT_F 1640
-SQRT_Fp 1641
-SS_PREFIX 1642
-STAC 1643
-STACKALLOC_W_PROBING 1644
-STACKMAP 1645
-STATEPOINT 1646
-STC 1647
-STD 1648
-STGI 1649
-STI 1650
-STMXCSR 1651
-STOSB 1652
-STOSL 1653
-STOSQ 1654
-STOSW 1655
-STR 1656
-STRm 1657
-STTILECFG 1658
-STTILECFG_EVEX 1659
-STUI 1660
-ST_F 1661
-ST_FP 1662
-ST_FPrr 1663
-ST_Fp 1664
-ST_FpP 1665
-ST_Frr 1666
-SUB 1667
-SUBPDrm 1668
-SUBPDrr 1669
-SUBPSrm 1670
-SUBPSrr 1671
-SUBREG_TO_REG 1672
-SUBR_F 1673
-SUBR_FI 1674
-SUBR_FPrST 1675
-SUBR_FST 1676
-SUBR_Fp 1677
-SUBR_FpI 1678
-SUBR_FrST 1679
-SUBSDrm 1680
-SUBSDrm_Int 1681
-SUBSDrr 1682
-SUBSDrr_Int 1683
-SUBSSrm 1684
-SUBSSrm_Int 1685
-SUBSSrr 1686
-SUBSSrr_Int 1687
-SUB_F 1688
-SUB_FI 1689
-SUB_FPrST 1690
-SUB_FST 1691
-SUB_Fp 1692
-SUB_FpI 1693
-SUB_FrST 1694
-SWAPGS 1695
-SYSCALL 1696
-SYSENTER 1697
-SYSEXIT 1698
-SYSRET 1699
-T 1700
-TAILJMPd 1701
-TAILJMPd_CC 1702
-TAILJMPm 1703
-TAILJMPr 1704
-TCMMIMFP 1705
-TCMMRLFP 1706
-TCRETURN_HIPE 1707
-TCRETURN_WIN 1708
-TCRETURN_WINmi 1709
-TCRETURNdi 1710
-TCRETURNdicc 1711
-TCRETURNmi 1712
-TCRETURNri 1713
-TCVTROWD 1714
-TCVTROWPS 1715
-TDCALL 1716
-TDPBF 1717
-TDPBHF 1718
-TDPBSSD 1719
-TDPBSUD 1720
-TDPBUSD 1721
-TDPBUUD 1722
-TDPFP 1723
-TDPHBF 1724
-TDPHF 1725
-TEST 1726
-TESTUI 1727
-TILELOADD 1728
-TILELOADDRS 1729
-TILELOADDRST 1730
-TILELOADDRS_EVEX 1731
-TILELOADDT 1732
-TILELOADD_EVEX 1733
-TILEMOVROWrre 1734
-TILEMOVROWrri 1735
-TILERELEASE 1736
-TILESTORED 1737
-TILESTORED_EVEX 1738
-TILEZERO 1739
-TLBSYNC 1740
-TLSCall 1741
-TLS_addr 1742
-TLS_addrX 1743
-TLS_base_addr 1744
-TLS_base_addrX 1745
-TLS_desc 1746
-TMMULTF 1747
-TPAUSE 1748
-TRAP 1749
-TST_F 1750
-TST_Fp 1751
-TZCNT 1752
-TZMSK 1753
-UBSAN_UD 1754
-UCOMISDrm 1755
-UCOMISDrm_Int 1756
-UCOMISDrr 1757
-UCOMISDrr_Int 1758
-UCOMISSrm 1759
-UCOMISSrm_Int 1760
-UCOMISSrr 1761
-UCOMISSrr_Int 1762
-UCOM_FIPr 1763
-UCOM_FIr 1764
-UCOM_FPPr 1765
-UCOM_FPr 1766
-UCOM_FpIr 1767
-UCOM_Fpr 1768
-UCOM_Fr 1769
-UD 1770
-UIRET 1771
-UMONITOR 1772
-UMWAIT 1773
-UNPCKHPDrm 1774
-UNPCKHPDrr 1775
-UNPCKHPSrm 1776
-UNPCKHPSrr 1777
-UNPCKLPDrm 1778
-UNPCKLPDrr 1779
-UNPCKLPSrm 1780
-UNPCKLPSrr 1781
-URDMSRri 1782
-URDMSRri_EVEX 1783
-URDMSRrr 1784
-URDMSRrr_EVEX 1785
-UWRMSRir 1786
-UWRMSRir_EVEX 1787
-UWRMSRrr 1788
-UWRMSRrr_EVEX 1789
-V 1790
-VAARG 1791
-VAARG_X 1792
-VADDBF 1793
-VADDPDYrm 1794
-VADDPDYrr 1795
-VADDPDZ 1796
-VADDPDZrm 1797
-VADDPDZrmb 1798
-VADDPDZrmbk 1799
-VADDPDZrmbkz 1800
-VADDPDZrmk 1801
-VADDPDZrmkz 1802
-VADDPDZrr 1803
-VADDPDZrrb 1804
-VADDPDZrrbk 1805
-VADDPDZrrbkz 1806
-VADDPDZrrk 1807
-VADDPDZrrkz 1808
-VADDPDrm 1809
-VADDPDrr 1810
-VADDPHZ 1811
-VADDPHZrm 1812
-VADDPHZrmb 1813
-VADDPHZrmbk 1814
-VADDPHZrmbkz 1815
-VADDPHZrmk 1816
-VADDPHZrmkz 1817
-VADDPHZrr 1818
-VADDPHZrrb 1819
-VADDPHZrrbk 1820
-VADDPHZrrbkz 1821
-VADDPHZrrk 1822
-VADDPHZrrkz 1823
-VADDPSYrm 1824
-VADDPSYrr 1825
-VADDPSZ 1826
-VADDPSZrm 1827
-VADDPSZrmb 1828
-VADDPSZrmbk 1829
-VADDPSZrmbkz 1830
-VADDPSZrmk 1831
-VADDPSZrmkz 1832
-VADDPSZrr 1833
-VADDPSZrrb 1834
-VADDPSZrrbk 1835
-VADDPSZrrbkz 1836
-VADDPSZrrk 1837
-VADDPSZrrkz 1838
-VADDPSrm 1839
-VADDPSrr 1840
-VADDSDZrm 1841
-VADDSDZrm_Int 1842
-VADDSDZrmk_Int 1843
-VADDSDZrmkz_Int 1844
-VADDSDZrr 1845
-VADDSDZrr_Int 1846
-VADDSDZrrb_Int 1847
-VADDSDZrrbk_Int 1848
-VADDSDZrrbkz_Int 1849
-VADDSDZrrk_Int 1850
-VADDSDZrrkz_Int 1851
-VADDSDrm 1852
-VADDSDrm_Int 1853
-VADDSDrr 1854
-VADDSDrr_Int 1855
-VADDSHZrm 1856
-VADDSHZrm_Int 1857
-VADDSHZrmk_Int 1858
-VADDSHZrmkz_Int 1859
-VADDSHZrr 1860
-VADDSHZrr_Int 1861
-VADDSHZrrb_Int 1862
-VADDSHZrrbk_Int 1863
-VADDSHZrrbkz_Int 1864
-VADDSHZrrk_Int 1865
-VADDSHZrrkz_Int 1866
-VADDSSZrm 1867
-VADDSSZrm_Int 1868
-VADDSSZrmk_Int 1869
-VADDSSZrmkz_Int 1870
-VADDSSZrr 1871
-VADDSSZrr_Int 1872
-VADDSSZrrb_Int 1873
-VADDSSZrrbk_Int 1874
-VADDSSZrrbkz_Int 1875
-VADDSSZrrk_Int 1876
-VADDSSZrrkz_Int 1877
-VADDSSrm 1878
-VADDSSrm_Int 1879
-VADDSSrr 1880
-VADDSSrr_Int 1881
-VADDSUBPDYrm 1882
-VADDSUBPDYrr 1883
-VADDSUBPDrm 1884
-VADDSUBPDrr 1885
-VADDSUBPSYrm 1886
-VADDSUBPSYrr 1887
-VADDSUBPSrm 1888
-VADDSUBPSrr 1889
-VAESDECLASTYrm 1890
-VAESDECLASTYrr 1891
-VAESDECLASTZ 1892
-VAESDECLASTZrm 1893
-VAESDECLASTZrr 1894
-VAESDECLASTrm 1895
-VAESDECLASTrr 1896
-VAESDECYrm 1897
-VAESDECYrr 1898
-VAESDECZ 1899
-VAESDECZrm 1900
-VAESDECZrr 1901
-VAESDECrm 1902
-VAESDECrr 1903
-VAESENCLASTYrm 1904
-VAESENCLASTYrr 1905
-VAESENCLASTZ 1906
-VAESENCLASTZrm 1907
-VAESENCLASTZrr 1908
-VAESENCLASTrm 1909
-VAESENCLASTrr 1910
-VAESENCYrm 1911
-VAESENCYrr 1912
-VAESENCZ 1913
-VAESENCZrm 1914
-VAESENCZrr 1915
-VAESENCrm 1916
-VAESENCrr 1917
-VAESIMCrm 1918
-VAESIMCrr 1919
-VAESKEYGENASSISTrmi 1920
-VAESKEYGENASSISTrri 1921
-VALIGNDZ 1922
-VALIGNDZrmbi 1923
-VALIGNDZrmbik 1924
-VALIGNDZrmbikz 1925
-VALIGNDZrmi 1926
-VALIGNDZrmik 1927
-VALIGNDZrmikz 1928
-VALIGNDZrri 1929
-VALIGNDZrrik 1930
-VALIGNDZrrikz 1931
-VALIGNQZ 1932
-VALIGNQZrmbi 1933
-VALIGNQZrmbik 1934
-VALIGNQZrmbikz 1935
-VALIGNQZrmi 1936
-VALIGNQZrmik 1937
-VALIGNQZrmikz 1938
-VALIGNQZrri 1939
-VALIGNQZrrik 1940
-VALIGNQZrrikz 1941
-VANDNPDYrm 1942
-VANDNPDYrr 1943
-VANDNPDZ 1944
-VANDNPDZrm 1945
-VANDNPDZrmb 1946
-VANDNPDZrmbk 1947
-VANDNPDZrmbkz 1948
-VANDNPDZrmk 1949
-VANDNPDZrmkz 1950
-VANDNPDZrr 1951
-VANDNPDZrrk 1952
-VANDNPDZrrkz 1953
-VANDNPDrm 1954
-VANDNPDrr 1955
-VANDNPSYrm 1956
-VANDNPSYrr 1957
-VANDNPSZ 1958
-VANDNPSZrm 1959
-VANDNPSZrmb 1960
-VANDNPSZrmbk 1961
-VANDNPSZrmbkz 1962
-VANDNPSZrmk 1963
-VANDNPSZrmkz 1964
-VANDNPSZrr 1965
-VANDNPSZrrk 1966
-VANDNPSZrrkz 1967
-VANDNPSrm 1968
-VANDNPSrr 1969
-VANDPDYrm 1970
-VANDPDYrr 1971
-VANDPDZ 1972
-VANDPDZrm 1973
-VANDPDZrmb 1974
-VANDPDZrmbk 1975
-VANDPDZrmbkz 1976
-VANDPDZrmk 1977
-VANDPDZrmkz 1978
-VANDPDZrr 1979
-VANDPDZrrk 1980
-VANDPDZrrkz 1981
-VANDPDrm 1982
-VANDPDrr 1983
-VANDPSYrm 1984
-VANDPSYrr 1985
-VANDPSZ 1986
-VANDPSZrm 1987
-VANDPSZrmb 1988
-VANDPSZrmbk 1989
-VANDPSZrmbkz 1990
-VANDPSZrmk 1991
-VANDPSZrmkz 1992
-VANDPSZrr 1993
-VANDPSZrrk 1994
-VANDPSZrrkz 1995
-VANDPSrm 1996
-VANDPSrr 1997
-VASTART_SAVE_XMM_REGS 1998
-VBCSTNEBF 1999
-VBCSTNESH 2000
-VBLENDMPDZ 2001
-VBLENDMPDZrm 2002
-VBLENDMPDZrmb 2003
-VBLENDMPDZrmbk 2004
-VBLENDMPDZrmbkz 2005
-VBLENDMPDZrmk 2006
-VBLENDMPDZrmkz 2007
-VBLENDMPDZrr 2008
-VBLENDMPDZrrk 2009
-VBLENDMPDZrrkz 2010
-VBLENDMPSZ 2011
-VBLENDMPSZrm 2012
-VBLENDMPSZrmb 2013
-VBLENDMPSZrmbk 2014
-VBLENDMPSZrmbkz 2015
-VBLENDMPSZrmk 2016
-VBLENDMPSZrmkz 2017
-VBLENDMPSZrr 2018
-VBLENDMPSZrrk 2019
-VBLENDMPSZrrkz 2020
-VBLENDPDYrmi 2021
-VBLENDPDYrri 2022
-VBLENDPDrmi 2023
-VBLENDPDrri 2024
-VBLENDPSYrmi 2025
-VBLENDPSYrri 2026
-VBLENDPSrmi 2027
-VBLENDPSrri 2028
-VBLENDVPDYrmr 2029
-VBLENDVPDYrrr 2030
-VBLENDVPDrmr 2031
-VBLENDVPDrrr 2032
-VBLENDVPSYrmr 2033
-VBLENDVPSYrrr 2034
-VBLENDVPSrmr 2035
-VBLENDVPSrrr 2036
-VBROADCASTF 2037
-VBROADCASTI 2038
-VBROADCASTSDYrm 2039
-VBROADCASTSDYrr 2040
-VBROADCASTSDZ 2041
-VBROADCASTSDZrm 2042
-VBROADCASTSDZrmk 2043
-VBROADCASTSDZrmkz 2044
-VBROADCASTSDZrr 2045
-VBROADCASTSDZrrk 2046
-VBROADCASTSDZrrkz 2047
-VBROADCASTSSYrm 2048
-VBROADCASTSSYrr 2049
-VBROADCASTSSZ 2050
-VBROADCASTSSZrm 2051
-VBROADCASTSSZrmk 2052
-VBROADCASTSSZrmkz 2053
-VBROADCASTSSZrr 2054
-VBROADCASTSSZrrk 2055
-VBROADCASTSSZrrkz 2056
-VBROADCASTSSrm 2057
-VBROADCASTSSrr 2058
-VCMPBF 2059
-VCMPPDYrmi 2060
-VCMPPDYrri 2061
-VCMPPDZ 2062
-VCMPPDZrmbi 2063
-VCMPPDZrmbik 2064
-VCMPPDZrmi 2065
-VCMPPDZrmik 2066
-VCMPPDZrri 2067
-VCMPPDZrrib 2068
-VCMPPDZrribk 2069
-VCMPPDZrrik 2070
-VCMPPDrmi 2071
-VCMPPDrri 2072
-VCMPPHZ 2073
-VCMPPHZrmbi 2074
-VCMPPHZrmbik 2075
-VCMPPHZrmi 2076
-VCMPPHZrmik 2077
-VCMPPHZrri 2078
-VCMPPHZrrib 2079
-VCMPPHZrribk 2080
-VCMPPHZrrik 2081
-VCMPPSYrmi 2082
-VCMPPSYrri 2083
-VCMPPSZ 2084
-VCMPPSZrmbi 2085
-VCMPPSZrmbik 2086
-VCMPPSZrmi 2087
-VCMPPSZrmik 2088
-VCMPPSZrri 2089
-VCMPPSZrrib 2090
-VCMPPSZrribk 2091
-VCMPPSZrrik 2092
-VCMPPSrmi 2093
-VCMPPSrri 2094
-VCMPSDZrmi 2095
-VCMPSDZrmi_Int 2096
-VCMPSDZrmik_Int 2097
-VCMPSDZrri 2098
-VCMPSDZrri_Int 2099
-VCMPSDZrrib_Int 2100
-VCMPSDZrribk_Int 2101
-VCMPSDZrrik_Int 2102
-VCMPSDrmi 2103
-VCMPSDrmi_Int 2104
-VCMPSDrri 2105
-VCMPSDrri_Int 2106
-VCMPSHZrmi 2107
-VCMPSHZrmi_Int 2108
-VCMPSHZrmik_Int 2109
-VCMPSHZrri 2110
-VCMPSHZrri_Int 2111
-VCMPSHZrrib_Int 2112
-VCMPSHZrribk_Int 2113
-VCMPSHZrrik_Int 2114
-VCMPSSZrmi 2115
-VCMPSSZrmi_Int 2116
-VCMPSSZrmik_Int 2117
-VCMPSSZrri 2118
-VCMPSSZrri_Int 2119
-VCMPSSZrrib_Int 2120
-VCMPSSZrribk_Int 2121
-VCMPSSZrrik_Int 2122
-VCMPSSrmi 2123
-VCMPSSrmi_Int 2124
-VCMPSSrri 2125
-VCMPSSrri_Int 2126
-VCOMISBF 2127
-VCOMISDZrm 2128
-VCOMISDZrm_Int 2129
-VCOMISDZrr 2130
-VCOMISDZrr_Int 2131
-VCOMISDZrrb 2132
-VCOMISDrm 2133
-VCOMISDrm_Int 2134
-VCOMISDrr 2135
-VCOMISDrr_Int 2136
-VCOMISHZrm 2137
-VCOMISHZrm_Int 2138
-VCOMISHZrr 2139
-VCOMISHZrr_Int 2140
-VCOMISHZrrb 2141
-VCOMISSZrm 2142
-VCOMISSZrm_Int 2143
-VCOMISSZrr 2144
-VCOMISSZrr_Int 2145
-VCOMISSZrrb 2146
-VCOMISSrm 2147
-VCOMISSrm_Int 2148
-VCOMISSrr 2149
-VCOMISSrr_Int 2150
-VCOMPRESSPDZ 2151
-VCOMPRESSPDZmr 2152
-VCOMPRESSPDZmrk 2153
-VCOMPRESSPDZrr 2154
-VCOMPRESSPDZrrk 2155
-VCOMPRESSPDZrrkz 2156
-VCOMPRESSPSZ 2157
-VCOMPRESSPSZmr 2158
-VCOMPRESSPSZmrk 2159
-VCOMPRESSPSZrr 2160
-VCOMPRESSPSZrrk 2161
-VCOMPRESSPSZrrkz 2162
-VCOMXSDZrm_Int 2163
-VCOMXSDZrr_Int 2164
-VCOMXSDZrrb_Int 2165
-VCOMXSHZrm_Int 2166
-VCOMXSHZrr_Int 2167
-VCOMXSHZrrb_Int 2168
-VCOMXSSZrm_Int 2169
-VCOMXSSZrr_Int 2170
-VCOMXSSZrrb_Int 2171
-VCVT 2172
-VCVTBF 2173
-VCVTBIASPH 2174
-VCVTDQ 2175
-VCVTHF 2176
-VCVTNE 2177
-VCVTNEEBF 2178
-VCVTNEEPH 2179
-VCVTNEOBF 2180
-VCVTNEOPH 2181
-VCVTNEPS 2182
-VCVTPD 2183
-VCVTPH 2184
-VCVTPS 2185
-VCVTQQ 2186
-VCVTSD 2187
-VCVTSH 2188
-VCVTSI 2189
-VCVTSS 2190
-VCVTTBF 2191
-VCVTTPD 2192
-VCVTTPH 2193
-VCVTTPS 2194
-VCVTTSD 2195
-VCVTTSH 2196
-VCVTTSS 2197
-VCVTUDQ 2198
-VCVTUQQ 2199
-VCVTUSI 2200
-VCVTUW 2201
-VCVTW 2202
-VDBPSADBWZ 2203
-VDBPSADBWZrmi 2204
-VDBPSADBWZrmik 2205
-VDBPSADBWZrmikz 2206
-VDBPSADBWZrri 2207
-VDBPSADBWZrrik 2208
-VDBPSADBWZrrikz 2209
-VDIVBF 2210
-VDIVPDYrm 2211
-VDIVPDYrr 2212
-VDIVPDZ 2213
-VDIVPDZrm 2214
-VDIVPDZrmb 2215
-VDIVPDZrmbk 2216
-VDIVPDZrmbkz 2217
-VDIVPDZrmk 2218
-VDIVPDZrmkz 2219
-VDIVPDZrr 2220
-VDIVPDZrrb 2221
-VDIVPDZrrbk 2222
-VDIVPDZrrbkz 2223
-VDIVPDZrrk 2224
-VDIVPDZrrkz 2225
-VDIVPDrm 2226
-VDIVPDrr 2227
-VDIVPHZ 2228
-VDIVPHZrm 2229
-VDIVPHZrmb 2230
-VDIVPHZrmbk 2231
-VDIVPHZrmbkz 2232
-VDIVPHZrmk 2233
-VDIVPHZrmkz 2234
-VDIVPHZrr 2235
-VDIVPHZrrb 2236
-VDIVPHZrrbk 2237
-VDIVPHZrrbkz 2238
-VDIVPHZrrk 2239
-VDIVPHZrrkz 2240
-VDIVPSYrm 2241
-VDIVPSYrr 2242
-VDIVPSZ 2243
-VDIVPSZrm 2244
-VDIVPSZrmb 2245
-VDIVPSZrmbk 2246
-VDIVPSZrmbkz 2247
-VDIVPSZrmk 2248
-VDIVPSZrmkz 2249
-VDIVPSZrr 2250
-VDIVPSZrrb 2251
-VDIVPSZrrbk 2252
-VDIVPSZrrbkz 2253
-VDIVPSZrrk 2254
-VDIVPSZrrkz 2255
-VDIVPSrm 2256
-VDIVPSrr 2257
-VDIVSDZrm 2258
-VDIVSDZrm_Int 2259
-VDIVSDZrmk_Int 2260
-VDIVSDZrmkz_Int 2261
-VDIVSDZrr 2262
-VDIVSDZrr_Int 2263
-VDIVSDZrrb_Int 2264
-VDIVSDZrrbk_Int 2265
-VDIVSDZrrbkz_Int 2266
-VDIVSDZrrk_Int 2267
-VDIVSDZrrkz_Int 2268
-VDIVSDrm 2269
-VDIVSDrm_Int 2270
-VDIVSDrr 2271
-VDIVSDrr_Int 2272
-VDIVSHZrm 2273
-VDIVSHZrm_Int 2274
-VDIVSHZrmk_Int 2275
-VDIVSHZrmkz_Int 2276
-VDIVSHZrr 2277
-VDIVSHZrr_Int 2278
-VDIVSHZrrb_Int 2279
-VDIVSHZrrbk_Int 2280
-VDIVSHZrrbkz_Int 2281
-VDIVSHZrrk_Int 2282
-VDIVSHZrrkz_Int 2283
-VDIVSSZrm 2284
-VDIVSSZrm_Int 2285
-VDIVSSZrmk_Int 2286
-VDIVSSZrmkz_Int 2287
-VDIVSSZrr 2288
-VDIVSSZrr_Int 2289
-VDIVSSZrrb_Int 2290
-VDIVSSZrrbk_Int 2291
-VDIVSSZrrbkz_Int 2292
-VDIVSSZrrk_Int 2293
-VDIVSSZrrkz_Int 2294
-VDIVSSrm 2295
-VDIVSSrm_Int 2296
-VDIVSSrr 2297
-VDIVSSrr_Int 2298
-VDPBF 2299
-VDPPDrmi 2300
-VDPPDrri 2301
-VDPPHPSZ 2302
-VDPPHPSZm 2303
-VDPPHPSZmb 2304
-VDPPHPSZmbk 2305
-VDPPHPSZmbkz 2306
-VDPPHPSZmk 2307
-VDPPHPSZmkz 2308
-VDPPHPSZr 2309
-VDPPHPSZrk 2310
-VDPPHPSZrkz 2311
-VDPPSYrmi 2312
-VDPPSYrri 2313
-VDPPSrmi 2314
-VDPPSrri 2315
-VERRm 2316
-VERRr 2317
-VERWm 2318
-VERWr 2319
-VEXP 2320
-VEXPANDPDZ 2321
-VEXPANDPDZrm 2322
-VEXPANDPDZrmk 2323
-VEXPANDPDZrmkz 2324
-VEXPANDPDZrr 2325
-VEXPANDPDZrrk 2326
-VEXPANDPDZrrkz 2327
-VEXPANDPSZ 2328
-VEXPANDPSZrm 2329
-VEXPANDPSZrmk 2330
-VEXPANDPSZrmkz 2331
-VEXPANDPSZrr 2332
-VEXPANDPSZrrk 2333
-VEXPANDPSZrrkz 2334
-VEXTRACTF 2335
-VEXTRACTI 2336
-VEXTRACTPSZmri 2337
-VEXTRACTPSZrri 2338
-VEXTRACTPSmri 2339
-VEXTRACTPSrri 2340
-VFCMADDCPHZ 2341
-VFCMADDCPHZm 2342
-VFCMADDCPHZmb 2343
-VFCMADDCPHZmbk 2344
-VFCMADDCPHZmbkz 2345
-VFCMADDCPHZmk 2346
-VFCMADDCPHZmkz 2347
-VFCMADDCPHZr 2348
-VFCMADDCPHZrb 2349
-VFCMADDCPHZrbk 2350
-VFCMADDCPHZrbkz 2351
-VFCMADDCPHZrk 2352
-VFCMADDCPHZrkz 2353
-VFCMADDCSHZm 2354
-VFCMADDCSHZmk 2355
-VFCMADDCSHZmkz 2356
-VFCMADDCSHZr 2357
-VFCMADDCSHZrb 2358
-VFCMADDCSHZrbk 2359
-VFCMADDCSHZrbkz 2360
-VFCMADDCSHZrk 2361
-VFCMADDCSHZrkz 2362
-VFCMULCPHZ 2363
-VFCMULCPHZrm 2364
-VFCMULCPHZrmb 2365
-VFCMULCPHZrmbk 2366
-VFCMULCPHZrmbkz 2367
-VFCMULCPHZrmk 2368
-VFCMULCPHZrmkz 2369
-VFCMULCPHZrr 2370
-VFCMULCPHZrrb 2371
-VFCMULCPHZrrbk 2372
-VFCMULCPHZrrbkz 2373
-VFCMULCPHZrrk 2374
-VFCMULCPHZrrkz 2375
-VFCMULCSHZrm 2376
-VFCMULCSHZrmk 2377
-VFCMULCSHZrmkz 2378
-VFCMULCSHZrr 2379
-VFCMULCSHZrrb 2380
-VFCMULCSHZrrbk 2381
-VFCMULCSHZrrbkz 2382
-VFCMULCSHZrrk 2383
-VFCMULCSHZrrkz 2384
-VFIXUPIMMPDZ 2385
-VFIXUPIMMPDZrmbi 2386
-VFIXUPIMMPDZrmbik 2387
-VFIXUPIMMPDZrmbikz 2388
-VFIXUPIMMPDZrmi 2389
-VFIXUPIMMPDZrmik 2390
-VFIXUPIMMPDZrmikz 2391
-VFIXUPIMMPDZrri 2392
-VFIXUPIMMPDZrrib 2393
-VFIXUPIMMPDZrribk 2394
-VFIXUPIMMPDZrribkz 2395
-VFIXUPIMMPDZrrik 2396
-VFIXUPIMMPDZrrikz 2397
-VFIXUPIMMPSZ 2398
-VFIXUPIMMPSZrmbi 2399
-VFIXUPIMMPSZrmbik 2400
-VFIXUPIMMPSZrmbikz 2401
-VFIXUPIMMPSZrmi 2402
-VFIXUPIMMPSZrmik 2403
-VFIXUPIMMPSZrmikz 2404
-VFIXUPIMMPSZrri 2405
-VFIXUPIMMPSZrrib 2406
-VFIXUPIMMPSZrribk 2407
-VFIXUPIMMPSZrribkz 2408
-VFIXUPIMMPSZrrik 2409
-VFIXUPIMMPSZrrikz 2410
-VFIXUPIMMSDZrmi 2411
-VFIXUPIMMSDZrmik 2412
-VFIXUPIMMSDZrmikz 2413
-VFIXUPIMMSDZrri 2414
-VFIXUPIMMSDZrrib 2415
-VFIXUPIMMSDZrribk 2416
-VFIXUPIMMSDZrribkz 2417
-VFIXUPIMMSDZrrik 2418
-VFIXUPIMMSDZrrikz 2419
-VFIXUPIMMSSZrmi 2420
-VFIXUPIMMSSZrmik 2421
-VFIXUPIMMSSZrmikz 2422
-VFIXUPIMMSSZrri 2423
-VFIXUPIMMSSZrrib 2424
-VFIXUPIMMSSZrribk 2425
-VFIXUPIMMSSZrribkz 2426
-VFIXUPIMMSSZrrik 2427
-VFIXUPIMMSSZrrikz 2428
-VFMADD 2429
-VFMADDCPHZ 2430
-VFMADDCPHZm 2431
-VFMADDCPHZmb 2432
-VFMADDCPHZmbk 2433
-VFMADDCPHZmbkz 2434
-VFMADDCPHZmk 2435
-VFMADDCPHZmkz 2436
-VFMADDCPHZr 2437
-VFMADDCPHZrb 2438
-VFMADDCPHZrbk 2439
-VFMADDCPHZrbkz 2440
-VFMADDCPHZrk 2441
-VFMADDCPHZrkz 2442
-VFMADDCSHZm 2443
-VFMADDCSHZmk 2444
-VFMADDCSHZmkz 2445
-VFMADDCSHZr 2446
-VFMADDCSHZrb 2447
-VFMADDCSHZrbk 2448
-VFMADDCSHZrbkz 2449
-VFMADDCSHZrk 2450
-VFMADDCSHZrkz 2451
-VFMADDPD 2452
-VFMADDPS 2453
-VFMADDSD 2454
-VFMADDSS 2455
-VFMADDSUB 2456
-VFMADDSUBPD 2457
-VFMADDSUBPS 2458
-VFMSUB 2459
-VFMSUBADD 2460
-VFMSUBADDPD 2461
-VFMSUBADDPS 2462
-VFMSUBPD 2463
-VFMSUBPS 2464
-VFMSUBSD 2465
-VFMSUBSS 2466
-VFMULCPHZ 2467
-VFMULCPHZrm 2468
-VFMULCPHZrmb 2469
-VFMULCPHZrmbk 2470
-VFMULCPHZrmbkz 2471
-VFMULCPHZrmk 2472
-VFMULCPHZrmkz 2473
-VFMULCPHZrr 2474
-VFMULCPHZrrb 2475
-VFMULCPHZrrbk 2476
-VFMULCPHZrrbkz 2477
-VFMULCPHZrrk 2478
-VFMULCPHZrrkz 2479
-VFMULCSHZrm 2480
-VFMULCSHZrmk 2481
-VFMULCSHZrmkz 2482
-VFMULCSHZrr 2483
-VFMULCSHZrrb 2484
-VFMULCSHZrrbk 2485
-VFMULCSHZrrbkz 2486
-VFMULCSHZrrk 2487
-VFMULCSHZrrkz 2488
-VFNMADD 2489
-VFNMADDPD 2490
-VFNMADDPS 2491
-VFNMADDSD 2492
-VFNMADDSS 2493
-VFNMSUB 2494
-VFNMSUBPD 2495
-VFNMSUBPS 2496
-VFNMSUBSD 2497
-VFNMSUBSS 2498
-VFPCLASSBF 2499
-VFPCLASSPDZ 2500
-VFPCLASSPDZmbi 2501
-VFPCLASSPDZmbik 2502
-VFPCLASSPDZmi 2503
-VFPCLASSPDZmik 2504
-VFPCLASSPDZri 2505
-VFPCLASSPDZrik 2506
-VFPCLASSPHZ 2507
-VFPCLASSPHZmbi 2508
-VFPCLASSPHZmbik 2509
-VFPCLASSPHZmi 2510
-VFPCLASSPHZmik 2511
-VFPCLASSPHZri 2512
-VFPCLASSPHZrik 2513
-VFPCLASSPSZ 2514
-VFPCLASSPSZmbi 2515
-VFPCLASSPSZmbik 2516
-VFPCLASSPSZmi 2517
-VFPCLASSPSZmik 2518
-VFPCLASSPSZri 2519
-VFPCLASSPSZrik 2520
-VFPCLASSSDZmi 2521
-VFPCLASSSDZmik 2522
-VFPCLASSSDZri 2523
-VFPCLASSSDZrik 2524
-VFPCLASSSHZmi 2525
-VFPCLASSSHZmik 2526
-VFPCLASSSHZri 2527
-VFPCLASSSHZrik 2528
-VFPCLASSSSZmi 2529
-VFPCLASSSSZmik 2530
-VFPCLASSSSZri 2531
-VFPCLASSSSZrik 2532
-VFRCZPDYrm 2533
-VFRCZPDYrr 2534
-VFRCZPDrm 2535
-VFRCZPDrr 2536
-VFRCZPSYrm 2537
-VFRCZPSYrr 2538
-VFRCZPSrm 2539
-VFRCZPSrr 2540
-VFRCZSDrm 2541
-VFRCZSDrr 2542
-VFRCZSSrm 2543
-VFRCZSSrr 2544
-VGATHERDPDYrm 2545
-VGATHERDPDZ 2546
-VGATHERDPDZrm 2547
-VGATHERDPDrm 2548
-VGATHERDPSYrm 2549
-VGATHERDPSZ 2550
-VGATHERDPSZrm 2551
-VGATHERDPSrm 2552
-VGATHERPF 2553
-VGATHERQPDYrm 2554
-VGATHERQPDZ 2555
-VGATHERQPDZrm 2556
-VGATHERQPDrm 2557
-VGATHERQPSYrm 2558
-VGATHERQPSZ 2559
-VGATHERQPSZrm 2560
-VGATHERQPSrm 2561
-VGETEXPBF 2562
-VGETEXPPDZ 2563
-VGETEXPPDZm 2564
-VGETEXPPDZmb 2565
-VGETEXPPDZmbk 2566
-VGETEXPPDZmbkz 2567
-VGETEXPPDZmk 2568
-VGETEXPPDZmkz 2569
-VGETEXPPDZr 2570
-VGETEXPPDZrb 2571
-VGETEXPPDZrbk 2572
-VGETEXPPDZrbkz 2573
-VGETEXPPDZrk 2574
-VGETEXPPDZrkz 2575
-VGETEXPPHZ 2576
-VGETEXPPHZm 2577
-VGETEXPPHZmb 2578
-VGETEXPPHZmbk 2579
-VGETEXPPHZmbkz 2580
-VGETEXPPHZmk 2581
-VGETEXPPHZmkz 2582
-VGETEXPPHZr 2583
-VGETEXPPHZrb 2584
-VGETEXPPHZrbk 2585
-VGETEXPPHZrbkz 2586
-VGETEXPPHZrk 2587
-VGETEXPPHZrkz 2588
-VGETEXPPSZ 2589
-VGETEXPPSZm 2590
-VGETEXPPSZmb 2591
-VGETEXPPSZmbk 2592
-VGETEXPPSZmbkz 2593
-VGETEXPPSZmk 2594
-VGETEXPPSZmkz 2595
-VGETEXPPSZr 2596
-VGETEXPPSZrb 2597
-VGETEXPPSZrbk 2598
-VGETEXPPSZrbkz 2599
-VGETEXPPSZrk 2600
-VGETEXPPSZrkz 2601
-VGETEXPSDZm 2602
-VGETEXPSDZmk 2603
-VGETEXPSDZmkz 2604
-VGETEXPSDZr 2605
-VGETEXPSDZrb 2606
-VGETEXPSDZrbk 2607
-VGETEXPSDZrbkz 2608
-VGETEXPSDZrk 2609
-VGETEXPSDZrkz 2610
-VGETEXPSHZm 2611
-VGETEXPSHZmk 2612
-VGETEXPSHZmkz 2613
-VGETEXPSHZr 2614
-VGETEXPSHZrb 2615
-VGETEXPSHZrbk 2616
-VGETEXPSHZrbkz 2617
-VGETEXPSHZrk 2618
-VGETEXPSHZrkz 2619
-VGETEXPSSZm 2620
-VGETEXPSSZmk 2621
-VGETEXPSSZmkz 2622
-VGETEXPSSZr 2623
-VGETEXPSSZrb 2624
-VGETEXPSSZrbk 2625
-VGETEXPSSZrbkz 2626
-VGETEXPSSZrk 2627
-VGETEXPSSZrkz 2628
-VGETMANTBF 2629
-VGETMANTPDZ 2630
-VGETMANTPDZrmbi 2631
-VGETMANTPDZrmbik 2632
-VGETMANTPDZrmbikz 2633
-VGETMANTPDZrmi 2634
-VGETMANTPDZrmik 2635
-VGETMANTPDZrmikz 2636
-VGETMANTPDZrri 2637
-VGETMANTPDZrrib 2638
-VGETMANTPDZrribk 2639
-VGETMANTPDZrribkz 2640
-VGETMANTPDZrrik 2641
-VGETMANTPDZrrikz 2642
-VGETMANTPHZ 2643
-VGETMANTPHZrmbi 2644
-VGETMANTPHZrmbik 2645
-VGETMANTPHZrmbikz 2646
-VGETMANTPHZrmi 2647
-VGETMANTPHZrmik 2648
-VGETMANTPHZrmikz 2649
-VGETMANTPHZrri 2650
-VGETMANTPHZrrib 2651
-VGETMANTPHZrribk 2652
-VGETMANTPHZrribkz 2653
-VGETMANTPHZrrik 2654
-VGETMANTPHZrrikz 2655
-VGETMANTPSZ 2656
-VGETMANTPSZrmbi 2657
-VGETMANTPSZrmbik 2658
-VGETMANTPSZrmbikz 2659
-VGETMANTPSZrmi 2660
-VGETMANTPSZrmik 2661
-VGETMANTPSZrmikz 2662
-VGETMANTPSZrri 2663
-VGETMANTPSZrrib 2664
-VGETMANTPSZrribk 2665
-VGETMANTPSZrribkz 2666
-VGETMANTPSZrrik 2667
-VGETMANTPSZrrikz 2668
-VGETMANTSDZrmi 2669
-VGETMANTSDZrmik 2670
-VGETMANTSDZrmikz 2671
-VGETMANTSDZrri 2672
-VGETMANTSDZrrib 2673
-VGETMANTSDZrribk 2674
-VGETMANTSDZrribkz 2675
-VGETMANTSDZrrik 2676
-VGETMANTSDZrrikz 2677
-VGETMANTSHZrmi 2678
-VGETMANTSHZrmik 2679
-VGETMANTSHZrmikz 2680
-VGETMANTSHZrri 2681
-VGETMANTSHZrrib 2682
-VGETMANTSHZrribk 2683
-VGETMANTSHZrribkz 2684
-VGETMANTSHZrrik 2685
-VGETMANTSHZrrikz 2686
-VGETMANTSSZrmi 2687
-VGETMANTSSZrmik 2688
-VGETMANTSSZrmikz 2689
-VGETMANTSSZrri 2690
-VGETMANTSSZrrib 2691
-VGETMANTSSZrribk 2692
-VGETMANTSSZrribkz 2693
-VGETMANTSSZrrik 2694
-VGETMANTSSZrrikz 2695
-VGF 2696
-VHADDPDYrm 2697
-VHADDPDYrr 2698
-VHADDPDrm 2699
-VHADDPDrr 2700
-VHADDPSYrm 2701
-VHADDPSYrr 2702
-VHADDPSrm 2703
-VHADDPSrr 2704
-VHSUBPDYrm 2705
-VHSUBPDYrr 2706
-VHSUBPDrm 2707
-VHSUBPDrr 2708
-VHSUBPSYrm 2709
-VHSUBPSYrr 2710
-VHSUBPSrm 2711
-VHSUBPSrr 2712
-VINSERTF 2713
-VINSERTI 2714
-VINSERTPSZrmi 2715
-VINSERTPSZrri 2716
-VINSERTPSrmi 2717
-VINSERTPSrri 2718
-VLDDQUYrm 2719
-VLDDQUrm 2720
-VLDMXCSR 2721
-VMASKMOVDQU 2722
-VMASKMOVPDYmr 2723
-VMASKMOVPDYrm 2724
-VMASKMOVPDmr 2725
-VMASKMOVPDrm 2726
-VMASKMOVPSYmr 2727
-VMASKMOVPSYrm 2728
-VMASKMOVPSmr 2729
-VMASKMOVPSrm 2730
-VMAXBF 2731
-VMAXCPDYrm 2732
-VMAXCPDYrr 2733
-VMAXCPDZ 2734
-VMAXCPDZrm 2735
-VMAXCPDZrmb 2736
-VMAXCPDZrmbk 2737
-VMAXCPDZrmbkz 2738
-VMAXCPDZrmk 2739
-VMAXCPDZrmkz 2740
-VMAXCPDZrr 2741
-VMAXCPDZrrk 2742
-VMAXCPDZrrkz 2743
-VMAXCPDrm 2744
-VMAXCPDrr 2745
-VMAXCPHZ 2746
-VMAXCPHZrm 2747
-VMAXCPHZrmb 2748
-VMAXCPHZrmbk 2749
-VMAXCPHZrmbkz 2750
-VMAXCPHZrmk 2751
-VMAXCPHZrmkz 2752
-VMAXCPHZrr 2753
-VMAXCPHZrrk 2754
-VMAXCPHZrrkz 2755
-VMAXCPSYrm 2756
-VMAXCPSYrr 2757
-VMAXCPSZ 2758
-VMAXCPSZrm 2759
-VMAXCPSZrmb 2760
-VMAXCPSZrmbk 2761
-VMAXCPSZrmbkz 2762
-VMAXCPSZrmk 2763
-VMAXCPSZrmkz 2764
-VMAXCPSZrr 2765
-VMAXCPSZrrk 2766
-VMAXCPSZrrkz 2767
-VMAXCPSrm 2768
-VMAXCPSrr 2769
-VMAXCSDZrm 2770
-VMAXCSDZrr 2771
-VMAXCSDrm 2772
-VMAXCSDrr 2773
-VMAXCSHZrm 2774
-VMAXCSHZrr 2775
-VMAXCSSZrm 2776
-VMAXCSSZrr 2777
-VMAXCSSrm 2778
-VMAXCSSrr 2779
-VMAXPDYrm 2780
-VMAXPDYrr 2781
-VMAXPDZ 2782
-VMAXPDZrm 2783
-VMAXPDZrmb 2784
-VMAXPDZrmbk 2785
-VMAXPDZrmbkz 2786
-VMAXPDZrmk 2787
-VMAXPDZrmkz 2788
-VMAXPDZrr 2789
-VMAXPDZrrb 2790
-VMAXPDZrrbk 2791
-VMAXPDZrrbkz 2792
-VMAXPDZrrk 2793
-VMAXPDZrrkz 2794
-VMAXPDrm 2795
-VMAXPDrr 2796
-VMAXPHZ 2797
-VMAXPHZrm 2798
-VMAXPHZrmb 2799
-VMAXPHZrmbk 2800
-VMAXPHZrmbkz 2801
-VMAXPHZrmk 2802
-VMAXPHZrmkz 2803
-VMAXPHZrr 2804
-VMAXPHZrrb 2805
-VMAXPHZrrbk 2806
-VMAXPHZrrbkz 2807
-VMAXPHZrrk 2808
-VMAXPHZrrkz 2809
-VMAXPSYrm 2810
-VMAXPSYrr 2811
-VMAXPSZ 2812
-VMAXPSZrm 2813
-VMAXPSZrmb 2814
-VMAXPSZrmbk 2815
-VMAXPSZrmbkz 2816
-VMAXPSZrmk 2817
-VMAXPSZrmkz 2818
-VMAXPSZrr 2819
-VMAXPSZrrb 2820
-VMAXPSZrrbk 2821
-VMAXPSZrrbkz 2822
-VMAXPSZrrk 2823
-VMAXPSZrrkz 2824
-VMAXPSrm 2825
-VMAXPSrr 2826
-VMAXSDZrm 2827
-VMAXSDZrm_Int 2828
-VMAXSDZrmk_Int 2829
-VMAXSDZrmkz_Int 2830
-VMAXSDZrr 2831
-VMAXSDZrr_Int 2832
-VMAXSDZrrb_Int 2833
-VMAXSDZrrbk_Int 2834
-VMAXSDZrrbkz_Int 2835
-VMAXSDZrrk_Int 2836
-VMAXSDZrrkz_Int 2837
-VMAXSDrm 2838
-VMAXSDrm_Int 2839
-VMAXSDrr 2840
-VMAXSDrr_Int 2841
-VMAXSHZrm 2842
-VMAXSHZrm_Int 2843
-VMAXSHZrmk_Int 2844
-VMAXSHZrmkz_Int 2845
-VMAXSHZrr 2846
-VMAXSHZrr_Int 2847
-VMAXSHZrrb_Int 2848
-VMAXSHZrrbk_Int 2849
-VMAXSHZrrbkz_Int 2850
-VMAXSHZrrk_Int 2851
-VMAXSHZrrkz_Int 2852
-VMAXSSZrm 2853
-VMAXSSZrm_Int 2854
-VMAXSSZrmk_Int 2855
-VMAXSSZrmkz_Int 2856
-VMAXSSZrr 2857
-VMAXSSZrr_Int 2858
-VMAXSSZrrb_Int 2859
-VMAXSSZrrbk_Int 2860
-VMAXSSZrrbkz_Int 2861
-VMAXSSZrrk_Int 2862
-VMAXSSZrrkz_Int 2863
-VMAXSSrm 2864
-VMAXSSrm_Int 2865
-VMAXSSrr 2866
-VMAXSSrr_Int 2867
-VMCALL 2868
-VMCLEARm 2869
-VMFUNC 2870
-VMINBF 2871
-VMINCPDYrm 2872
-VMINCPDYrr 2873
-VMINCPDZ 2874
-VMINCPDZrm 2875
-VMINCPDZrmb 2876
-VMINCPDZrmbk 2877
-VMINCPDZrmbkz 2878
-VMINCPDZrmk 2879
-VMINCPDZrmkz 2880
-VMINCPDZrr 2881
-VMINCPDZrrk 2882
-VMINCPDZrrkz 2883
-VMINCPDrm 2884
-VMINCPDrr 2885
-VMINCPHZ 2886
-VMINCPHZrm 2887
-VMINCPHZrmb 2888
-VMINCPHZrmbk 2889
-VMINCPHZrmbkz 2890
-VMINCPHZrmk 2891
-VMINCPHZrmkz 2892
-VMINCPHZrr 2893
-VMINCPHZrrk 2894
-VMINCPHZrrkz 2895
-VMINCPSYrm 2896
-VMINCPSYrr 2897
-VMINCPSZ 2898
-VMINCPSZrm 2899
-VMINCPSZrmb 2900
-VMINCPSZrmbk 2901
-VMINCPSZrmbkz 2902
-VMINCPSZrmk 2903
-VMINCPSZrmkz 2904
-VMINCPSZrr 2905
-VMINCPSZrrk 2906
-VMINCPSZrrkz 2907
-VMINCPSrm 2908
-VMINCPSrr 2909
-VMINCSDZrm 2910
-VMINCSDZrr 2911
-VMINCSDrm 2912
-VMINCSDrr 2913
-VMINCSHZrm 2914
-VMINCSHZrr 2915
-VMINCSSZrm 2916
-VMINCSSZrr 2917
-VMINCSSrm 2918
-VMINCSSrr 2919
-VMINMAXBF 2920
-VMINMAXPDZ 2921
-VMINMAXPDZrmbi 2922
-VMINMAXPDZrmbik 2923
-VMINMAXPDZrmbikz 2924
-VMINMAXPDZrmi 2925
-VMINMAXPDZrmik 2926
-VMINMAXPDZrmikz 2927
-VMINMAXPDZrri 2928
-VMINMAXPDZrrib 2929
-VMINMAXPDZrribk 2930
-VMINMAXPDZrribkz 2931
-VMINMAXPDZrrik 2932
-VMINMAXPDZrrikz 2933
-VMINMAXPHZ 2934
-VMINMAXPHZrmbi 2935
-VMINMAXPHZrmbik 2936
-VMINMAXPHZrmbikz 2937
-VMINMAXPHZrmi 2938
-VMINMAXPHZrmik 2939
-VMINMAXPHZrmikz 2940
-VMINMAXPHZrri 2941
-VMINMAXPHZrrib 2942
-VMINMAXPHZrribk 2943
-VMINMAXPHZrribkz 2944
-VMINMAXPHZrrik 2945
-VMINMAXPHZrrikz 2946
-VMINMAXPSZ 2947
-VMINMAXPSZrmbi 2948
-VMINMAXPSZrmbik 2949
-VMINMAXPSZrmbikz 2950
-VMINMAXPSZrmi 2951
-VMINMAXPSZrmik 2952
-VMINMAXPSZrmikz 2953
-VMINMAXPSZrri 2954
-VMINMAXPSZrrib 2955
-VMINMAXPSZrribk 2956
-VMINMAXPSZrribkz 2957
-VMINMAXPSZrrik 2958
-VMINMAXPSZrrikz 2959
-VMINMAXSDrmi 2960
-VMINMAXSDrmi_Int 2961
-VMINMAXSDrmik_Int 2962
-VMINMAXSDrmikz_Int 2963
-VMINMAXSDrri 2964
-VMINMAXSDrri_Int 2965
-VMINMAXSDrrib_Int 2966
-VMINMAXSDrribk_Int 2967
-VMINMAXSDrribkz_Int 2968
-VMINMAXSDrrik_Int 2969
-VMINMAXSDrrikz_Int 2970
-VMINMAXSHrmi 2971
-VMINMAXSHrmi_Int 2972
-VMINMAXSHrmik_Int 2973
-VMINMAXSHrmikz_Int 2974
-VMINMAXSHrri 2975
-VMINMAXSHrri_Int 2976
-VMINMAXSHrrib_Int 2977
-VMINMAXSHrribk_Int 2978
-VMINMAXSHrribkz_Int 2979
-VMINMAXSHrrik_Int 2980
-VMINMAXSHrrikz_Int 2981
-VMINMAXSSrmi 2982
-VMINMAXSSrmi_Int 2983
-VMINMAXSSrmik_Int 2984
-VMINMAXSSrmikz_Int 2985
-VMINMAXSSrri 2986
-VMINMAXSSrri_Int 2987
-VMINMAXSSrrib_Int 2988
-VMINMAXSSrribk_Int 2989
-VMINMAXSSrribkz_Int 2990
-VMINMAXSSrrik_Int 2991
-VMINMAXSSrrikz_Int 2992
-VMINPDYrm 2993
-VMINPDYrr 2994
-VMINPDZ 2995
-VMINPDZrm 2996
-VMINPDZrmb 2997
-VMINPDZrmbk 2998
-VMINPDZrmbkz 2999
-VMINPDZrmk 3000
-VMINPDZrmkz 3001
-VMINPDZrr 3002
-VMINPDZrrb 3003
-VMINPDZrrbk 3004
-VMINPDZrrbkz 3005
-VMINPDZrrk 3006
-VMINPDZrrkz 3007
-VMINPDrm 3008
-VMINPDrr 3009
-VMINPHZ 3010
-VMINPHZrm 3011
-VMINPHZrmb 3012
-VMINPHZrmbk 3013
-VMINPHZrmbkz 3014
-VMINPHZrmk 3015
-VMINPHZrmkz 3016
-VMINPHZrr 3017
-VMINPHZrrb 3018
-VMINPHZrrbk 3019
-VMINPHZrrbkz 3020
-VMINPHZrrk 3021
-VMINPHZrrkz 3022
-VMINPSYrm 3023
-VMINPSYrr 3024
-VMINPSZ 3025
-VMINPSZrm 3026
-VMINPSZrmb 3027
-VMINPSZrmbk 3028
-VMINPSZrmbkz 3029
-VMINPSZrmk 3030
-VMINPSZrmkz 3031
-VMINPSZrr 3032
-VMINPSZrrb 3033
-VMINPSZrrbk 3034
-VMINPSZrrbkz 3035
-VMINPSZrrk 3036
-VMINPSZrrkz 3037
-VMINPSrm 3038
-VMINPSrr 3039
-VMINSDZrm 3040
-VMINSDZrm_Int 3041
-VMINSDZrmk_Int 3042
-VMINSDZrmkz_Int 3043
-VMINSDZrr 3044
-VMINSDZrr_Int 3045
-VMINSDZrrb_Int 3046
-VMINSDZrrbk_Int 3047
-VMINSDZrrbkz_Int 3048
-VMINSDZrrk_Int 3049
-VMINSDZrrkz_Int 3050
-VMINSDrm 3051
-VMINSDrm_Int 3052
-VMINSDrr 3053
-VMINSDrr_Int 3054
-VMINSHZrm 3055
-VMINSHZrm_Int 3056
-VMINSHZrmk_Int 3057
-VMINSHZrmkz_Int 3058
-VMINSHZrr 3059
-VMINSHZrr_Int 3060
-VMINSHZrrb_Int 3061
-VMINSHZrrbk_Int 3062
-VMINSHZrrbkz_Int 3063
-VMINSHZrrk_Int 3064
-VMINSHZrrkz_Int 3065
-VMINSSZrm 3066
-VMINSSZrm_Int 3067
-VMINSSZrmk_Int 3068
-VMINSSZrmkz_Int 3069
-VMINSSZrr 3070
-VMINSSZrr_Int 3071
-VMINSSZrrb_Int 3072
-VMINSSZrrbk_Int 3073
-VMINSSZrrbkz_Int 3074
-VMINSSZrrk_Int 3075
-VMINSSZrrkz_Int 3076
-VMINSSrm 3077
-VMINSSrm_Int 3078
-VMINSSrr 3079
-VMINSSrr_Int 3080
-VMLAUNCH 3081
-VMLOAD 3082
-VMMCALL 3083
-VMOV 3084
-VMOVAPDYmr 3085
-VMOVAPDYrm 3086
-VMOVAPDYrr 3087
-VMOVAPDYrr_REV 3088
-VMOVAPDZ 3089
-VMOVAPDZmr 3090
-VMOVAPDZmrk 3091
-VMOVAPDZrm 3092
-VMOVAPDZrmk 3093
-VMOVAPDZrmkz 3094
-VMOVAPDZrr 3095
-VMOVAPDZrr_REV 3096
-VMOVAPDZrrk 3097
-VMOVAPDZrrk_REV 3098
-VMOVAPDZrrkz 3099
-VMOVAPDZrrkz_REV 3100
-VMOVAPDmr 3101
-VMOVAPDrm 3102
-VMOVAPDrr 3103
-VMOVAPDrr_REV 3104
-VMOVAPSYmr 3105
-VMOVAPSYrm 3106
-VMOVAPSYrr 3107
-VMOVAPSYrr_REV 3108
-VMOVAPSZ 3109
-VMOVAPSZmr 3110
-VMOVAPSZmrk 3111
-VMOVAPSZrm 3112
-VMOVAPSZrmk 3113
-VMOVAPSZrmkz 3114
-VMOVAPSZrr 3115
-VMOVAPSZrr_REV 3116
-VMOVAPSZrrk 3117
-VMOVAPSZrrk_REV 3118
-VMOVAPSZrrkz 3119
-VMOVAPSZrrkz_REV 3120
-VMOVAPSmr 3121
-VMOVAPSrm 3122
-VMOVAPSrr 3123
-VMOVAPSrr_REV 3124
-VMOVDDUPYrm 3125
-VMOVDDUPYrr 3126
-VMOVDDUPZ 3127
-VMOVDDUPZrm 3128
-VMOVDDUPZrmk 3129
-VMOVDDUPZrmkz 3130
-VMOVDDUPZrr 3131
-VMOVDDUPZrrk 3132
-VMOVDDUPZrrkz 3133
-VMOVDDUPrm 3134
-VMOVDDUPrr 3135
-VMOVDI 3136
-VMOVDQA 3137
-VMOVDQAYmr 3138
-VMOVDQAYrm 3139
-VMOVDQAYrr 3140
-VMOVDQAYrr_REV 3141
-VMOVDQAmr 3142
-VMOVDQArm 3143
-VMOVDQArr 3144
-VMOVDQArr_REV 3145
-VMOVDQU 3146
-VMOVDQUYmr 3147
-VMOVDQUYrm 3148
-VMOVDQUYrr 3149
-VMOVDQUYrr_REV 3150
-VMOVDQUmr 3151
-VMOVDQUrm 3152
-VMOVDQUrr 3153
-VMOVDQUrr_REV 3154
-VMOVHLPSZrr 3155
-VMOVHLPSrr 3156
-VMOVHPDZ 3157
-VMOVHPDmr 3158
-VMOVHPDrm 3159
-VMOVHPSZ 3160
-VMOVHPSmr 3161
-VMOVHPSrm 3162
-VMOVLHPSZrr 3163
-VMOVLHPSrr 3164
-VMOVLPDZ 3165
-VMOVLPDmr 3166
-VMOVLPDrm 3167
-VMOVLPSZ 3168
-VMOVLPSmr 3169
-VMOVLPSrm 3170
-VMOVMSKPDYrr 3171
-VMOVMSKPDrr 3172
-VMOVMSKPSYrr 3173
-VMOVMSKPSrr 3174
-VMOVNTDQAYrm 3175
-VMOVNTDQAZ 3176
-VMOVNTDQAZrm 3177
-VMOVNTDQArm 3178
-VMOVNTDQYmr 3179
-VMOVNTDQZ 3180
-VMOVNTDQZmr 3181
-VMOVNTDQmr 3182
-VMOVNTPDYmr 3183
-VMOVNTPDZ 3184
-VMOVNTPDZmr 3185
-VMOVNTPDmr 3186
-VMOVNTPSYmr 3187
-VMOVNTPSZ 3188
-VMOVNTPSZmr 3189
-VMOVNTPSmr 3190
-VMOVPDI 3191
-VMOVPQI 3192
-VMOVPQIto 3193
-VMOVQI 3194
-VMOVRSBZ 3195
-VMOVRSBZm 3196
-VMOVRSBZmk 3197
-VMOVRSBZmkz 3198
-VMOVRSDZ 3199
-VMOVRSDZm 3200
-VMOVRSDZmk 3201
-VMOVRSDZmkz 3202
-VMOVRSQZ 3203
-VMOVRSQZm 3204
-VMOVRSQZmk 3205
-VMOVRSQZmkz 3206
-VMOVRSWZ 3207
-VMOVRSWZm 3208
-VMOVRSWZmk 3209
-VMOVRSWZmkz 3210
-VMOVSDZmr 3211
-VMOVSDZmrk 3212
-VMOVSDZrm 3213
-VMOVSDZrm_alt 3214
-VMOVSDZrmk 3215
-VMOVSDZrmkz 3216
-VMOVSDZrr 3217
-VMOVSDZrr_REV 3218
-VMOVSDZrrk 3219
-VMOVSDZrrk_REV 3220
-VMOVSDZrrkz 3221
-VMOVSDZrrkz_REV 3222
-VMOVSDmr 3223
-VMOVSDrm 3224
-VMOVSDrm_alt 3225
-VMOVSDrr 3226
-VMOVSDrr_REV 3227
-VMOVSDto 3228
-VMOVSH 3229
-VMOVSHDUPYrm 3230
-VMOVSHDUPYrr 3231
-VMOVSHDUPZ 3232
-VMOVSHDUPZrm 3233
-VMOVSHDUPZrmk 3234
-VMOVSHDUPZrmkz 3235
-VMOVSHDUPZrr 3236
-VMOVSHDUPZrrk 3237
-VMOVSHDUPZrrkz 3238
-VMOVSHDUPrm 3239
-VMOVSHDUPrr 3240
-VMOVSHZmr 3241
-VMOVSHZmrk 3242
-VMOVSHZrm 3243
-VMOVSHZrm_alt 3244
-VMOVSHZrmk 3245
-VMOVSHZrmkz 3246
-VMOVSHZrr 3247
-VMOVSHZrr_REV 3248
-VMOVSHZrrk 3249
-VMOVSHZrrk_REV 3250
-VMOVSHZrrkz 3251
-VMOVSHZrrkz_REV 3252
-VMOVSHtoW 3253
-VMOVSLDUPYrm 3254
-VMOVSLDUPYrr 3255
-VMOVSLDUPZ 3256
-VMOVSLDUPZrm 3257
-VMOVSLDUPZrmk 3258
-VMOVSLDUPZrmkz 3259
-VMOVSLDUPZrr 3260
-VMOVSLDUPZrrk 3261
-VMOVSLDUPZrrkz 3262
-VMOVSLDUPrm 3263
-VMOVSLDUPrr 3264
-VMOVSS 3265
-VMOVSSZmr 3266
-VMOVSSZmrk 3267
-VMOVSSZrm 3268
-VMOVSSZrm_alt 3269
-VMOVSSZrmk 3270
-VMOVSSZrmkz 3271
-VMOVSSZrr 3272
-VMOVSSZrr_REV 3273
-VMOVSSZrrk 3274
-VMOVSSZrrk_REV 3275
-VMOVSSZrrkz 3276
-VMOVSSZrrkz_REV 3277
-VMOVSSmr 3278
-VMOVSSrm 3279
-VMOVSSrm_alt 3280
-VMOVSSrr 3281
-VMOVSSrr_REV 3282
-VMOVUPDYmr 3283
-VMOVUPDYrm 3284
-VMOVUPDYrr 3285
-VMOVUPDYrr_REV 3286
-VMOVUPDZ 3287
-VMOVUPDZmr 3288
-VMOVUPDZmrk 3289
-VMOVUPDZrm 3290
-VMOVUPDZrmk 3291
-VMOVUPDZrmkz 3292
-VMOVUPDZrr 3293
-VMOVUPDZrr_REV 3294
-VMOVUPDZrrk 3295
-VMOVUPDZrrk_REV 3296
-VMOVUPDZrrkz 3297
-VMOVUPDZrrkz_REV 3298
-VMOVUPDmr 3299
-VMOVUPDrm 3300
-VMOVUPDrr 3301
-VMOVUPDrr_REV 3302
-VMOVUPSYmr 3303
-VMOVUPSYrm 3304
-VMOVUPSYrr 3305
-VMOVUPSYrr_REV 3306
-VMOVUPSZ 3307
-VMOVUPSZmr 3308
-VMOVUPSZmrk 3309
-VMOVUPSZrm 3310
-VMOVUPSZrmk 3311
-VMOVUPSZrmkz 3312
-VMOVUPSZrr 3313
-VMOVUPSZrr_REV 3314
-VMOVUPSZrrk 3315
-VMOVUPSZrrk_REV 3316
-VMOVUPSZrrkz 3317
-VMOVUPSZrrkz_REV 3318
-VMOVUPSmr 3319
-VMOVUPSrm 3320
-VMOVUPSrr 3321
-VMOVUPSrr_REV 3322
-VMOVW 3323
-VMOVWmr 3324
-VMOVWrm 3325
-VMOVZPDILo 3326
-VMOVZPQILo 3327
-VMOVZPWILo 3328
-VMPSADBWYrmi 3329
-VMPSADBWYrri 3330
-VMPSADBWZ 3331
-VMPSADBWZrmi 3332
-VMPSADBWZrmik 3333
-VMPSADBWZrmikz 3334
-VMPSADBWZrri 3335
-VMPSADBWZrrik 3336
-VMPSADBWZrrikz 3337
-VMPSADBWrmi 3338
-VMPSADBWrri 3339
-VMPTRLDm 3340
-VMPTRSTm 3341
-VMREAD 3342
-VMRESUME 3343
-VMRUN 3344
-VMSAVE 3345
-VMULBF 3346
-VMULPDYrm 3347
-VMULPDYrr 3348
-VMULPDZ 3349
-VMULPDZrm 3350
-VMULPDZrmb 3351
-VMULPDZrmbk 3352
-VMULPDZrmbkz 3353
-VMULPDZrmk 3354
-VMULPDZrmkz 3355
-VMULPDZrr 3356
-VMULPDZrrb 3357
-VMULPDZrrbk 3358
-VMULPDZrrbkz 3359
-VMULPDZrrk 3360
-VMULPDZrrkz 3361
-VMULPDrm 3362
-VMULPDrr 3363
-VMULPHZ 3364
-VMULPHZrm 3365
-VMULPHZrmb 3366
-VMULPHZrmbk 3367
-VMULPHZrmbkz 3368
-VMULPHZrmk 3369
-VMULPHZrmkz 3370
-VMULPHZrr 3371
-VMULPHZrrb 3372
-VMULPHZrrbk 3373
-VMULPHZrrbkz 3374
-VMULPHZrrk 3375
-VMULPHZrrkz 3376
-VMULPSYrm 3377
-VMULPSYrr 3378
-VMULPSZ 3379
-VMULPSZrm 3380
-VMULPSZrmb 3381
-VMULPSZrmbk 3382
-VMULPSZrmbkz 3383
-VMULPSZrmk 3384
-VMULPSZrmkz 3385
-VMULPSZrr 3386
-VMULPSZrrb 3387
-VMULPSZrrbk 3388
-VMULPSZrrbkz 3389
-VMULPSZrrk 3390
-VMULPSZrrkz 3391
-VMULPSrm 3392
-VMULPSrr 3393
-VMULSDZrm 3394
-VMULSDZrm_Int 3395
-VMULSDZrmk_Int 3396
-VMULSDZrmkz_Int 3397
-VMULSDZrr 3398
-VMULSDZrr_Int 3399
-VMULSDZrrb_Int 3400
-VMULSDZrrbk_Int 3401
-VMULSDZrrbkz_Int 3402
-VMULSDZrrk_Int 3403
-VMULSDZrrkz_Int 3404
-VMULSDrm 3405
-VMULSDrm_Int 3406
-VMULSDrr 3407
-VMULSDrr_Int 3408
-VMULSHZrm 3409
-VMULSHZrm_Int 3410
-VMULSHZrmk_Int 3411
-VMULSHZrmkz_Int 3412
-VMULSHZrr 3413
-VMULSHZrr_Int 3414
-VMULSHZrrb_Int 3415
-VMULSHZrrbk_Int 3416
-VMULSHZrrbkz_Int 3417
-VMULSHZrrk_Int 3418
-VMULSHZrrkz_Int 3419
-VMULSSZrm 3420
-VMULSSZrm_Int 3421
-VMULSSZrmk_Int 3422
-VMULSSZrmkz_Int 3423
-VMULSSZrr 3424
-VMULSSZrr_Int 3425
-VMULSSZrrb_Int 3426
-VMULSSZrrbk_Int 3427
-VMULSSZrrbkz_Int 3428
-VMULSSZrrk_Int 3429
-VMULSSZrrkz_Int 3430
-VMULSSrm 3431
-VMULSSrm_Int 3432
-VMULSSrr 3433
-VMULSSrr_Int 3434
-VMWRITE 3435
-VMXOFF 3436
-VMXON 3437
-VORPDYrm 3438
-VORPDYrr 3439
-VORPDZ 3440
-VORPDZrm 3441
-VORPDZrmb 3442
-VORPDZrmbk 3443
-VORPDZrmbkz 3444
-VORPDZrmk 3445
-VORPDZrmkz 3446
-VORPDZrr 3447
-VORPDZrrk 3448
-VORPDZrrkz 3449
-VORPDrm 3450
-VORPDrr 3451
-VORPSYrm 3452
-VORPSYrr 3453
-VORPSZ 3454
-VORPSZrm 3455
-VORPSZrmb 3456
-VORPSZrmbk 3457
-VORPSZrmbkz 3458
-VORPSZrmk 3459
-VORPSZrmkz 3460
-VORPSZrr 3461
-VORPSZrrk 3462
-VORPSZrrkz 3463
-VORPSrm 3464
-VORPSrr 3465
-VP 3466
-VPABSBYrm 3467
-VPABSBYrr 3468
-VPABSBZ 3469
-VPABSBZrm 3470
-VPABSBZrmk 3471
-VPABSBZrmkz 3472
-VPABSBZrr 3473
-VPABSBZrrk 3474
-VPABSBZrrkz 3475
-VPABSBrm 3476
-VPABSBrr 3477
-VPABSDYrm 3478
-VPABSDYrr 3479
-VPABSDZ 3480
-VPABSDZrm 3481
-VPABSDZrmb 3482
-VPABSDZrmbk 3483
-VPABSDZrmbkz 3484
-VPABSDZrmk 3485
-VPABSDZrmkz 3486
-VPABSDZrr 3487
-VPABSDZrrk 3488
-VPABSDZrrkz 3489
-VPABSDrm 3490
-VPABSDrr 3491
-VPABSQZ 3492
-VPABSQZrm 3493
-VPABSQZrmb 3494
-VPABSQZrmbk 3495
-VPABSQZrmbkz 3496
-VPABSQZrmk 3497
-VPABSQZrmkz 3498
-VPABSQZrr 3499
-VPABSQZrrk 3500
-VPABSQZrrkz 3501
-VPABSWYrm 3502
-VPABSWYrr 3503
-VPABSWZ 3504
-VPABSWZrm 3505
-VPABSWZrmk 3506
-VPABSWZrmkz 3507
-VPABSWZrr 3508
-VPABSWZrrk 3509
-VPABSWZrrkz 3510
-VPABSWrm 3511
-VPABSWrr 3512
-VPACKSSDWYrm 3513
-VPACKSSDWYrr 3514
-VPACKSSDWZ 3515
-VPACKSSDWZrm 3516
-VPACKSSDWZrmb 3517
-VPACKSSDWZrmbk 3518
-VPACKSSDWZrmbkz 3519
-VPACKSSDWZrmk 3520
-VPACKSSDWZrmkz 3521
-VPACKSSDWZrr 3522
-VPACKSSDWZrrk 3523
-VPACKSSDWZrrkz 3524
-VPACKSSDWrm 3525
-VPACKSSDWrr 3526
-VPACKSSWBYrm 3527
-VPACKSSWBYrr 3528
-VPACKSSWBZ 3529
-VPACKSSWBZrm 3530
-VPACKSSWBZrmk 3531
-VPACKSSWBZrmkz 3532
-VPACKSSWBZrr 3533
-VPACKSSWBZrrk 3534
-VPACKSSWBZrrkz 3535
-VPACKSSWBrm 3536
-VPACKSSWBrr 3537
-VPACKUSDWYrm 3538
-VPACKUSDWYrr 3539
-VPACKUSDWZ 3540
-VPACKUSDWZrm 3541
-VPACKUSDWZrmb 3542
-VPACKUSDWZrmbk 3543
-VPACKUSDWZrmbkz 3544
-VPACKUSDWZrmk 3545
-VPACKUSDWZrmkz 3546
-VPACKUSDWZrr 3547
-VPACKUSDWZrrk 3548
-VPACKUSDWZrrkz 3549
-VPACKUSDWrm 3550
-VPACKUSDWrr 3551
-VPACKUSWBYrm 3552
-VPACKUSWBYrr 3553
-VPACKUSWBZ 3554
-VPACKUSWBZrm 3555
-VPACKUSWBZrmk 3556
-VPACKUSWBZrmkz 3557
-VPACKUSWBZrr 3558
-VPACKUSWBZrrk 3559
-VPACKUSWBZrrkz 3560
-VPACKUSWBrm 3561
-VPACKUSWBrr 3562
-VPADDBYrm 3563
-VPADDBYrr 3564
-VPADDBZ 3565
-VPADDBZrm 3566
-VPADDBZrmk 3567
-VPADDBZrmkz 3568
-VPADDBZrr 3569
-VPADDBZrrk 3570
-VPADDBZrrkz 3571
-VPADDBrm 3572
-VPADDBrr 3573
-VPADDDYrm 3574
-VPADDDYrr 3575
-VPADDDZ 3576
-VPADDDZrm 3577
-VPADDDZrmb 3578
-VPADDDZrmbk 3579
-VPADDDZrmbkz 3580
-VPADDDZrmk 3581
-VPADDDZrmkz 3582
-VPADDDZrr 3583
-VPADDDZrrk 3584
-VPADDDZrrkz 3585
-VPADDDrm 3586
-VPADDDrr 3587
-VPADDQYrm 3588
-VPADDQYrr 3589
-VPADDQZ 3590
-VPADDQZrm 3591
-VPADDQZrmb 3592
-VPADDQZrmbk 3593
-VPADDQZrmbkz 3594
-VPADDQZrmk 3595
-VPADDQZrmkz 3596
-VPADDQZrr 3597
-VPADDQZrrk 3598
-VPADDQZrrkz 3599
-VPADDQrm 3600
-VPADDQrr 3601
-VPADDSBYrm 3602
-VPADDSBYrr 3603
-VPADDSBZ 3604
-VPADDSBZrm 3605
-VPADDSBZrmk 3606
-VPADDSBZrmkz 3607
-VPADDSBZrr 3608
-VPADDSBZrrk 3609
-VPADDSBZrrkz 3610
-VPADDSBrm 3611
-VPADDSBrr 3612
-VPADDSWYrm 3613
-VPADDSWYrr 3614
-VPADDSWZ 3615
-VPADDSWZrm 3616
-VPADDSWZrmk 3617
-VPADDSWZrmkz 3618
-VPADDSWZrr 3619
-VPADDSWZrrk 3620
-VPADDSWZrrkz 3621
-VPADDSWrm 3622
-VPADDSWrr 3623
-VPADDUSBYrm 3624
-VPADDUSBYrr 3625
-VPADDUSBZ 3626
-VPADDUSBZrm 3627
-VPADDUSBZrmk 3628
-VPADDUSBZrmkz 3629
-VPADDUSBZrr 3630
-VPADDUSBZrrk 3631
-VPADDUSBZrrkz 3632
-VPADDUSBrm 3633
-VPADDUSBrr 3634
-VPADDUSWYrm 3635
-VPADDUSWYrr 3636
-VPADDUSWZ 3637
-VPADDUSWZrm 3638
-VPADDUSWZrmk 3639
-VPADDUSWZrmkz 3640
-VPADDUSWZrr 3641
-VPADDUSWZrrk 3642
-VPADDUSWZrrkz 3643
-VPADDUSWrm 3644
-VPADDUSWrr 3645
-VPADDWYrm 3646
-VPADDWYrr 3647
-VPADDWZ 3648
-VPADDWZrm 3649
-VPADDWZrmk 3650
-VPADDWZrmkz 3651
-VPADDWZrr 3652
-VPADDWZrrk 3653
-VPADDWZrrkz 3654
-VPADDWrm 3655
-VPADDWrr 3656
-VPALIGNRYrmi 3657
-VPALIGNRYrri 3658
-VPALIGNRZ 3659
-VPALIGNRZrmi 3660
-VPALIGNRZrmik 3661
-VPALIGNRZrmikz 3662
-VPALIGNRZrri 3663
-VPALIGNRZrrik 3664
-VPALIGNRZrrikz 3665
-VPALIGNRrmi 3666
-VPALIGNRrri 3667
-VPANDDZ 3668
-VPANDDZrm 3669
-VPANDDZrmb 3670
-VPANDDZrmbk 3671
-VPANDDZrmbkz 3672
-VPANDDZrmk 3673
-VPANDDZrmkz 3674
-VPANDDZrr 3675
-VPANDDZrrk 3676
-VPANDDZrrkz 3677
-VPANDNDZ 3678
-VPANDNDZrm 3679
-VPANDNDZrmb 3680
-VPANDNDZrmbk 3681
-VPANDNDZrmbkz 3682
-VPANDNDZrmk 3683
-VPANDNDZrmkz 3684
-VPANDNDZrr 3685
-VPANDNDZrrk 3686
-VPANDNDZrrkz 3687
-VPANDNQZ 3688
-VPANDNQZrm 3689
-VPANDNQZrmb 3690
-VPANDNQZrmbk 3691
-VPANDNQZrmbkz 3692
-VPANDNQZrmk 3693
-VPANDNQZrmkz 3694
-VPANDNQZrr 3695
-VPANDNQZrrk 3696
-VPANDNQZrrkz 3697
-VPANDNYrm 3698
-VPANDNYrr 3699
-VPANDNrm 3700
-VPANDNrr 3701
-VPANDQZ 3702
-VPANDQZrm 3703
-VPANDQZrmb 3704
-VPANDQZrmbk 3705
-VPANDQZrmbkz 3706
-VPANDQZrmk 3707
-VPANDQZrmkz 3708
-VPANDQZrr 3709
-VPANDQZrrk 3710
-VPANDQZrrkz 3711
-VPANDYrm 3712
-VPANDYrr 3713
-VPANDrm 3714
-VPANDrr 3715
-VPAVGBYrm 3716
-VPAVGBYrr 3717
-VPAVGBZ 3718
-VPAVGBZrm 3719
-VPAVGBZrmk 3720
-VPAVGBZrmkz 3721
-VPAVGBZrr 3722
-VPAVGBZrrk 3723
-VPAVGBZrrkz 3724
-VPAVGBrm 3725
-VPAVGBrr 3726
-VPAVGWYrm 3727
-VPAVGWYrr 3728
-VPAVGWZ 3729
-VPAVGWZrm 3730
-VPAVGWZrmk 3731
-VPAVGWZrmkz 3732
-VPAVGWZrr 3733
-VPAVGWZrrk 3734
-VPAVGWZrrkz 3735
-VPAVGWrm 3736
-VPAVGWrr 3737
-VPBLENDDYrmi 3738
-VPBLENDDYrri 3739
-VPBLENDDrmi 3740
-VPBLENDDrri 3741
-VPBLENDMBZ 3742
-VPBLENDMBZrm 3743
-VPBLENDMBZrmk 3744
-VPBLENDMBZrmkz 3745
-VPBLENDMBZrr 3746
-VPBLENDMBZrrk 3747
-VPBLENDMBZrrkz 3748
-VPBLENDMDZ 3749
-VPBLENDMDZrm 3750
-VPBLENDMDZrmb 3751
-VPBLENDMDZrmbk 3752
-VPBLENDMDZrmbkz 3753
-VPBLENDMDZrmk 3754
-VPBLENDMDZrmkz 3755
-VPBLENDMDZrr 3756
-VPBLENDMDZrrk 3757
-VPBLENDMDZrrkz 3758
-VPBLENDMQZ 3759
-VPBLENDMQZrm 3760
-VPBLENDMQZrmb 3761
-VPBLENDMQZrmbk 3762
-VPBLENDMQZrmbkz 3763
-VPBLENDMQZrmk 3764
-VPBLENDMQZrmkz 3765
-VPBLENDMQZrr 3766
-VPBLENDMQZrrk 3767
-VPBLENDMQZrrkz 3768
-VPBLENDMWZ 3769
-VPBLENDMWZrm 3770
-VPBLENDMWZrmk 3771
-VPBLENDMWZrmkz 3772
-VPBLENDMWZrr 3773
-VPBLENDMWZrrk 3774
-VPBLENDMWZrrkz 3775
-VPBLENDVBYrmr 3776
-VPBLENDVBYrrr 3777
-VPBLENDVBrmr 3778
-VPBLENDVBrrr 3779
-VPBLENDWYrmi 3780
-VPBLENDWYrri 3781
-VPBLENDWrmi 3782
-VPBLENDWrri 3783
-VPBROADCASTBYrm 3784
-VPBROADCASTBYrr 3785
-VPBROADCASTBZ 3786
-VPBROADCASTBZrm 3787
-VPBROADCASTBZrmk 3788
-VPBROADCASTBZrmkz 3789
-VPBROADCASTBZrr 3790
-VPBROADCASTBZrrk 3791
-VPBROADCASTBZrrkz 3792
-VPBROADCASTBrZ 3793
-VPBROADCASTBrZrr 3794
-VPBROADCASTBrZrrk 3795
-VPBROADCASTBrZrrkz 3796
-VPBROADCASTBrm 3797
-VPBROADCASTBrr 3798
-VPBROADCASTDYrm 3799
-VPBROADCASTDYrr 3800
-VPBROADCASTDZ 3801
-VPBROADCASTDZrm 3802
-VPBROADCASTDZrmk 3803
-VPBROADCASTDZrmkz 3804
-VPBROADCASTDZrr 3805
-VPBROADCASTDZrrk 3806
-VPBROADCASTDZrrkz 3807
-VPBROADCASTDrZ 3808
-VPBROADCASTDrZrr 3809
-VPBROADCASTDrZrrk 3810
-VPBROADCASTDrZrrkz 3811
-VPBROADCASTDrm 3812
-VPBROADCASTDrr 3813
-VPBROADCASTMB 3814
-VPBROADCASTMW 3815
-VPBROADCASTQYrm 3816
-VPBROADCASTQYrr 3817
-VPBROADCASTQZ 3818
-VPBROADCASTQZrm 3819
-VPBROADCASTQZrmk 3820
-VPBROADCASTQZrmkz 3821
-VPBROADCASTQZrr 3822
-VPBROADCASTQZrrk 3823
-VPBROADCASTQZrrkz 3824
-VPBROADCASTQrZ 3825
-VPBROADCASTQrZrr 3826
-VPBROADCASTQrZrrk 3827
-VPBROADCASTQrZrrkz 3828
-VPBROADCASTQrm 3829
-VPBROADCASTQrr 3830
-VPBROADCASTWYrm 3831
-VPBROADCASTWYrr 3832
-VPBROADCASTWZ 3833
-VPBROADCASTWZrm 3834
-VPBROADCASTWZrmk 3835
-VPBROADCASTWZrmkz 3836
-VPBROADCASTWZrr 3837
-VPBROADCASTWZrrk 3838
-VPBROADCASTWZrrkz 3839
-VPBROADCASTWrZ 3840
-VPBROADCASTWrZrr 3841
-VPBROADCASTWrZrrk 3842
-VPBROADCASTWrZrrkz 3843
-VPBROADCASTWrm 3844
-VPBROADCASTWrr 3845
-VPCLMULQDQYrmi 3846
-VPCLMULQDQYrri 3847
-VPCLMULQDQZ 3848
-VPCLMULQDQZrmi 3849
-VPCLMULQDQZrri 3850
-VPCLMULQDQrmi 3851
-VPCLMULQDQrri 3852
-VPCMOVYrmr 3853
-VPCMOVYrrm 3854
-VPCMOVYrrr 3855
-VPCMOVYrrr_REV 3856
-VPCMOVrmr 3857
-VPCMOVrrm 3858
-VPCMOVrrr 3859
-VPCMOVrrr_REV 3860
-VPCMPBZ 3861
-VPCMPBZrmi 3862
-VPCMPBZrmik 3863
-VPCMPBZrri 3864
-VPCMPBZrrik 3865
-VPCMPDZ 3866
-VPCMPDZrmbi 3867
-VPCMPDZrmbik 3868
-VPCMPDZrmi 3869
-VPCMPDZrmik 3870
-VPCMPDZrri 3871
-VPCMPDZrrik 3872
-VPCMPEQBYrm 3873
-VPCMPEQBYrr 3874
-VPCMPEQBZ 3875
-VPCMPEQBZrm 3876
-VPCMPEQBZrmk 3877
-VPCMPEQBZrr 3878
-VPCMPEQBZrrk 3879
-VPCMPEQBrm 3880
-VPCMPEQBrr 3881
-VPCMPEQDYrm 3882
-VPCMPEQDYrr 3883
-VPCMPEQDZ 3884
-VPCMPEQDZrm 3885
-VPCMPEQDZrmb 3886
-VPCMPEQDZrmbk 3887
-VPCMPEQDZrmk 3888
-VPCMPEQDZrr 3889
-VPCMPEQDZrrk 3890
-VPCMPEQDrm 3891
-VPCMPEQDrr 3892
-VPCMPEQQYrm 3893
-VPCMPEQQYrr 3894
-VPCMPEQQZ 3895
-VPCMPEQQZrm 3896
-VPCMPEQQZrmb 3897
-VPCMPEQQZrmbk 3898
-VPCMPEQQZrmk 3899
-VPCMPEQQZrr 3900
-VPCMPEQQZrrk 3901
-VPCMPEQQrm 3902
-VPCMPEQQrr 3903
-VPCMPEQWYrm 3904
-VPCMPEQWYrr 3905
-VPCMPEQWZ 3906
-VPCMPEQWZrm 3907
-VPCMPEQWZrmk 3908
-VPCMPEQWZrr 3909
-VPCMPEQWZrrk 3910
-VPCMPEQWrm 3911
-VPCMPEQWrr 3912
-VPCMPESTRIrmi 3913
-VPCMPESTRIrri 3914
-VPCMPESTRMrmi 3915
-VPCMPESTRMrri 3916
-VPCMPGTBYrm 3917
-VPCMPGTBYrr 3918
-VPCMPGTBZ 3919
-VPCMPGTBZrm 3920
-VPCMPGTBZrmk 3921
-VPCMPGTBZrr 3922
-VPCMPGTBZrrk 3923
-VPCMPGTBrm 3924
-VPCMPGTBrr 3925
-VPCMPGTDYrm 3926
-VPCMPGTDYrr 3927
-VPCMPGTDZ 3928
-VPCMPGTDZrm 3929
-VPCMPGTDZrmb 3930
-VPCMPGTDZrmbk 3931
-VPCMPGTDZrmk 3932
-VPCMPGTDZrr 3933
-VPCMPGTDZrrk 3934
-VPCMPGTDrm 3935
-VPCMPGTDrr 3936
-VPCMPGTQYrm 3937
-VPCMPGTQYrr 3938
-VPCMPGTQZ 3939
-VPCMPGTQZrm 3940
-VPCMPGTQZrmb 3941
-VPCMPGTQZrmbk 3942
-VPCMPGTQZrmk 3943
-VPCMPGTQZrr 3944
-VPCMPGTQZrrk 3945
-VPCMPGTQrm 3946
-VPCMPGTQrr 3947
-VPCMPGTWYrm 3948
-VPCMPGTWYrr 3949
-VPCMPGTWZ 3950
-VPCMPGTWZrm 3951
-VPCMPGTWZrmk 3952
-VPCMPGTWZrr 3953
-VPCMPGTWZrrk 3954
-VPCMPGTWrm 3955
-VPCMPGTWrr 3956
-VPCMPISTRIrmi 3957
-VPCMPISTRIrri 3958
-VPCMPISTRMrmi 3959
-VPCMPISTRMrri 3960
-VPCMPQZ 3961
-VPCMPQZrmbi 3962
-VPCMPQZrmbik 3963
-VPCMPQZrmi 3964
-VPCMPQZrmik 3965
-VPCMPQZrri 3966
-VPCMPQZrrik 3967
-VPCMPUBZ 3968
-VPCMPUBZrmi 3969
-VPCMPUBZrmik 3970
-VPCMPUBZrri 3971
-VPCMPUBZrrik 3972
-VPCMPUDZ 3973
-VPCMPUDZrmbi 3974
-VPCMPUDZrmbik 3975
-VPCMPUDZrmi 3976
-VPCMPUDZrmik 3977
-VPCMPUDZrri 3978
-VPCMPUDZrrik 3979
-VPCMPUQZ 3980
-VPCMPUQZrmbi 3981
-VPCMPUQZrmbik 3982
-VPCMPUQZrmi 3983
-VPCMPUQZrmik 3984
-VPCMPUQZrri 3985
-VPCMPUQZrrik 3986
-VPCMPUWZ 3987
-VPCMPUWZrmi 3988
-VPCMPUWZrmik 3989
-VPCMPUWZrri 3990
-VPCMPUWZrrik 3991
-VPCMPWZ 3992
-VPCMPWZrmi 3993
-VPCMPWZrmik 3994
-VPCMPWZrri 3995
-VPCMPWZrrik 3996
-VPCOMBmi 3997
-VPCOMBri 3998
-VPCOMDmi 3999
-VPCOMDri 4000
-VPCOMPRESSBZ 4001
-VPCOMPRESSBZmr 4002
-VPCOMPRESSBZmrk 4003
-VPCOMPRESSBZrr 4004
-VPCOMPRESSBZrrk 4005
-VPCOMPRESSBZrrkz 4006
-VPCOMPRESSDZ 4007
-VPCOMPRESSDZmr 4008
-VPCOMPRESSDZmrk 4009
-VPCOMPRESSDZrr 4010
-VPCOMPRESSDZrrk 4011
-VPCOMPRESSDZrrkz 4012
-VPCOMPRESSQZ 4013
-VPCOMPRESSQZmr 4014
-VPCOMPRESSQZmrk 4015
-VPCOMPRESSQZrr 4016
-VPCOMPRESSQZrrk 4017
-VPCOMPRESSQZrrkz 4018
-VPCOMPRESSWZ 4019
-VPCOMPRESSWZmr 4020
-VPCOMPRESSWZmrk 4021
-VPCOMPRESSWZrr 4022
-VPCOMPRESSWZrrk 4023
-VPCOMPRESSWZrrkz 4024
-VPCOMQmi 4025
-VPCOMQri 4026
-VPCOMUBmi 4027
-VPCOMUBri 4028
-VPCOMUDmi 4029
-VPCOMUDri 4030
-VPCOMUQmi 4031
-VPCOMUQri 4032
-VPCOMUWmi 4033
-VPCOMUWri 4034
-VPCOMWmi 4035
-VPCOMWri 4036
-VPCONFLICTDZ 4037
-VPCONFLICTDZrm 4038
-VPCONFLICTDZrmb 4039
-VPCONFLICTDZrmbk 4040
-VPCONFLICTDZrmbkz 4041
-VPCONFLICTDZrmk 4042
-VPCONFLICTDZrmkz 4043
-VPCONFLICTDZrr 4044
-VPCONFLICTDZrrk 4045
-VPCONFLICTDZrrkz 4046
-VPCONFLICTQZ 4047
-VPCONFLICTQZrm 4048
-VPCONFLICTQZrmb 4049
-VPCONFLICTQZrmbk 4050
-VPCONFLICTQZrmbkz 4051
-VPCONFLICTQZrmk 4052
-VPCONFLICTQZrmkz 4053
-VPCONFLICTQZrr 4054
-VPCONFLICTQZrrk 4055
-VPCONFLICTQZrrkz 4056
-VPDPBSSDSYrm 4057
-VPDPBSSDSYrr 4058
-VPDPBSSDSZ 4059
-VPDPBSSDSZrm 4060
-VPDPBSSDSZrmb 4061
-VPDPBSSDSZrmbk 4062
-VPDPBSSDSZrmbkz 4063
-VPDPBSSDSZrmk 4064
-VPDPBSSDSZrmkz 4065
-VPDPBSSDSZrr 4066
-VPDPBSSDSZrrk 4067
-VPDPBSSDSZrrkz 4068
-VPDPBSSDSrm 4069
-VPDPBSSDSrr 4070
-VPDPBSSDYrm 4071
-VPDPBSSDYrr 4072
-VPDPBSSDZ 4073
-VPDPBSSDZrm 4074
-VPDPBSSDZrmb 4075
-VPDPBSSDZrmbk 4076
-VPDPBSSDZrmbkz 4077
-VPDPBSSDZrmk 4078
-VPDPBSSDZrmkz 4079
-VPDPBSSDZrr 4080
-VPDPBSSDZrrk 4081
-VPDPBSSDZrrkz 4082
-VPDPBSSDrm 4083
-VPDPBSSDrr 4084
-VPDPBSUDSYrm 4085
-VPDPBSUDSYrr 4086
-VPDPBSUDSZ 4087
-VPDPBSUDSZrm 4088
-VPDPBSUDSZrmb 4089
-VPDPBSUDSZrmbk 4090
-VPDPBSUDSZrmbkz 4091
-VPDPBSUDSZrmk 4092
-VPDPBSUDSZrmkz 4093
-VPDPBSUDSZrr 4094
-VPDPBSUDSZrrk 4095
-VPDPBSUDSZrrkz 4096
-VPDPBSUDSrm 4097
-VPDPBSUDSrr 4098
-VPDPBSUDYrm 4099
-VPDPBSUDYrr 4100
-VPDPBSUDZ 4101
-VPDPBSUDZrm 4102
-VPDPBSUDZrmb 4103
-VPDPBSUDZrmbk 4104
-VPDPBSUDZrmbkz 4105
-VPDPBSUDZrmk 4106
-VPDPBSUDZrmkz 4107
-VPDPBSUDZrr 4108
-VPDPBSUDZrrk 4109
-VPDPBSUDZrrkz 4110
-VPDPBSUDrm 4111
-VPDPBSUDrr 4112
-VPDPBUSDSYrm 4113
-VPDPBUSDSYrr 4114
-VPDPBUSDSZ 4115
-VPDPBUSDSZrm 4116
-VPDPBUSDSZrmb 4117
-VPDPBUSDSZrmbk 4118
-VPDPBUSDSZrmbkz 4119
-VPDPBUSDSZrmk 4120
-VPDPBUSDSZrmkz 4121
-VPDPBUSDSZrr 4122
-VPDPBUSDSZrrk 4123
-VPDPBUSDSZrrkz 4124
-VPDPBUSDSrm 4125
-VPDPBUSDSrr 4126
-VPDPBUSDYrm 4127
-VPDPBUSDYrr 4128
-VPDPBUSDZ 4129
-VPDPBUSDZrm 4130
-VPDPBUSDZrmb 4131
-VPDPBUSDZrmbk 4132
-VPDPBUSDZrmbkz 4133
-VPDPBUSDZrmk 4134
-VPDPBUSDZrmkz 4135
-VPDPBUSDZrr 4136
-VPDPBUSDZrrk 4137
-VPDPBUSDZrrkz 4138
-VPDPBUSDrm 4139
-VPDPBUSDrr 4140
-VPDPBUUDSYrm 4141
-VPDPBUUDSYrr 4142
-VPDPBUUDSZ 4143
-VPDPBUUDSZrm 4144
-VPDPBUUDSZrmb 4145
-VPDPBUUDSZrmbk 4146
-VPDPBUUDSZrmbkz 4147
-VPDPBUUDSZrmk 4148
-VPDPBUUDSZrmkz 4149
-VPDPBUUDSZrr 4150
-VPDPBUUDSZrrk 4151
-VPDPBUUDSZrrkz 4152
-VPDPBUUDSrm 4153
-VPDPBUUDSrr 4154
-VPDPBUUDYrm 4155
-VPDPBUUDYrr 4156
-VPDPBUUDZ 4157
-VPDPBUUDZrm 4158
-VPDPBUUDZrmb 4159
-VPDPBUUDZrmbk 4160
-VPDPBUUDZrmbkz 4161
-VPDPBUUDZrmk 4162
-VPDPBUUDZrmkz 4163
-VPDPBUUDZrr 4164
-VPDPBUUDZrrk 4165
-VPDPBUUDZrrkz 4166
-VPDPBUUDrm 4167
-VPDPBUUDrr 4168
-VPDPWSSDSYrm 4169
-VPDPWSSDSYrr 4170
-VPDPWSSDSZ 4171
-VPDPWSSDSZrm 4172
-VPDPWSSDSZrmb 4173
-VPDPWSSDSZrmbk 4174
-VPDPWSSDSZrmbkz 4175
-VPDPWSSDSZrmk 4176
-VPDPWSSDSZrmkz 4177
-VPDPWSSDSZrr 4178
-VPDPWSSDSZrrk 4179
-VPDPWSSDSZrrkz 4180
-VPDPWSSDSrm 4181
-VPDPWSSDSrr 4182
-VPDPWSSDYrm 4183
-VPDPWSSDYrr 4184
-VPDPWSSDZ 4185
-VPDPWSSDZrm 4186
-VPDPWSSDZrmb 4187
-VPDPWSSDZrmbk 4188
-VPDPWSSDZrmbkz 4189
-VPDPWSSDZrmk 4190
-VPDPWSSDZrmkz 4191
-VPDPWSSDZrr 4192
-VPDPWSSDZrrk 4193
-VPDPWSSDZrrkz 4194
-VPDPWSSDrm 4195
-VPDPWSSDrr 4196
-VPDPWSUDSYrm 4197
-VPDPWSUDSYrr 4198
-VPDPWSUDSZ 4199
-VPDPWSUDSZrm 4200
-VPDPWSUDSZrmb 4201
-VPDPWSUDSZrmbk 4202
-VPDPWSUDSZrmbkz 4203
-VPDPWSUDSZrmk 4204
-VPDPWSUDSZrmkz 4205
-VPDPWSUDSZrr 4206
-VPDPWSUDSZrrk 4207
-VPDPWSUDSZrrkz 4208
-VPDPWSUDSrm 4209
-VPDPWSUDSrr 4210
-VPDPWSUDYrm 4211
-VPDPWSUDYrr 4212
-VPDPWSUDZ 4213
-VPDPWSUDZrm 4214
-VPDPWSUDZrmb 4215
-VPDPWSUDZrmbk 4216
-VPDPWSUDZrmbkz 4217
-VPDPWSUDZrmk 4218
-VPDPWSUDZrmkz 4219
-VPDPWSUDZrr 4220
-VPDPWSUDZrrk 4221
-VPDPWSUDZrrkz 4222
-VPDPWSUDrm 4223
-VPDPWSUDrr 4224
-VPDPWUSDSYrm 4225
-VPDPWUSDSYrr 4226
-VPDPWUSDSZ 4227
-VPDPWUSDSZrm 4228
-VPDPWUSDSZrmb 4229
-VPDPWUSDSZrmbk 4230
-VPDPWUSDSZrmbkz 4231
-VPDPWUSDSZrmk 4232
-VPDPWUSDSZrmkz 4233
-VPDPWUSDSZrr 4234
-VPDPWUSDSZrrk 4235
-VPDPWUSDSZrrkz 4236
-VPDPWUSDSrm 4237
-VPDPWUSDSrr 4238
-VPDPWUSDYrm 4239
-VPDPWUSDYrr 4240
-VPDPWUSDZ 4241
-VPDPWUSDZrm 4242
-VPDPWUSDZrmb 4243
-VPDPWUSDZrmbk 4244
-VPDPWUSDZrmbkz 4245
-VPDPWUSDZrmk 4246
-VPDPWUSDZrmkz 4247
-VPDPWUSDZrr 4248
-VPDPWUSDZrrk 4249
-VPDPWUSDZrrkz 4250
-VPDPWUSDrm 4251
-VPDPWUSDrr 4252
-VPDPWUUDSYrm 4253
-VPDPWUUDSYrr 4254
-VPDPWUUDSZ 4255
-VPDPWUUDSZrm 4256
-VPDPWUUDSZrmb 4257
-VPDPWUUDSZrmbk 4258
-VPDPWUUDSZrmbkz 4259
-VPDPWUUDSZrmk 4260
-VPDPWUUDSZrmkz 4261
-VPDPWUUDSZrr 4262
-VPDPWUUDSZrrk 4263
-VPDPWUUDSZrrkz 4264
-VPDPWUUDSrm 4265
-VPDPWUUDSrr 4266
-VPDPWUUDYrm 4267
-VPDPWUUDYrr 4268
-VPDPWUUDZ 4269
-VPDPWUUDZrm 4270
-VPDPWUUDZrmb 4271
-VPDPWUUDZrmbk 4272
-VPDPWUUDZrmbkz 4273
-VPDPWUUDZrmk 4274
-VPDPWUUDZrmkz 4275
-VPDPWUUDZrr 4276
-VPDPWUUDZrrk 4277
-VPDPWUUDZrrkz 4278
-VPDPWUUDrm 4279
-VPDPWUUDrr 4280
-VPERM 4281
-VPERMBZ 4282
-VPERMBZrm 4283
-VPERMBZrmk 4284
-VPERMBZrmkz 4285
-VPERMBZrr 4286
-VPERMBZrrk 4287
-VPERMBZrrkz 4288
-VPERMDYrm 4289
-VPERMDYrr 4290
-VPERMDZ 4291
-VPERMDZrm 4292
-VPERMDZrmb 4293
-VPERMDZrmbk 4294
-VPERMDZrmbkz 4295
-VPERMDZrmk 4296
-VPERMDZrmkz 4297
-VPERMDZrr 4298
-VPERMDZrrk 4299
-VPERMDZrrkz 4300
-VPERMI 4301
-VPERMIL 4302
-VPERMILPDYmi 4303
-VPERMILPDYri 4304
-VPERMILPDYrm 4305
-VPERMILPDYrr 4306
-VPERMILPDZ 4307
-VPERMILPDZmbi 4308
-VPERMILPDZmbik 4309
-VPERMILPDZmbikz 4310
-VPERMILPDZmi 4311
-VPERMILPDZmik 4312
-VPERMILPDZmikz 4313
-VPERMILPDZri 4314
-VPERMILPDZrik 4315
-VPERMILPDZrikz 4316
-VPERMILPDZrm 4317
-VPERMILPDZrmb 4318
-VPERMILPDZrmbk 4319
-VPERMILPDZrmbkz 4320
-VPERMILPDZrmk 4321
-VPERMILPDZrmkz 4322
-VPERMILPDZrr 4323
-VPERMILPDZrrk 4324
-VPERMILPDZrrkz 4325
-VPERMILPDmi 4326
-VPERMILPDri 4327
-VPERMILPDrm 4328
-VPERMILPDrr 4329
-VPERMILPSYmi 4330
-VPERMILPSYri 4331
-VPERMILPSYrm 4332
-VPERMILPSYrr 4333
-VPERMILPSZ 4334
-VPERMILPSZmbi 4335
-VPERMILPSZmbik 4336
-VPERMILPSZmbikz 4337
-VPERMILPSZmi 4338
-VPERMILPSZmik 4339
-VPERMILPSZmikz 4340
-VPERMILPSZri 4341
-VPERMILPSZrik 4342
-VPERMILPSZrikz 4343
-VPERMILPSZrm 4344
-VPERMILPSZrmb 4345
-VPERMILPSZrmbk 4346
-VPERMILPSZrmbkz 4347
-VPERMILPSZrmk 4348
-VPERMILPSZrmkz 4349
-VPERMILPSZrr 4350
-VPERMILPSZrrk 4351
-VPERMILPSZrrkz 4352
-VPERMILPSmi 4353
-VPERMILPSri 4354
-VPERMILPSrm 4355
-VPERMILPSrr 4356
-VPERMPDYmi 4357
-VPERMPDYri 4358
-VPERMPDZ 4359
-VPERMPDZmbi 4360
-VPERMPDZmbik 4361
-VPERMPDZmbikz 4362
-VPERMPDZmi 4363
-VPERMPDZmik 4364
-VPERMPDZmikz 4365
-VPERMPDZri 4366
-VPERMPDZrik 4367
-VPERMPDZrikz 4368
-VPERMPDZrm 4369
-VPERMPDZrmb 4370
-VPERMPDZrmbk 4371
-VPERMPDZrmbkz 4372
-VPERMPDZrmk 4373
-VPERMPDZrmkz 4374
-VPERMPDZrr 4375
-VPERMPDZrrk 4376
-VPERMPDZrrkz 4377
-VPERMPSYrm 4378
-VPERMPSYrr 4379
-VPERMPSZ 4380
-VPERMPSZrm 4381
-VPERMPSZrmb 4382
-VPERMPSZrmbk 4383
-VPERMPSZrmbkz 4384
-VPERMPSZrmk 4385
-VPERMPSZrmkz 4386
-VPERMPSZrr 4387
-VPERMPSZrrk 4388
-VPERMPSZrrkz 4389
-VPERMQYmi 4390
-VPERMQYri 4391
-VPERMQZ 4392
-VPERMQZmbi 4393
-VPERMQZmbik 4394
-VPERMQZmbikz 4395
-VPERMQZmi 4396
-VPERMQZmik 4397
-VPERMQZmikz 4398
-VPERMQZri 4399
-VPERMQZrik 4400
-VPERMQZrikz 4401
-VPERMQZrm 4402
-VPERMQZrmb 4403
-VPERMQZrmbk 4404
-VPERMQZrmbkz 4405
-VPERMQZrmk 4406
-VPERMQZrmkz 4407
-VPERMQZrr 4408
-VPERMQZrrk 4409
-VPERMQZrrkz 4410
-VPERMT 4411
-VPERMWZ 4412
-VPERMWZrm 4413
-VPERMWZrmk 4414
-VPERMWZrmkz 4415
-VPERMWZrr 4416
-VPERMWZrrk 4417
-VPERMWZrrkz 4418
-VPEXPANDBZ 4419
-VPEXPANDBZrm 4420
-VPEXPANDBZrmk 4421
-VPEXPANDBZrmkz 4422
-VPEXPANDBZrr 4423
-VPEXPANDBZrrk 4424
-VPEXPANDBZrrkz 4425
-VPEXPANDDZ 4426
-VPEXPANDDZrm 4427
-VPEXPANDDZrmk 4428
-VPEXPANDDZrmkz 4429
-VPEXPANDDZrr 4430
-VPEXPANDDZrrk 4431
-VPEXPANDDZrrkz 4432
-VPEXPANDQZ 4433
-VPEXPANDQZrm 4434
-VPEXPANDQZrmk 4435
-VPEXPANDQZrmkz 4436
-VPEXPANDQZrr 4437
-VPEXPANDQZrrk 4438
-VPEXPANDQZrrkz 4439
-VPEXPANDWZ 4440
-VPEXPANDWZrm 4441
-VPEXPANDWZrmk 4442
-VPEXPANDWZrmkz 4443
-VPEXPANDWZrr 4444
-VPEXPANDWZrrk 4445
-VPEXPANDWZrrkz 4446
-VPEXTRBZmri 4447
-VPEXTRBZrri 4448
-VPEXTRBmri 4449
-VPEXTRBrri 4450
-VPEXTRDZmri 4451
-VPEXTRDZrri 4452
-VPEXTRDmri 4453
-VPEXTRDrri 4454
-VPEXTRQZmri 4455
-VPEXTRQZrri 4456
-VPEXTRQmri 4457
-VPEXTRQrri 4458
-VPEXTRWZmri 4459
-VPEXTRWZrri 4460
-VPEXTRWZrri_REV 4461
-VPEXTRWmri 4462
-VPEXTRWrri 4463
-VPEXTRWrri_REV 4464
-VPGATHERDDYrm 4465
-VPGATHERDDZ 4466
-VPGATHERDDZrm 4467
-VPGATHERDDrm 4468
-VPGATHERDQYrm 4469
-VPGATHERDQZ 4470
-VPGATHERDQZrm 4471
-VPGATHERDQrm 4472
-VPGATHERQDYrm 4473
-VPGATHERQDZ 4474
-VPGATHERQDZrm 4475
-VPGATHERQDrm 4476
-VPGATHERQQYrm 4477
-VPGATHERQQZ 4478
-VPGATHERQQZrm 4479
-VPGATHERQQrm 4480
-VPHADDBDrm 4481
-VPHADDBDrr 4482
-VPHADDBQrm 4483
-VPHADDBQrr 4484
-VPHADDBWrm 4485
-VPHADDBWrr 4486
-VPHADDDQrm 4487
-VPHADDDQrr 4488
-VPHADDDYrm 4489
-VPHADDDYrr 4490
-VPHADDDrm 4491
-VPHADDDrr 4492
-VPHADDSWYrm 4493
-VPHADDSWYrr 4494
-VPHADDSWrm 4495
-VPHADDSWrr 4496
-VPHADDUBDrm 4497
-VPHADDUBDrr 4498
-VPHADDUBQrm 4499
-VPHADDUBQrr 4500
-VPHADDUBWrm 4501
-VPHADDUBWrr 4502
-VPHADDUDQrm 4503
-VPHADDUDQrr 4504
-VPHADDUWDrm 4505
-VPHADDUWDrr 4506
-VPHADDUWQrm 4507
-VPHADDUWQrr 4508
-VPHADDWDrm 4509
-VPHADDWDrr 4510
-VPHADDWQrm 4511
-VPHADDWQrr 4512
-VPHADDWYrm 4513
-VPHADDWYrr 4514
-VPHADDWrm 4515
-VPHADDWrr 4516
-VPHMINPOSUWrm 4517
-VPHMINPOSUWrr 4518
-VPHSUBBWrm 4519
-VPHSUBBWrr 4520
-VPHSUBDQrm 4521
-VPHSUBDQrr 4522
-VPHSUBDYrm 4523
-VPHSUBDYrr 4524
-VPHSUBDrm 4525
-VPHSUBDrr 4526
-VPHSUBSWYrm 4527
-VPHSUBSWYrr 4528
-VPHSUBSWrm 4529
-VPHSUBSWrr 4530
-VPHSUBWDrm 4531
-VPHSUBWDrr 4532
-VPHSUBWYrm 4533
-VPHSUBWYrr 4534
-VPHSUBWrm 4535
-VPHSUBWrr 4536
-VPINSRBZrmi 4537
-VPINSRBZrri 4538
-VPINSRBrmi 4539
-VPINSRBrri 4540
-VPINSRDZrmi 4541
-VPINSRDZrri 4542
-VPINSRDrmi 4543
-VPINSRDrri 4544
-VPINSRQZrmi 4545
-VPINSRQZrri 4546
-VPINSRQrmi 4547
-VPINSRQrri 4548
-VPINSRWZrmi 4549
-VPINSRWZrri 4550
-VPINSRWrmi 4551
-VPINSRWrri 4552
-VPLZCNTDZ 4553
-VPLZCNTDZrm 4554
-VPLZCNTDZrmb 4555
-VPLZCNTDZrmbk 4556
-VPLZCNTDZrmbkz 4557
-VPLZCNTDZrmk 4558
-VPLZCNTDZrmkz 4559
-VPLZCNTDZrr 4560
-VPLZCNTDZrrk 4561
-VPLZCNTDZrrkz 4562
-VPLZCNTQZ 4563
-VPLZCNTQZrm 4564
-VPLZCNTQZrmb 4565
-VPLZCNTQZrmbk 4566
-VPLZCNTQZrmbkz 4567
-VPLZCNTQZrmk 4568
-VPLZCNTQZrmkz 4569
-VPLZCNTQZrr 4570
-VPLZCNTQZrrk 4571
-VPLZCNTQZrrkz 4572
-VPMACSDDrm 4573
-VPMACSDDrr 4574
-VPMACSDQHrm 4575
-VPMACSDQHrr 4576
-VPMACSDQLrm 4577
-VPMACSDQLrr 4578
-VPMACSSDDrm 4579
-VPMACSSDDrr 4580
-VPMACSSDQHrm 4581
-VPMACSSDQHrr 4582
-VPMACSSDQLrm 4583
-VPMACSSDQLrr 4584
-VPMACSSWDrm 4585
-VPMACSSWDrr 4586
-VPMACSSWWrm 4587
-VPMACSSWWrr 4588
-VPMACSWDrm 4589
-VPMACSWDrr 4590
-VPMACSWWrm 4591
-VPMACSWWrr 4592
-VPMADCSSWDrm 4593
-VPMADCSSWDrr 4594
-VPMADCSWDrm 4595
-VPMADCSWDrr 4596
-VPMADD 4597
-VPMADDUBSWYrm 4598
-VPMADDUBSWYrr 4599
-VPMADDUBSWZ 4600
-VPMADDUBSWZrm 4601
-VPMADDUBSWZrmk 4602
-VPMADDUBSWZrmkz 4603
-VPMADDUBSWZrr 4604
-VPMADDUBSWZrrk 4605
-VPMADDUBSWZrrkz 4606
-VPMADDUBSWrm 4607
-VPMADDUBSWrr 4608
-VPMADDWDYrm 4609
-VPMADDWDYrr 4610
-VPMADDWDZ 4611
-VPMADDWDZrm 4612
-VPMADDWDZrmk 4613
-VPMADDWDZrmkz 4614
-VPMADDWDZrr 4615
-VPMADDWDZrrk 4616
-VPMADDWDZrrkz 4617
-VPMADDWDrm 4618
-VPMADDWDrr 4619
-VPMASKMOVDYmr 4620
-VPMASKMOVDYrm 4621
-VPMASKMOVDmr 4622
-VPMASKMOVDrm 4623
-VPMASKMOVQYmr 4624
-VPMASKMOVQYrm 4625
-VPMASKMOVQmr 4626
-VPMASKMOVQrm 4627
-VPMAXSBYrm 4628
-VPMAXSBYrr 4629
-VPMAXSBZ 4630
-VPMAXSBZrm 4631
-VPMAXSBZrmk 4632
-VPMAXSBZrmkz 4633
-VPMAXSBZrr 4634
-VPMAXSBZrrk 4635
-VPMAXSBZrrkz 4636
-VPMAXSBrm 4637
-VPMAXSBrr 4638
-VPMAXSDYrm 4639
-VPMAXSDYrr 4640
-VPMAXSDZ 4641
-VPMAXSDZrm 4642
-VPMAXSDZrmb 4643
-VPMAXSDZrmbk 4644
-VPMAXSDZrmbkz 4645
-VPMAXSDZrmk 4646
-VPMAXSDZrmkz 4647
-VPMAXSDZrr 4648
-VPMAXSDZrrk 4649
-VPMAXSDZrrkz 4650
-VPMAXSDrm 4651
-VPMAXSDrr 4652
-VPMAXSQZ 4653
-VPMAXSQZrm 4654
-VPMAXSQZrmb 4655
-VPMAXSQZrmbk 4656
-VPMAXSQZrmbkz 4657
-VPMAXSQZrmk 4658
-VPMAXSQZrmkz 4659
-VPMAXSQZrr 4660
-VPMAXSQZrrk 4661
-VPMAXSQZrrkz 4662
-VPMAXSWYrm 4663
-VPMAXSWYrr 4664
-VPMAXSWZ 4665
-VPMAXSWZrm 4666
-VPMAXSWZrmk 4667
-VPMAXSWZrmkz 4668
-VPMAXSWZrr 4669
-VPMAXSWZrrk 4670
-VPMAXSWZrrkz 4671
-VPMAXSWrm 4672
-VPMAXSWrr 4673
-VPMAXUBYrm 4674
-VPMAXUBYrr 4675
-VPMAXUBZ 4676
-VPMAXUBZrm 4677
-VPMAXUBZrmk 4678
-VPMAXUBZrmkz 4679
-VPMAXUBZrr 4680
-VPMAXUBZrrk 4681
-VPMAXUBZrrkz 4682
-VPMAXUBrm 4683
-VPMAXUBrr 4684
-VPMAXUDYrm 4685
-VPMAXUDYrr 4686
-VPMAXUDZ 4687
-VPMAXUDZrm 4688
-VPMAXUDZrmb 4689
-VPMAXUDZrmbk 4690
-VPMAXUDZrmbkz 4691
-VPMAXUDZrmk 4692
-VPMAXUDZrmkz 4693
-VPMAXUDZrr 4694
-VPMAXUDZrrk 4695
-VPMAXUDZrrkz 4696
-VPMAXUDrm 4697
-VPMAXUDrr 4698
-VPMAXUQZ 4699
-VPMAXUQZrm 4700
-VPMAXUQZrmb 4701
-VPMAXUQZrmbk 4702
-VPMAXUQZrmbkz 4703
-VPMAXUQZrmk 4704
-VPMAXUQZrmkz 4705
-VPMAXUQZrr 4706
-VPMAXUQZrrk 4707
-VPMAXUQZrrkz 4708
-VPMAXUWYrm 4709
-VPMAXUWYrr 4710
-VPMAXUWZ 4711
-VPMAXUWZrm 4712
-VPMAXUWZrmk 4713
-VPMAXUWZrmkz 4714
-VPMAXUWZrr 4715
-VPMAXUWZrrk 4716
-VPMAXUWZrrkz 4717
-VPMAXUWrm 4718
-VPMAXUWrr 4719
-VPMINSBYrm 4720
-VPMINSBYrr 4721
-VPMINSBZ 4722
-VPMINSBZrm 4723
-VPMINSBZrmk 4724
-VPMINSBZrmkz 4725
-VPMINSBZrr 4726
-VPMINSBZrrk 4727
-VPMINSBZrrkz 4728
-VPMINSBrm 4729
-VPMINSBrr 4730
-VPMINSDYrm 4731
-VPMINSDYrr 4732
-VPMINSDZ 4733
-VPMINSDZrm 4734
-VPMINSDZrmb 4735
-VPMINSDZrmbk 4736
-VPMINSDZrmbkz 4737
-VPMINSDZrmk 4738
-VPMINSDZrmkz 4739
-VPMINSDZrr 4740
-VPMINSDZrrk 4741
-VPMINSDZrrkz 4742
-VPMINSDrm 4743
-VPMINSDrr 4744
-VPMINSQZ 4745
-VPMINSQZrm 4746
-VPMINSQZrmb 4747
-VPMINSQZrmbk 4748
-VPMINSQZrmbkz 4749
-VPMINSQZrmk 4750
-VPMINSQZrmkz 4751
-VPMINSQZrr 4752
-VPMINSQZrrk 4753
-VPMINSQZrrkz 4754
-VPMINSWYrm 4755
-VPMINSWYrr 4756
-VPMINSWZ 4757
-VPMINSWZrm 4758
-VPMINSWZrmk 4759
-VPMINSWZrmkz 4760
-VPMINSWZrr 4761
-VPMINSWZrrk 4762
-VPMINSWZrrkz 4763
-VPMINSWrm 4764
-VPMINSWrr 4765
-VPMINUBYrm 4766
-VPMINUBYrr 4767
-VPMINUBZ 4768
-VPMINUBZrm 4769
-VPMINUBZrmk 4770
-VPMINUBZrmkz 4771
-VPMINUBZrr 4772
-VPMINUBZrrk 4773
-VPMINUBZrrkz 4774
-VPMINUBrm 4775
-VPMINUBrr 4776
-VPMINUDYrm 4777
-VPMINUDYrr 4778
-VPMINUDZ 4779
-VPMINUDZrm 4780
-VPMINUDZrmb 4781
-VPMINUDZrmbk 4782
-VPMINUDZrmbkz 4783
-VPMINUDZrmk 4784
-VPMINUDZrmkz 4785
-VPMINUDZrr 4786
-VPMINUDZrrk 4787
-VPMINUDZrrkz 4788
-VPMINUDrm 4789
-VPMINUDrr 4790
-VPMINUQZ 4791
-VPMINUQZrm 4792
-VPMINUQZrmb 4793
-VPMINUQZrmbk 4794
-VPMINUQZrmbkz 4795
-VPMINUQZrmk 4796
-VPMINUQZrmkz 4797
-VPMINUQZrr 4798
-VPMINUQZrrk 4799
-VPMINUQZrrkz 4800
-VPMINUWYrm 4801
-VPMINUWYrr 4802
-VPMINUWZ 4803
-VPMINUWZrm 4804
-VPMINUWZrmk 4805
-VPMINUWZrmkz 4806
-VPMINUWZrr 4807
-VPMINUWZrrk 4808
-VPMINUWZrrkz 4809
-VPMINUWrm 4810
-VPMINUWrr 4811
-VPMOVB 4812
-VPMOVD 4813
-VPMOVDBZ 4814
-VPMOVDBZmr 4815
-VPMOVDBZmrk 4816
-VPMOVDBZrr 4817
-VPMOVDBZrrk 4818
-VPMOVDBZrrkz 4819
-VPMOVDWZ 4820
-VPMOVDWZmr 4821
-VPMOVDWZmrk 4822
-VPMOVDWZrr 4823
-VPMOVDWZrrk 4824
-VPMOVDWZrrkz 4825
-VPMOVM 4826
-VPMOVMSKBYrr 4827
-VPMOVMSKBrr 4828
-VPMOVQ 4829
-VPMOVQBZ 4830
-VPMOVQBZmr 4831
-VPMOVQBZmrk 4832
-VPMOVQBZrr 4833
-VPMOVQBZrrk 4834
-VPMOVQBZrrkz 4835
-VPMOVQDZ 4836
-VPMOVQDZmr 4837
-VPMOVQDZmrk 4838
-VPMOVQDZrr 4839
-VPMOVQDZrrk 4840
-VPMOVQDZrrkz 4841
-VPMOVQWZ 4842
-VPMOVQWZmr 4843
-VPMOVQWZmrk 4844
-VPMOVQWZrr 4845
-VPMOVQWZrrk 4846
-VPMOVQWZrrkz 4847
-VPMOVSDBZ 4848
-VPMOVSDBZmr 4849
-VPMOVSDBZmrk 4850
-VPMOVSDBZrr 4851
-VPMOVSDBZrrk 4852
-VPMOVSDBZrrkz 4853
-VPMOVSDWZ 4854
-VPMOVSDWZmr 4855
-VPMOVSDWZmrk 4856
-VPMOVSDWZrr 4857
-VPMOVSDWZrrk 4858
-VPMOVSDWZrrkz 4859
-VPMOVSQBZ 4860
-VPMOVSQBZmr 4861
-VPMOVSQBZmrk 4862
-VPMOVSQBZrr 4863
-VPMOVSQBZrrk 4864
-VPMOVSQBZrrkz 4865
-VPMOVSQDZ 4866
-VPMOVSQDZmr 4867
-VPMOVSQDZmrk 4868
-VPMOVSQDZrr 4869
-VPMOVSQDZrrk 4870
-VPMOVSQDZrrkz 4871
-VPMOVSQWZ 4872
-VPMOVSQWZmr 4873
-VPMOVSQWZmrk 4874
-VPMOVSQWZrr 4875
-VPMOVSQWZrrk 4876
-VPMOVSQWZrrkz 4877
-VPMOVSWBZ 4878
-VPMOVSWBZmr 4879
-VPMOVSWBZmrk 4880
-VPMOVSWBZrr 4881
-VPMOVSWBZrrk 4882
-VPMOVSWBZrrkz 4883
-VPMOVSXBDYrm 4884
-VPMOVSXBDYrr 4885
-VPMOVSXBDZ 4886
-VPMOVSXBDZrm 4887
-VPMOVSXBDZrmk 4888
-VPMOVSXBDZrmkz 4889
-VPMOVSXBDZrr 4890
-VPMOVSXBDZrrk 4891
-VPMOVSXBDZrrkz 4892
-VPMOVSXBDrm 4893
-VPMOVSXBDrr 4894
-VPMOVSXBQYrm 4895
-VPMOVSXBQYrr 4896
-VPMOVSXBQZ 4897
-VPMOVSXBQZrm 4898
-VPMOVSXBQZrmk 4899
-VPMOVSXBQZrmkz 4900
-VPMOVSXBQZrr 4901
-VPMOVSXBQZrrk 4902
-VPMOVSXBQZrrkz 4903
-VPMOVSXBQrm 4904
-VPMOVSXBQrr 4905
-VPMOVSXBWYrm 4906
-VPMOVSXBWYrr 4907
-VPMOVSXBWZ 4908
-VPMOVSXBWZrm 4909
-VPMOVSXBWZrmk 4910
-VPMOVSXBWZrmkz 4911
-VPMOVSXBWZrr 4912
-VPMOVSXBWZrrk 4913
-VPMOVSXBWZrrkz 4914
-VPMOVSXBWrm 4915
-VPMOVSXBWrr 4916
-VPMOVSXDQYrm 4917
-VPMOVSXDQYrr 4918
-VPMOVSXDQZ 4919
-VPMOVSXDQZrm 4920
-VPMOVSXDQZrmk 4921
-VPMOVSXDQZrmkz 4922
-VPMOVSXDQZrr 4923
-VPMOVSXDQZrrk 4924
-VPMOVSXDQZrrkz 4925
-VPMOVSXDQrm 4926
-VPMOVSXDQrr 4927
-VPMOVSXWDYrm 4928
-VPMOVSXWDYrr 4929
-VPMOVSXWDZ 4930
-VPMOVSXWDZrm 4931
-VPMOVSXWDZrmk 4932
-VPMOVSXWDZrmkz 4933
-VPMOVSXWDZrr 4934
-VPMOVSXWDZrrk 4935
-VPMOVSXWDZrrkz 4936
-VPMOVSXWDrm 4937
-VPMOVSXWDrr 4938
-VPMOVSXWQYrm 4939
-VPMOVSXWQYrr 4940
-VPMOVSXWQZ 4941
-VPMOVSXWQZrm 4942
-VPMOVSXWQZrmk 4943
-VPMOVSXWQZrmkz 4944
-VPMOVSXWQZrr 4945
-VPMOVSXWQZrrk 4946
-VPMOVSXWQZrrkz 4947
-VPMOVSXWQrm 4948
-VPMOVSXWQrr 4949
-VPMOVUSDBZ 4950
-VPMOVUSDBZmr 4951
-VPMOVUSDBZmrk 4952
-VPMOVUSDBZrr 4953
-VPMOVUSDBZrrk 4954
-VPMOVUSDBZrrkz 4955
-VPMOVUSDWZ 4956
-VPMOVUSDWZmr 4957
-VPMOVUSDWZmrk 4958
-VPMOVUSDWZrr 4959
-VPMOVUSDWZrrk 4960
-VPMOVUSDWZrrkz 4961
-VPMOVUSQBZ 4962
-VPMOVUSQBZmr 4963
-VPMOVUSQBZmrk 4964
-VPMOVUSQBZrr 4965
-VPMOVUSQBZrrk 4966
-VPMOVUSQBZrrkz 4967
-VPMOVUSQDZ 4968
-VPMOVUSQDZmr 4969
-VPMOVUSQDZmrk 4970
-VPMOVUSQDZrr 4971
-VPMOVUSQDZrrk 4972
-VPMOVUSQDZrrkz 4973
-VPMOVUSQWZ 4974
-VPMOVUSQWZmr 4975
-VPMOVUSQWZmrk 4976
-VPMOVUSQWZrr 4977
-VPMOVUSQWZrrk 4978
-VPMOVUSQWZrrkz 4979
-VPMOVUSWBZ 4980
-VPMOVUSWBZmr 4981
-VPMOVUSWBZmrk 4982
-VPMOVUSWBZrr 4983
-VPMOVUSWBZrrk 4984
-VPMOVUSWBZrrkz 4985
-VPMOVW 4986
-VPMOVWBZ 4987
-VPMOVWBZmr 4988
-VPMOVWBZmrk 4989
-VPMOVWBZrr 4990
-VPMOVWBZrrk 4991
-VPMOVWBZrrkz 4992
-VPMOVZXBDYrm 4993
-VPMOVZXBDYrr 4994
-VPMOVZXBDZ 4995
-VPMOVZXBDZrm 4996
-VPMOVZXBDZrmk 4997
-VPMOVZXBDZrmkz 4998
-VPMOVZXBDZrr 4999
-VPMOVZXBDZrrk 5000
-VPMOVZXBDZrrkz 5001
-VPMOVZXBDrm 5002
-VPMOVZXBDrr 5003
-VPMOVZXBQYrm 5004
-VPMOVZXBQYrr 5005
-VPMOVZXBQZ 5006
-VPMOVZXBQZrm 5007
-VPMOVZXBQZrmk 5008
-VPMOVZXBQZrmkz 5009
-VPMOVZXBQZrr 5010
-VPMOVZXBQZrrk 5011
-VPMOVZXBQZrrkz 5012
-VPMOVZXBQrm 5013
-VPMOVZXBQrr 5014
-VPMOVZXBWYrm 5015
-VPMOVZXBWYrr 5016
-VPMOVZXBWZ 5017
-VPMOVZXBWZrm 5018
-VPMOVZXBWZrmk 5019
-VPMOVZXBWZrmkz 5020
-VPMOVZXBWZrr 5021
-VPMOVZXBWZrrk 5022
-VPMOVZXBWZrrkz 5023
-VPMOVZXBWrm 5024
-VPMOVZXBWrr 5025
-VPMOVZXDQYrm 5026
-VPMOVZXDQYrr 5027
-VPMOVZXDQZ 5028
-VPMOVZXDQZrm 5029
-VPMOVZXDQZrmk 5030
-VPMOVZXDQZrmkz 5031
-VPMOVZXDQZrr 5032
-VPMOVZXDQZrrk 5033
-VPMOVZXDQZrrkz 5034
-VPMOVZXDQrm 5035
-VPMOVZXDQrr 5036
-VPMOVZXWDYrm 5037
-VPMOVZXWDYrr 5038
-VPMOVZXWDZ 5039
-VPMOVZXWDZrm 5040
-VPMOVZXWDZrmk 5041
-VPMOVZXWDZrmkz 5042
-VPMOVZXWDZrr 5043
-VPMOVZXWDZrrk 5044
-VPMOVZXWDZrrkz 5045
-VPMOVZXWDrm 5046
-VPMOVZXWDrr 5047
-VPMOVZXWQYrm 5048
-VPMOVZXWQYrr 5049
-VPMOVZXWQZ 5050
-VPMOVZXWQZrm 5051
-VPMOVZXWQZrmk 5052
-VPMOVZXWQZrmkz 5053
-VPMOVZXWQZrr 5054
-VPMOVZXWQZrrk 5055
-VPMOVZXWQZrrkz 5056
-VPMOVZXWQrm 5057
-VPMOVZXWQrr 5058
-VPMULDQYrm 5059
-VPMULDQYrr 5060
-VPMULDQZ 5061
-VPMULDQZrm 5062
-VPMULDQZrmb 5063
-VPMULDQZrmbk 5064
-VPMULDQZrmbkz 5065
-VPMULDQZrmk 5066
-VPMULDQZrmkz 5067
-VPMULDQZrr 5068
-VPMULDQZrrk 5069
-VPMULDQZrrkz 5070
-VPMULDQrm 5071
-VPMULDQrr 5072
-VPMULHRSWYrm 5073
-VPMULHRSWYrr 5074
-VPMULHRSWZ 5075
-VPMULHRSWZrm 5076
-VPMULHRSWZrmk 5077
-VPMULHRSWZrmkz 5078
-VPMULHRSWZrr 5079
-VPMULHRSWZrrk 5080
-VPMULHRSWZrrkz 5081
-VPMULHRSWrm 5082
-VPMULHRSWrr 5083
-VPMULHUWYrm 5084
-VPMULHUWYrr 5085
-VPMULHUWZ 5086
-VPMULHUWZrm 5087
-VPMULHUWZrmk 5088
-VPMULHUWZrmkz 5089
-VPMULHUWZrr 5090
-VPMULHUWZrrk 5091
-VPMULHUWZrrkz 5092
-VPMULHUWrm 5093
-VPMULHUWrr 5094
-VPMULHWYrm 5095
-VPMULHWYrr 5096
-VPMULHWZ 5097
-VPMULHWZrm 5098
-VPMULHWZrmk 5099
-VPMULHWZrmkz 5100
-VPMULHWZrr 5101
-VPMULHWZrrk 5102
-VPMULHWZrrkz 5103
-VPMULHWrm 5104
-VPMULHWrr 5105
-VPMULLDYrm 5106
-VPMULLDYrr 5107
-VPMULLDZ 5108
-VPMULLDZrm 5109
-VPMULLDZrmb 5110
-VPMULLDZrmbk 5111
-VPMULLDZrmbkz 5112
-VPMULLDZrmk 5113
-VPMULLDZrmkz 5114
-VPMULLDZrr 5115
-VPMULLDZrrk 5116
-VPMULLDZrrkz 5117
-VPMULLDrm 5118
-VPMULLDrr 5119
-VPMULLQZ 5120
-VPMULLQZrm 5121
-VPMULLQZrmb 5122
-VPMULLQZrmbk 5123
-VPMULLQZrmbkz 5124
-VPMULLQZrmk 5125
-VPMULLQZrmkz 5126
-VPMULLQZrr 5127
-VPMULLQZrrk 5128
-VPMULLQZrrkz 5129
-VPMULLWYrm 5130
-VPMULLWYrr 5131
-VPMULLWZ 5132
-VPMULLWZrm 5133
-VPMULLWZrmk 5134
-VPMULLWZrmkz 5135
-VPMULLWZrr 5136
-VPMULLWZrrk 5137
-VPMULLWZrrkz 5138
-VPMULLWrm 5139
-VPMULLWrr 5140
-VPMULTISHIFTQBZ 5141
-VPMULTISHIFTQBZrm 5142
-VPMULTISHIFTQBZrmb 5143
-VPMULTISHIFTQBZrmbk 5144
-VPMULTISHIFTQBZrmbkz 5145
-VPMULTISHIFTQBZrmk 5146
-VPMULTISHIFTQBZrmkz 5147
-VPMULTISHIFTQBZrr 5148
-VPMULTISHIFTQBZrrk 5149
-VPMULTISHIFTQBZrrkz 5150
-VPMULUDQYrm 5151
-VPMULUDQYrr 5152
-VPMULUDQZ 5153
-VPMULUDQZrm 5154
-VPMULUDQZrmb 5155
-VPMULUDQZrmbk 5156
-VPMULUDQZrmbkz 5157
-VPMULUDQZrmk 5158
-VPMULUDQZrmkz 5159
-VPMULUDQZrr 5160
-VPMULUDQZrrk 5161
-VPMULUDQZrrkz 5162
-VPMULUDQrm 5163
-VPMULUDQrr 5164
-VPOPCNTBZ 5165
-VPOPCNTBZrm 5166
-VPOPCNTBZrmk 5167
-VPOPCNTBZrmkz 5168
-VPOPCNTBZrr 5169
-VPOPCNTBZrrk 5170
-VPOPCNTBZrrkz 5171
-VPOPCNTDZ 5172
-VPOPCNTDZrm 5173
-VPOPCNTDZrmb 5174
-VPOPCNTDZrmbk 5175
-VPOPCNTDZrmbkz 5176
-VPOPCNTDZrmk 5177
-VPOPCNTDZrmkz 5178
-VPOPCNTDZrr 5179
-VPOPCNTDZrrk 5180
-VPOPCNTDZrrkz 5181
-VPOPCNTQZ 5182
-VPOPCNTQZrm 5183
-VPOPCNTQZrmb 5184
-VPOPCNTQZrmbk 5185
-VPOPCNTQZrmbkz 5186
-VPOPCNTQZrmk 5187
-VPOPCNTQZrmkz 5188
-VPOPCNTQZrr 5189
-VPOPCNTQZrrk 5190
-VPOPCNTQZrrkz 5191
-VPOPCNTWZ 5192
-VPOPCNTWZrm 5193
-VPOPCNTWZrmk 5194
-VPOPCNTWZrmkz 5195
-VPOPCNTWZrr 5196
-VPOPCNTWZrrk 5197
-VPOPCNTWZrrkz 5198
-VPORDZ 5199
-VPORDZrm 5200
-VPORDZrmb 5201
-VPORDZrmbk 5202
-VPORDZrmbkz 5203
-VPORDZrmk 5204
-VPORDZrmkz 5205
-VPORDZrr 5206
-VPORDZrrk 5207
-VPORDZrrkz 5208
-VPORQZ 5209
-VPORQZrm 5210
-VPORQZrmb 5211
-VPORQZrmbk 5212
-VPORQZrmbkz 5213
-VPORQZrmk 5214
-VPORQZrmkz 5215
-VPORQZrr 5216
-VPORQZrrk 5217
-VPORQZrrkz 5218
-VPORYrm 5219
-VPORYrr 5220
-VPORrm 5221
-VPORrr 5222
-VPPERMrmr 5223
-VPPERMrrm 5224
-VPPERMrrr 5225
-VPPERMrrr_REV 5226
-VPROLDZ 5227
-VPROLDZmbi 5228
-VPROLDZmbik 5229
-VPROLDZmbikz 5230
-VPROLDZmi 5231
-VPROLDZmik 5232
-VPROLDZmikz 5233
-VPROLDZri 5234
-VPROLDZrik 5235
-VPROLDZrikz 5236
-VPROLQZ 5237
-VPROLQZmbi 5238
-VPROLQZmbik 5239
-VPROLQZmbikz 5240
-VPROLQZmi 5241
-VPROLQZmik 5242
-VPROLQZmikz 5243
-VPROLQZri 5244
-VPROLQZrik 5245
-VPROLQZrikz 5246
-VPROLVDZ 5247
-VPROLVDZrm 5248
-VPROLVDZrmb 5249
-VPROLVDZrmbk 5250
-VPROLVDZrmbkz 5251
-VPROLVDZrmk 5252
-VPROLVDZrmkz 5253
-VPROLVDZrr 5254
-VPROLVDZrrk 5255
-VPROLVDZrrkz 5256
-VPROLVQZ 5257
-VPROLVQZrm 5258
-VPROLVQZrmb 5259
-VPROLVQZrmbk 5260
-VPROLVQZrmbkz 5261
-VPROLVQZrmk 5262
-VPROLVQZrmkz 5263
-VPROLVQZrr 5264
-VPROLVQZrrk 5265
-VPROLVQZrrkz 5266
-VPRORDZ 5267
-VPRORDZmbi 5268
-VPRORDZmbik 5269
-VPRORDZmbikz 5270
-VPRORDZmi 5271
-VPRORDZmik 5272
-VPRORDZmikz 5273
-VPRORDZri 5274
-VPRORDZrik 5275
-VPRORDZrikz 5276
-VPRORQZ 5277
-VPRORQZmbi 5278
-VPRORQZmbik 5279
-VPRORQZmbikz 5280
-VPRORQZmi 5281
-VPRORQZmik 5282
-VPRORQZmikz 5283
-VPRORQZri 5284
-VPRORQZrik 5285
-VPRORQZrikz 5286
-VPRORVDZ 5287
-VPRORVDZrm 5288
-VPRORVDZrmb 5289
-VPRORVDZrmbk 5290
-VPRORVDZrmbkz 5291
-VPRORVDZrmk 5292
-VPRORVDZrmkz 5293
-VPRORVDZrr 5294
-VPRORVDZrrk 5295
-VPRORVDZrrkz 5296
-VPRORVQZ 5297
-VPRORVQZrm 5298
-VPRORVQZrmb 5299
-VPRORVQZrmbk 5300
-VPRORVQZrmbkz 5301
-VPRORVQZrmk 5302
-VPRORVQZrmkz 5303
-VPRORVQZrr 5304
-VPRORVQZrrk 5305
-VPRORVQZrrkz 5306
-VPROTBmi 5307
-VPROTBmr 5308
-VPROTBri 5309
-VPROTBrm 5310
-VPROTBrr 5311
-VPROTBrr_REV 5312
-VPROTDmi 5313
-VPROTDmr 5314
-VPROTDri 5315
-VPROTDrm 5316
-VPROTDrr 5317
-VPROTDrr_REV 5318
-VPROTQmi 5319
-VPROTQmr 5320
-VPROTQri 5321
-VPROTQrm 5322
-VPROTQrr 5323
-VPROTQrr_REV 5324
-VPROTWmi 5325
-VPROTWmr 5326
-VPROTWri 5327
-VPROTWrm 5328
-VPROTWrr 5329
-VPROTWrr_REV 5330
-VPSADBWYrm 5331
-VPSADBWYrr 5332
-VPSADBWZ 5333
-VPSADBWZrm 5334
-VPSADBWZrr 5335
-VPSADBWrm 5336
-VPSADBWrr 5337
-VPSCATTERDDZ 5338
-VPSCATTERDDZmr 5339
-VPSCATTERDQZ 5340
-VPSCATTERDQZmr 5341
-VPSCATTERQDZ 5342
-VPSCATTERQDZmr 5343
-VPSCATTERQQZ 5344
-VPSCATTERQQZmr 5345
-VPSHABmr 5346
-VPSHABrm 5347
-VPSHABrr 5348
-VPSHABrr_REV 5349
-VPSHADmr 5350
-VPSHADrm 5351
-VPSHADrr 5352
-VPSHADrr_REV 5353
-VPSHAQmr 5354
-VPSHAQrm 5355
-VPSHAQrr 5356
-VPSHAQrr_REV 5357
-VPSHAWmr 5358
-VPSHAWrm 5359
-VPSHAWrr 5360
-VPSHAWrr_REV 5361
-VPSHLBmr 5362
-VPSHLBrm 5363
-VPSHLBrr 5364
-VPSHLBrr_REV 5365
-VPSHLDDZ 5366
-VPSHLDDZrmbi 5367
-VPSHLDDZrmbik 5368
-VPSHLDDZrmbikz 5369
-VPSHLDDZrmi 5370
-VPSHLDDZrmik 5371
-VPSHLDDZrmikz 5372
-VPSHLDDZrri 5373
-VPSHLDDZrrik 5374
-VPSHLDDZrrikz 5375
-VPSHLDQZ 5376
-VPSHLDQZrmbi 5377
-VPSHLDQZrmbik 5378
-VPSHLDQZrmbikz 5379
-VPSHLDQZrmi 5380
-VPSHLDQZrmik 5381
-VPSHLDQZrmikz 5382
-VPSHLDQZrri 5383
-VPSHLDQZrrik 5384
-VPSHLDQZrrikz 5385
-VPSHLDVDZ 5386
-VPSHLDVDZm 5387
-VPSHLDVDZmb 5388
-VPSHLDVDZmbk 5389
-VPSHLDVDZmbkz 5390
-VPSHLDVDZmk 5391
-VPSHLDVDZmkz 5392
-VPSHLDVDZr 5393
-VPSHLDVDZrk 5394
-VPSHLDVDZrkz 5395
-VPSHLDVQZ 5396
-VPSHLDVQZm 5397
-VPSHLDVQZmb 5398
-VPSHLDVQZmbk 5399
-VPSHLDVQZmbkz 5400
-VPSHLDVQZmk 5401
-VPSHLDVQZmkz 5402
-VPSHLDVQZr 5403
-VPSHLDVQZrk 5404
-VPSHLDVQZrkz 5405
-VPSHLDVWZ 5406
-VPSHLDVWZm 5407
-VPSHLDVWZmk 5408
-VPSHLDVWZmkz 5409
-VPSHLDVWZr 5410
-VPSHLDVWZrk 5411
-VPSHLDVWZrkz 5412
-VPSHLDWZ 5413
-VPSHLDWZrmi 5414
-VPSHLDWZrmik 5415
-VPSHLDWZrmikz 5416
-VPSHLDWZrri 5417
-VPSHLDWZrrik 5418
-VPSHLDWZrrikz 5419
-VPSHLDmr 5420
-VPSHLDrm 5421
-VPSHLDrr 5422
-VPSHLDrr_REV 5423
-VPSHLQmr 5424
-VPSHLQrm 5425
-VPSHLQrr 5426
-VPSHLQrr_REV 5427
-VPSHLWmr 5428
-VPSHLWrm 5429
-VPSHLWrr 5430
-VPSHLWrr_REV 5431
-VPSHRDDZ 5432
-VPSHRDDZrmbi 5433
-VPSHRDDZrmbik 5434
-VPSHRDDZrmbikz 5435
-VPSHRDDZrmi 5436
-VPSHRDDZrmik 5437
-VPSHRDDZrmikz 5438
-VPSHRDDZrri 5439
-VPSHRDDZrrik 5440
-VPSHRDDZrrikz 5441
-VPSHRDQZ 5442
-VPSHRDQZrmbi 5443
-VPSHRDQZrmbik 5444
-VPSHRDQZrmbikz 5445
-VPSHRDQZrmi 5446
-VPSHRDQZrmik 5447
-VPSHRDQZrmikz 5448
-VPSHRDQZrri 5449
-VPSHRDQZrrik 5450
-VPSHRDQZrrikz 5451
-VPSHRDVDZ 5452
-VPSHRDVDZm 5453
-VPSHRDVDZmb 5454
-VPSHRDVDZmbk 5455
-VPSHRDVDZmbkz 5456
-VPSHRDVDZmk 5457
-VPSHRDVDZmkz 5458
-VPSHRDVDZr 5459
-VPSHRDVDZrk 5460
-VPSHRDVDZrkz 5461
-VPSHRDVQZ 5462
-VPSHRDVQZm 5463
-VPSHRDVQZmb 5464
-VPSHRDVQZmbk 5465
-VPSHRDVQZmbkz 5466
-VPSHRDVQZmk 5467
-VPSHRDVQZmkz 5468
-VPSHRDVQZr 5469
-VPSHRDVQZrk 5470
-VPSHRDVQZrkz 5471
-VPSHRDVWZ 5472
-VPSHRDVWZm 5473
-VPSHRDVWZmk 5474
-VPSHRDVWZmkz 5475
-VPSHRDVWZr 5476
-VPSHRDVWZrk 5477
-VPSHRDVWZrkz 5478
-VPSHRDWZ 5479
-VPSHRDWZrmi 5480
-VPSHRDWZrmik 5481
-VPSHRDWZrmikz 5482
-VPSHRDWZrri 5483
-VPSHRDWZrrik 5484
-VPSHRDWZrrikz 5485
-VPSHUFBITQMBZ 5486
-VPSHUFBITQMBZrm 5487
-VPSHUFBITQMBZrmk 5488
-VPSHUFBITQMBZrr 5489
-VPSHUFBITQMBZrrk 5490
-VPSHUFBYrm 5491
-VPSHUFBYrr 5492
-VPSHUFBZ 5493
-VPSHUFBZrm 5494
-VPSHUFBZrmk 5495
-VPSHUFBZrmkz 5496
-VPSHUFBZrr 5497
-VPSHUFBZrrk 5498
-VPSHUFBZrrkz 5499
-VPSHUFBrm 5500
-VPSHUFBrr 5501
-VPSHUFDYmi 5502
-VPSHUFDYri 5503
-VPSHUFDZ 5504
-VPSHUFDZmbi 5505
-VPSHUFDZmbik 5506
-VPSHUFDZmbikz 5507
-VPSHUFDZmi 5508
-VPSHUFDZmik 5509
-VPSHUFDZmikz 5510
-VPSHUFDZri 5511
-VPSHUFDZrik 5512
-VPSHUFDZrikz 5513
-VPSHUFDmi 5514
-VPSHUFDri 5515
-VPSHUFHWYmi 5516
-VPSHUFHWYri 5517
-VPSHUFHWZ 5518
-VPSHUFHWZmi 5519
-VPSHUFHWZmik 5520
-VPSHUFHWZmikz 5521
-VPSHUFHWZri 5522
-VPSHUFHWZrik 5523
-VPSHUFHWZrikz 5524
-VPSHUFHWmi 5525
-VPSHUFHWri 5526
-VPSHUFLWYmi 5527
-VPSHUFLWYri 5528
-VPSHUFLWZ 5529
-VPSHUFLWZmi 5530
-VPSHUFLWZmik 5531
-VPSHUFLWZmikz 5532
-VPSHUFLWZri 5533
-VPSHUFLWZrik 5534
-VPSHUFLWZrikz 5535
-VPSHUFLWmi 5536
-VPSHUFLWri 5537
-VPSIGNBYrm 5538
-VPSIGNBYrr 5539
-VPSIGNBrm 5540
-VPSIGNBrr 5541
-VPSIGNDYrm 5542
-VPSIGNDYrr 5543
-VPSIGNDrm 5544
-VPSIGNDrr 5545
-VPSIGNWYrm 5546
-VPSIGNWYrr 5547
-VPSIGNWrm 5548
-VPSIGNWrr 5549
-VPSLLDQYri 5550
-VPSLLDQZ 5551
-VPSLLDQZmi 5552
-VPSLLDQZri 5553
-VPSLLDQri 5554
-VPSLLDYri 5555
-VPSLLDYrm 5556
-VPSLLDYrr 5557
-VPSLLDZ 5558
-VPSLLDZmbi 5559
-VPSLLDZmbik 5560
-VPSLLDZmbikz 5561
-VPSLLDZmi 5562
-VPSLLDZmik 5563
-VPSLLDZmikz 5564
-VPSLLDZri 5565
-VPSLLDZrik 5566
-VPSLLDZrikz 5567
-VPSLLDZrm 5568
-VPSLLDZrmk 5569
-VPSLLDZrmkz 5570
-VPSLLDZrr 5571
-VPSLLDZrrk 5572
-VPSLLDZrrkz 5573
-VPSLLDri 5574
-VPSLLDrm 5575
-VPSLLDrr 5576
-VPSLLQYri 5577
-VPSLLQYrm 5578
-VPSLLQYrr 5579
-VPSLLQZ 5580
-VPSLLQZmbi 5581
-VPSLLQZmbik 5582
-VPSLLQZmbikz 5583
-VPSLLQZmi 5584
-VPSLLQZmik 5585
-VPSLLQZmikz 5586
-VPSLLQZri 5587
-VPSLLQZrik 5588
-VPSLLQZrikz 5589
-VPSLLQZrm 5590
-VPSLLQZrmk 5591
-VPSLLQZrmkz 5592
-VPSLLQZrr 5593
-VPSLLQZrrk 5594
-VPSLLQZrrkz 5595
-VPSLLQri 5596
-VPSLLQrm 5597
-VPSLLQrr 5598
-VPSLLVDYrm 5599
-VPSLLVDYrr 5600
-VPSLLVDZ 5601
-VPSLLVDZrm 5602
-VPSLLVDZrmb 5603
-VPSLLVDZrmbk 5604
-VPSLLVDZrmbkz 5605
-VPSLLVDZrmk 5606
-VPSLLVDZrmkz 5607
-VPSLLVDZrr 5608
-VPSLLVDZrrk 5609
-VPSLLVDZrrkz 5610
-VPSLLVDrm 5611
-VPSLLVDrr 5612
-VPSLLVQYrm 5613
-VPSLLVQYrr 5614
-VPSLLVQZ 5615
-VPSLLVQZrm 5616
-VPSLLVQZrmb 5617
-VPSLLVQZrmbk 5618
-VPSLLVQZrmbkz 5619
-VPSLLVQZrmk 5620
-VPSLLVQZrmkz 5621
-VPSLLVQZrr 5622
-VPSLLVQZrrk 5623
-VPSLLVQZrrkz 5624
-VPSLLVQrm 5625
-VPSLLVQrr 5626
-VPSLLVWZ 5627
-VPSLLVWZrm 5628
-VPSLLVWZrmk 5629
-VPSLLVWZrmkz 5630
-VPSLLVWZrr 5631
-VPSLLVWZrrk 5632
-VPSLLVWZrrkz 5633
-VPSLLWYri 5634
-VPSLLWYrm 5635
-VPSLLWYrr 5636
-VPSLLWZ 5637
-VPSLLWZmi 5638
-VPSLLWZmik 5639
-VPSLLWZmikz 5640
-VPSLLWZri 5641
-VPSLLWZrik 5642
-VPSLLWZrikz 5643
-VPSLLWZrm 5644
-VPSLLWZrmk 5645
-VPSLLWZrmkz 5646
-VPSLLWZrr 5647
-VPSLLWZrrk 5648
-VPSLLWZrrkz 5649
-VPSLLWri 5650
-VPSLLWrm 5651
-VPSLLWrr 5652
-VPSRADYri 5653
-VPSRADYrm 5654
-VPSRADYrr 5655
-VPSRADZ 5656
-VPSRADZmbi 5657
-VPSRADZmbik 5658
-VPSRADZmbikz 5659
-VPSRADZmi 5660
-VPSRADZmik 5661
-VPSRADZmikz 5662
-VPSRADZri 5663
-VPSRADZrik 5664
-VPSRADZrikz 5665
-VPSRADZrm 5666
-VPSRADZrmk 5667
-VPSRADZrmkz 5668
-VPSRADZrr 5669
-VPSRADZrrk 5670
-VPSRADZrrkz 5671
-VPSRADri 5672
-VPSRADrm 5673
-VPSRADrr 5674
-VPSRAQZ 5675
-VPSRAQZmbi 5676
-VPSRAQZmbik 5677
-VPSRAQZmbikz 5678
-VPSRAQZmi 5679
-VPSRAQZmik 5680
-VPSRAQZmikz 5681
-VPSRAQZri 5682
-VPSRAQZrik 5683
-VPSRAQZrikz 5684
-VPSRAQZrm 5685
-VPSRAQZrmk 5686
-VPSRAQZrmkz 5687
-VPSRAQZrr 5688
-VPSRAQZrrk 5689
-VPSRAQZrrkz 5690
-VPSRAVDYrm 5691
-VPSRAVDYrr 5692
-VPSRAVDZ 5693
-VPSRAVDZrm 5694
-VPSRAVDZrmb 5695
-VPSRAVDZrmbk 5696
-VPSRAVDZrmbkz 5697
-VPSRAVDZrmk 5698
-VPSRAVDZrmkz 5699
-VPSRAVDZrr 5700
-VPSRAVDZrrk 5701
-VPSRAVDZrrkz 5702
-VPSRAVDrm 5703
-VPSRAVDrr 5704
-VPSRAVQZ 5705
-VPSRAVQZrm 5706
-VPSRAVQZrmb 5707
-VPSRAVQZrmbk 5708
-VPSRAVQZrmbkz 5709
-VPSRAVQZrmk 5710
-VPSRAVQZrmkz 5711
-VPSRAVQZrr 5712
-VPSRAVQZrrk 5713
-VPSRAVQZrrkz 5714
-VPSRAVWZ 5715
-VPSRAVWZrm 5716
-VPSRAVWZrmk 5717
-VPSRAVWZrmkz 5718
-VPSRAVWZrr 5719
-VPSRAVWZrrk 5720
-VPSRAVWZrrkz 5721
-VPSRAWYri 5722
-VPSRAWYrm 5723
-VPSRAWYrr 5724
-VPSRAWZ 5725
-VPSRAWZmi 5726
-VPSRAWZmik 5727
-VPSRAWZmikz 5728
-VPSRAWZri 5729
-VPSRAWZrik 5730
-VPSRAWZrikz 5731
-VPSRAWZrm 5732
-VPSRAWZrmk 5733
-VPSRAWZrmkz 5734
-VPSRAWZrr 5735
-VPSRAWZrrk 5736
-VPSRAWZrrkz 5737
-VPSRAWri 5738
-VPSRAWrm 5739
-VPSRAWrr 5740
-VPSRLDQYri 5741
-VPSRLDQZ 5742
-VPSRLDQZmi 5743
-VPSRLDQZri 5744
-VPSRLDQri 5745
-VPSRLDYri 5746
-VPSRLDYrm 5747
-VPSRLDYrr 5748
-VPSRLDZ 5749
-VPSRLDZmbi 5750
-VPSRLDZmbik 5751
-VPSRLDZmbikz 5752
-VPSRLDZmi 5753
-VPSRLDZmik 5754
-VPSRLDZmikz 5755
-VPSRLDZri 5756
-VPSRLDZrik 5757
-VPSRLDZrikz 5758
-VPSRLDZrm 5759
-VPSRLDZrmk 5760
-VPSRLDZrmkz 5761
-VPSRLDZrr 5762
-VPSRLDZrrk 5763
-VPSRLDZrrkz 5764
-VPSRLDri 5765
-VPSRLDrm 5766
-VPSRLDrr 5767
-VPSRLQYri 5768
-VPSRLQYrm 5769
-VPSRLQYrr 5770
-VPSRLQZ 5771
-VPSRLQZmbi 5772
-VPSRLQZmbik 5773
-VPSRLQZmbikz 5774
-VPSRLQZmi 5775
-VPSRLQZmik 5776
-VPSRLQZmikz 5777
-VPSRLQZri 5778
-VPSRLQZrik 5779
-VPSRLQZrikz 5780
-VPSRLQZrm 5781
-VPSRLQZrmk 5782
-VPSRLQZrmkz 5783
-VPSRLQZrr 5784
-VPSRLQZrrk 5785
-VPSRLQZrrkz 5786
-VPSRLQri 5787
-VPSRLQrm 5788
-VPSRLQrr 5789
-VPSRLVDYrm 5790
-VPSRLVDYrr 5791
-VPSRLVDZ 5792
-VPSRLVDZrm 5793
-VPSRLVDZrmb 5794
-VPSRLVDZrmbk 5795
-VPSRLVDZrmbkz 5796
-VPSRLVDZrmk 5797
-VPSRLVDZrmkz 5798
-VPSRLVDZrr 5799
-VPSRLVDZrrk 5800
-VPSRLVDZrrkz 5801
-VPSRLVDrm 5802
-VPSRLVDrr 5803
-VPSRLVQYrm 5804
-VPSRLVQYrr 5805
-VPSRLVQZ 5806
-VPSRLVQZrm 5807
-VPSRLVQZrmb 5808
-VPSRLVQZrmbk 5809
-VPSRLVQZrmbkz 5810
-VPSRLVQZrmk 5811
-VPSRLVQZrmkz 5812
-VPSRLVQZrr 5813
-VPSRLVQZrrk 5814
-VPSRLVQZrrkz 5815
-VPSRLVQrm 5816
-VPSRLVQrr 5817
-VPSRLVWZ 5818
-VPSRLVWZrm 5819
-VPSRLVWZrmk 5820
-VPSRLVWZrmkz 5821
-VPSRLVWZrr 5822
-VPSRLVWZrrk 5823
-VPSRLVWZrrkz 5824
-VPSRLWYri 5825
-VPSRLWYrm 5826
-VPSRLWYrr 5827
-VPSRLWZ 5828
-VPSRLWZmi 5829
-VPSRLWZmik 5830
-VPSRLWZmikz 5831
-VPSRLWZri 5832
-VPSRLWZrik 5833
-VPSRLWZrikz 5834
-VPSRLWZrm 5835
-VPSRLWZrmk 5836
-VPSRLWZrmkz 5837
-VPSRLWZrr 5838
-VPSRLWZrrk 5839
-VPSRLWZrrkz 5840
-VPSRLWri 5841
-VPSRLWrm 5842
-VPSRLWrr 5843
-VPSUBBYrm 5844
-VPSUBBYrr 5845
-VPSUBBZ 5846
-VPSUBBZrm 5847
-VPSUBBZrmk 5848
-VPSUBBZrmkz 5849
-VPSUBBZrr 5850
-VPSUBBZrrk 5851
-VPSUBBZrrkz 5852
-VPSUBBrm 5853
-VPSUBBrr 5854
-VPSUBDYrm 5855
-VPSUBDYrr 5856
-VPSUBDZ 5857
-VPSUBDZrm 5858
-VPSUBDZrmb 5859
-VPSUBDZrmbk 5860
-VPSUBDZrmbkz 5861
-VPSUBDZrmk 5862
-VPSUBDZrmkz 5863
-VPSUBDZrr 5864
-VPSUBDZrrk 5865
-VPSUBDZrrkz 5866
-VPSUBDrm 5867
-VPSUBDrr 5868
-VPSUBQYrm 5869
-VPSUBQYrr 5870
-VPSUBQZ 5871
-VPSUBQZrm 5872
-VPSUBQZrmb 5873
-VPSUBQZrmbk 5874
-VPSUBQZrmbkz 5875
-VPSUBQZrmk 5876
-VPSUBQZrmkz 5877
-VPSUBQZrr 5878
-VPSUBQZrrk 5879
-VPSUBQZrrkz 5880
-VPSUBQrm 5881
-VPSUBQrr 5882
-VPSUBSBYrm 5883
-VPSUBSBYrr 5884
-VPSUBSBZ 5885
-VPSUBSBZrm 5886
-VPSUBSBZrmk 5887
-VPSUBSBZrmkz 5888
-VPSUBSBZrr 5889
-VPSUBSBZrrk 5890
-VPSUBSBZrrkz 5891
-VPSUBSBrm 5892
-VPSUBSBrr 5893
-VPSUBSWYrm 5894
-VPSUBSWYrr 5895
-VPSUBSWZ 5896
-VPSUBSWZrm 5897
-VPSUBSWZrmk 5898
-VPSUBSWZrmkz 5899
-VPSUBSWZrr 5900
-VPSUBSWZrrk 5901
-VPSUBSWZrrkz 5902
-VPSUBSWrm 5903
-VPSUBSWrr 5904
-VPSUBUSBYrm 5905
-VPSUBUSBYrr 5906
-VPSUBUSBZ 5907
-VPSUBUSBZrm 5908
-VPSUBUSBZrmk 5909
-VPSUBUSBZrmkz 5910
-VPSUBUSBZrr 5911
-VPSUBUSBZrrk 5912
-VPSUBUSBZrrkz 5913
-VPSUBUSBrm 5914
-VPSUBUSBrr 5915
-VPSUBUSWYrm 5916
-VPSUBUSWYrr 5917
-VPSUBUSWZ 5918
-VPSUBUSWZrm 5919
-VPSUBUSWZrmk 5920
-VPSUBUSWZrmkz 5921
-VPSUBUSWZrr 5922
-VPSUBUSWZrrk 5923
-VPSUBUSWZrrkz 5924
-VPSUBUSWrm 5925
-VPSUBUSWrr 5926
-VPSUBWYrm 5927
-VPSUBWYrr 5928
-VPSUBWZ 5929
-VPSUBWZrm 5930
-VPSUBWZrmk 5931
-VPSUBWZrmkz 5932
-VPSUBWZrr 5933
-VPSUBWZrrk 5934
-VPSUBWZrrkz 5935
-VPSUBWrm 5936
-VPSUBWrr 5937
-VPTERNLOGDZ 5938
-VPTERNLOGDZrmbi 5939
-VPTERNLOGDZrmbik 5940
-VPTERNLOGDZrmbikz 5941
-VPTERNLOGDZrmi 5942
-VPTERNLOGDZrmik 5943
-VPTERNLOGDZrmikz 5944
-VPTERNLOGDZrri 5945
-VPTERNLOGDZrrik 5946
-VPTERNLOGDZrrikz 5947
-VPTERNLOGQZ 5948
-VPTERNLOGQZrmbi 5949
-VPTERNLOGQZrmbik 5950
-VPTERNLOGQZrmbikz 5951
-VPTERNLOGQZrmi 5952
-VPTERNLOGQZrmik 5953
-VPTERNLOGQZrmikz 5954
-VPTERNLOGQZrri 5955
-VPTERNLOGQZrrik 5956
-VPTERNLOGQZrrikz 5957
-VPTESTMBZ 5958
-VPTESTMBZrm 5959
-VPTESTMBZrmk 5960
-VPTESTMBZrr 5961
-VPTESTMBZrrk 5962
-VPTESTMDZ 5963
-VPTESTMDZrm 5964
-VPTESTMDZrmb 5965
-VPTESTMDZrmbk 5966
-VPTESTMDZrmk 5967
-VPTESTMDZrr 5968
-VPTESTMDZrrk 5969
-VPTESTMQZ 5970
-VPTESTMQZrm 5971
-VPTESTMQZrmb 5972
-VPTESTMQZrmbk 5973
-VPTESTMQZrmk 5974
-VPTESTMQZrr 5975
-VPTESTMQZrrk 5976
-VPTESTMWZ 5977
-VPTESTMWZrm 5978
-VPTESTMWZrmk 5979
-VPTESTMWZrr 5980
-VPTESTMWZrrk 5981
-VPTESTNMBZ 5982
-VPTESTNMBZrm 5983
-VPTESTNMBZrmk 5984
-VPTESTNMBZrr 5985
-VPTESTNMBZrrk 5986
-VPTESTNMDZ 5987
-VPTESTNMDZrm 5988
-VPTESTNMDZrmb 5989
-VPTESTNMDZrmbk 5990
-VPTESTNMDZrmk 5991
-VPTESTNMDZrr 5992
-VPTESTNMDZrrk 5993
-VPTESTNMQZ 5994
-VPTESTNMQZrm 5995
-VPTESTNMQZrmb 5996
-VPTESTNMQZrmbk 5997
-VPTESTNMQZrmk 5998
-VPTESTNMQZrr 5999
-VPTESTNMQZrrk 6000
-VPTESTNMWZ 6001
-VPTESTNMWZrm 6002
-VPTESTNMWZrmk 6003
-VPTESTNMWZrr 6004
-VPTESTNMWZrrk 6005
-VPTESTYrm 6006
-VPTESTYrr 6007
-VPTESTrm 6008
-VPTESTrr 6009
-VPUNPCKHBWYrm 6010
-VPUNPCKHBWYrr 6011
-VPUNPCKHBWZ 6012
-VPUNPCKHBWZrm 6013
-VPUNPCKHBWZrmk 6014
-VPUNPCKHBWZrmkz 6015
-VPUNPCKHBWZrr 6016
-VPUNPCKHBWZrrk 6017
-VPUNPCKHBWZrrkz 6018
-VPUNPCKHBWrm 6019
-VPUNPCKHBWrr 6020
-VPUNPCKHDQYrm 6021
-VPUNPCKHDQYrr 6022
-VPUNPCKHDQZ 6023
-VPUNPCKHDQZrm 6024
-VPUNPCKHDQZrmb 6025
-VPUNPCKHDQZrmbk 6026
-VPUNPCKHDQZrmbkz 6027
-VPUNPCKHDQZrmk 6028
-VPUNPCKHDQZrmkz 6029
-VPUNPCKHDQZrr 6030
-VPUNPCKHDQZrrk 6031
-VPUNPCKHDQZrrkz 6032
-VPUNPCKHDQrm 6033
-VPUNPCKHDQrr 6034
-VPUNPCKHQDQYrm 6035
-VPUNPCKHQDQYrr 6036
-VPUNPCKHQDQZ 6037
-VPUNPCKHQDQZrm 6038
-VPUNPCKHQDQZrmb 6039
-VPUNPCKHQDQZrmbk 6040
-VPUNPCKHQDQZrmbkz 6041
-VPUNPCKHQDQZrmk 6042
-VPUNPCKHQDQZrmkz 6043
-VPUNPCKHQDQZrr 6044
-VPUNPCKHQDQZrrk 6045
-VPUNPCKHQDQZrrkz 6046
-VPUNPCKHQDQrm 6047
-VPUNPCKHQDQrr 6048
-VPUNPCKHWDYrm 6049
-VPUNPCKHWDYrr 6050
-VPUNPCKHWDZ 6051
-VPUNPCKHWDZrm 6052
-VPUNPCKHWDZrmk 6053
-VPUNPCKHWDZrmkz 6054
-VPUNPCKHWDZrr 6055
-VPUNPCKHWDZrrk 6056
-VPUNPCKHWDZrrkz 6057
-VPUNPCKHWDrm 6058
-VPUNPCKHWDrr 6059
-VPUNPCKLBWYrm 6060
-VPUNPCKLBWYrr 6061
-VPUNPCKLBWZ 6062
-VPUNPCKLBWZrm 6063
-VPUNPCKLBWZrmk 6064
-VPUNPCKLBWZrmkz 6065
-VPUNPCKLBWZrr 6066
-VPUNPCKLBWZrrk 6067
-VPUNPCKLBWZrrkz 6068
-VPUNPCKLBWrm 6069
-VPUNPCKLBWrr 6070
-VPUNPCKLDQYrm 6071
-VPUNPCKLDQYrr 6072
-VPUNPCKLDQZ 6073
-VPUNPCKLDQZrm 6074
-VPUNPCKLDQZrmb 6075
-VPUNPCKLDQZrmbk 6076
-VPUNPCKLDQZrmbkz 6077
-VPUNPCKLDQZrmk 6078
-VPUNPCKLDQZrmkz 6079
-VPUNPCKLDQZrr 6080
-VPUNPCKLDQZrrk 6081
-VPUNPCKLDQZrrkz 6082
-VPUNPCKLDQrm 6083
-VPUNPCKLDQrr 6084
-VPUNPCKLQDQYrm 6085
-VPUNPCKLQDQYrr 6086
-VPUNPCKLQDQZ 6087
-VPUNPCKLQDQZrm 6088
-VPUNPCKLQDQZrmb 6089
-VPUNPCKLQDQZrmbk 6090
-VPUNPCKLQDQZrmbkz 6091
-VPUNPCKLQDQZrmk 6092
-VPUNPCKLQDQZrmkz 6093
-VPUNPCKLQDQZrr 6094
-VPUNPCKLQDQZrrk 6095
-VPUNPCKLQDQZrrkz 6096
-VPUNPCKLQDQrm 6097
-VPUNPCKLQDQrr 6098
-VPUNPCKLWDYrm 6099
-VPUNPCKLWDYrr 6100
-VPUNPCKLWDZ 6101
-VPUNPCKLWDZrm 6102
-VPUNPCKLWDZrmk 6103
-VPUNPCKLWDZrmkz 6104
-VPUNPCKLWDZrr 6105
-VPUNPCKLWDZrrk 6106
-VPUNPCKLWDZrrkz 6107
-VPUNPCKLWDrm 6108
-VPUNPCKLWDrr 6109
-VPXORDZ 6110
-VPXORDZrm 6111
-VPXORDZrmb 6112
-VPXORDZrmbk 6113
-VPXORDZrmbkz 6114
-VPXORDZrmk 6115
-VPXORDZrmkz 6116
-VPXORDZrr 6117
-VPXORDZrrk 6118
-VPXORDZrrkz 6119
-VPXORQZ 6120
-VPXORQZrm 6121
-VPXORQZrmb 6122
-VPXORQZrmbk 6123
-VPXORQZrmbkz 6124
-VPXORQZrmk 6125
-VPXORQZrmkz 6126
-VPXORQZrr 6127
-VPXORQZrrk 6128
-VPXORQZrrkz 6129
-VPXORYrm 6130
-VPXORYrr 6131
-VPXORrm 6132
-VPXORrr 6133
-VRANGEPDZ 6134
-VRANGEPDZrmbi 6135
-VRANGEPDZrmbik 6136
-VRANGEPDZrmbikz 6137
-VRANGEPDZrmi 6138
-VRANGEPDZrmik 6139
-VRANGEPDZrmikz 6140
-VRANGEPDZrri 6141
-VRANGEPDZrrib 6142
-VRANGEPDZrribk 6143
-VRANGEPDZrribkz 6144
-VRANGEPDZrrik 6145
-VRANGEPDZrrikz 6146
-VRANGEPSZ 6147
-VRANGEPSZrmbi 6148
-VRANGEPSZrmbik 6149
-VRANGEPSZrmbikz 6150
-VRANGEPSZrmi 6151
-VRANGEPSZrmik 6152
-VRANGEPSZrmikz 6153
-VRANGEPSZrri 6154
-VRANGEPSZrrib 6155
-VRANGEPSZrribk 6156
-VRANGEPSZrribkz 6157
-VRANGEPSZrrik 6158
-VRANGEPSZrrikz 6159
-VRANGESDZrmi 6160
-VRANGESDZrmik 6161
-VRANGESDZrmikz 6162
-VRANGESDZrri 6163
-VRANGESDZrrib 6164
-VRANGESDZrribk 6165
-VRANGESDZrribkz 6166
-VRANGESDZrrik 6167
-VRANGESDZrrikz 6168
-VRANGESSZrmi 6169
-VRANGESSZrmik 6170
-VRANGESSZrmikz 6171
-VRANGESSZrri 6172
-VRANGESSZrrib 6173
-VRANGESSZrribk 6174
-VRANGESSZrribkz 6175
-VRANGESSZrrik 6176
-VRANGESSZrrikz 6177
-VRCP 6178
-VRCPBF 6179
-VRCPPHZ 6180
-VRCPPHZm 6181
-VRCPPHZmb 6182
-VRCPPHZmbk 6183
-VRCPPHZmbkz 6184
-VRCPPHZmk 6185
-VRCPPHZmkz 6186
-VRCPPHZr 6187
-VRCPPHZrk 6188
-VRCPPHZrkz 6189
-VRCPPSYm 6190
-VRCPPSYr 6191
-VRCPPSm 6192
-VRCPPSr 6193
-VRCPSHZrm 6194
-VRCPSHZrmk 6195
-VRCPSHZrmkz 6196
-VRCPSHZrr 6197
-VRCPSHZrrk 6198
-VRCPSHZrrkz 6199
-VRCPSSm 6200
-VRCPSSm_Int 6201
-VRCPSSr 6202
-VRCPSSr_Int 6203
-VREDUCEBF 6204
-VREDUCEPDZ 6205
-VREDUCEPDZrmbi 6206
-VREDUCEPDZrmbik 6207
-VREDUCEPDZrmbikz 6208
-VREDUCEPDZrmi 6209
-VREDUCEPDZrmik 6210
-VREDUCEPDZrmikz 6211
-VREDUCEPDZrri 6212
-VREDUCEPDZrrib 6213
-VREDUCEPDZrribk 6214
-VREDUCEPDZrribkz 6215
-VREDUCEPDZrrik 6216
-VREDUCEPDZrrikz 6217
-VREDUCEPHZ 6218
-VREDUCEPHZrmbi 6219
-VREDUCEPHZrmbik 6220
-VREDUCEPHZrmbikz 6221
-VREDUCEPHZrmi 6222
-VREDUCEPHZrmik 6223
-VREDUCEPHZrmikz 6224
-VREDUCEPHZrri 6225
-VREDUCEPHZrrib 6226
-VREDUCEPHZrribk 6227
-VREDUCEPHZrribkz 6228
-VREDUCEPHZrrik 6229
-VREDUCEPHZrrikz 6230
-VREDUCEPSZ 6231
-VREDUCEPSZrmbi 6232
-VREDUCEPSZrmbik 6233
-VREDUCEPSZrmbikz 6234
-VREDUCEPSZrmi 6235
-VREDUCEPSZrmik 6236
-VREDUCEPSZrmikz 6237
-VREDUCEPSZrri 6238
-VREDUCEPSZrrib 6239
-VREDUCEPSZrribk 6240
-VREDUCEPSZrribkz 6241
-VREDUCEPSZrrik 6242
-VREDUCEPSZrrikz 6243
-VREDUCESDZrmi 6244
-VREDUCESDZrmik 6245
-VREDUCESDZrmikz 6246
-VREDUCESDZrri 6247
-VREDUCESDZrrib 6248
-VREDUCESDZrribk 6249
-VREDUCESDZrribkz 6250
-VREDUCESDZrrik 6251
-VREDUCESDZrrikz 6252
-VREDUCESHZrmi 6253
-VREDUCESHZrmik 6254
-VREDUCESHZrmikz 6255
-VREDUCESHZrri 6256
-VREDUCESHZrrib 6257
-VREDUCESHZrribk 6258
-VREDUCESHZrribkz 6259
-VREDUCESHZrrik 6260
-VREDUCESHZrrikz 6261
-VREDUCESSZrmi 6262
-VREDUCESSZrmik 6263
-VREDUCESSZrmikz 6264
-VREDUCESSZrri 6265
-VREDUCESSZrrib 6266
-VREDUCESSZrribk 6267
-VREDUCESSZrribkz 6268
-VREDUCESSZrrik 6269
-VREDUCESSZrrikz 6270
-VRNDSCALEBF 6271
-VRNDSCALEPDZ 6272
-VRNDSCALEPDZrmbi 6273
-VRNDSCALEPDZrmbik 6274
-VRNDSCALEPDZrmbikz 6275
-VRNDSCALEPDZrmi 6276
-VRNDSCALEPDZrmik 6277
-VRNDSCALEPDZrmikz 6278
-VRNDSCALEPDZrri 6279
-VRNDSCALEPDZrrib 6280
-VRNDSCALEPDZrribk 6281
-VRNDSCALEPDZrribkz 6282
-VRNDSCALEPDZrrik 6283
-VRNDSCALEPDZrrikz 6284
-VRNDSCALEPHZ 6285
-VRNDSCALEPHZrmbi 6286
-VRNDSCALEPHZrmbik 6287
-VRNDSCALEPHZrmbikz 6288
-VRNDSCALEPHZrmi 6289
-VRNDSCALEPHZrmik 6290
-VRNDSCALEPHZrmikz 6291
-VRNDSCALEPHZrri 6292
-VRNDSCALEPHZrrib 6293
-VRNDSCALEPHZrribk 6294
-VRNDSCALEPHZrribkz 6295
-VRNDSCALEPHZrrik 6296
-VRNDSCALEPHZrrikz 6297
-VRNDSCALEPSZ 6298
-VRNDSCALEPSZrmbi 6299
-VRNDSCALEPSZrmbik 6300
-VRNDSCALEPSZrmbikz 6301
-VRNDSCALEPSZrmi 6302
-VRNDSCALEPSZrmik 6303
-VRNDSCALEPSZrmikz 6304
-VRNDSCALEPSZrri 6305
-VRNDSCALEPSZrrib 6306
-VRNDSCALEPSZrribk 6307
-VRNDSCALEPSZrribkz 6308
-VRNDSCALEPSZrrik 6309
-VRNDSCALEPSZrrikz 6310
-VRNDSCALESDZrmi 6311
-VRNDSCALESDZrmi_Int 6312
-VRNDSCALESDZrmik_Int 6313
-VRNDSCALESDZrmikz_Int 6314
-VRNDSCALESDZrri 6315
-VRNDSCALESDZrri_Int 6316
-VRNDSCALESDZrrib_Int 6317
-VRNDSCALESDZrribk_Int 6318
-VRNDSCALESDZrribkz_Int 6319
-VRNDSCALESDZrrik_Int 6320
-VRNDSCALESDZrrikz_Int 6321
-VRNDSCALESHZrmi 6322
-VRNDSCALESHZrmi_Int 6323
-VRNDSCALESHZrmik_Int 6324
-VRNDSCALESHZrmikz_Int 6325
-VRNDSCALESHZrri 6326
-VRNDSCALESHZrri_Int 6327
-VRNDSCALESHZrrib_Int 6328
-VRNDSCALESHZrribk_Int 6329
-VRNDSCALESHZrribkz_Int 6330
-VRNDSCALESHZrrik_Int 6331
-VRNDSCALESHZrrikz_Int 6332
-VRNDSCALESSZrmi 6333
-VRNDSCALESSZrmi_Int 6334
-VRNDSCALESSZrmik_Int 6335
-VRNDSCALESSZrmikz_Int 6336
-VRNDSCALESSZrri 6337
-VRNDSCALESSZrri_Int 6338
-VRNDSCALESSZrrib_Int 6339
-VRNDSCALESSZrribk_Int 6340
-VRNDSCALESSZrribkz_Int 6341
-VRNDSCALESSZrrik_Int 6342
-VRNDSCALESSZrrikz_Int 6343
-VROUNDPDYmi 6344
-VROUNDPDYri 6345
-VROUNDPDmi 6346
-VROUNDPDri 6347
-VROUNDPSYmi 6348
-VROUNDPSYri 6349
-VROUNDPSmi 6350
-VROUNDPSri 6351
-VROUNDSDmi 6352
-VROUNDSDmi_Int 6353
-VROUNDSDri 6354
-VROUNDSDri_Int 6355
-VROUNDSSmi 6356
-VROUNDSSmi_Int 6357
-VROUNDSSri 6358
-VROUNDSSri_Int 6359
-VRSQRT 6360
-VRSQRTBF 6361
-VRSQRTPHZ 6362
-VRSQRTPHZm 6363
-VRSQRTPHZmb 6364
-VRSQRTPHZmbk 6365
-VRSQRTPHZmbkz 6366
-VRSQRTPHZmk 6367
-VRSQRTPHZmkz 6368
-VRSQRTPHZr 6369
-VRSQRTPHZrk 6370
-VRSQRTPHZrkz 6371
-VRSQRTPSYm 6372
-VRSQRTPSYr 6373
-VRSQRTPSm 6374
-VRSQRTPSr 6375
-VRSQRTSHZrm 6376
-VRSQRTSHZrmk 6377
-VRSQRTSHZrmkz 6378
-VRSQRTSHZrr 6379
-VRSQRTSHZrrk 6380
-VRSQRTSHZrrkz 6381
-VRSQRTSSm 6382
-VRSQRTSSm_Int 6383
-VRSQRTSSr 6384
-VRSQRTSSr_Int 6385
-VSCALEFBF 6386
-VSCALEFPDZ 6387
-VSCALEFPDZrm 6388
-VSCALEFPDZrmb 6389
-VSCALEFPDZrmbk 6390
-VSCALEFPDZrmbkz 6391
-VSCALEFPDZrmk 6392
-VSCALEFPDZrmkz 6393
-VSCALEFPDZrr 6394
-VSCALEFPDZrrb 6395
-VSCALEFPDZrrbk 6396
-VSCALEFPDZrrbkz 6397
-VSCALEFPDZrrk 6398
-VSCALEFPDZrrkz 6399
-VSCALEFPHZ 6400
-VSCALEFPHZrm 6401
-VSCALEFPHZrmb 6402
-VSCALEFPHZrmbk 6403
-VSCALEFPHZrmbkz 6404
-VSCALEFPHZrmk 6405
-VSCALEFPHZrmkz 6406
-VSCALEFPHZrr 6407
-VSCALEFPHZrrb 6408
-VSCALEFPHZrrbk 6409
-VSCALEFPHZrrbkz 6410
-VSCALEFPHZrrk 6411
-VSCALEFPHZrrkz 6412
-VSCALEFPSZ 6413
-VSCALEFPSZrm 6414
-VSCALEFPSZrmb 6415
-VSCALEFPSZrmbk 6416
-VSCALEFPSZrmbkz 6417
-VSCALEFPSZrmk 6418
-VSCALEFPSZrmkz 6419
-VSCALEFPSZrr 6420
-VSCALEFPSZrrb 6421
-VSCALEFPSZrrbk 6422
-VSCALEFPSZrrbkz 6423
-VSCALEFPSZrrk 6424
-VSCALEFPSZrrkz 6425
-VSCALEFSDZrm 6426
-VSCALEFSDZrmk 6427
-VSCALEFSDZrmkz 6428
-VSCALEFSDZrr 6429
-VSCALEFSDZrrb_Int 6430
-VSCALEFSDZrrbk_Int 6431
-VSCALEFSDZrrbkz_Int 6432
-VSCALEFSDZrrk 6433
-VSCALEFSDZrrkz 6434
-VSCALEFSHZrm 6435
-VSCALEFSHZrmk 6436
-VSCALEFSHZrmkz 6437
-VSCALEFSHZrr 6438
-VSCALEFSHZrrb_Int 6439
-VSCALEFSHZrrbk_Int 6440
-VSCALEFSHZrrbkz_Int 6441
-VSCALEFSHZrrk 6442
-VSCALEFSHZrrkz 6443
-VSCALEFSSZrm 6444
-VSCALEFSSZrmk 6445
-VSCALEFSSZrmkz 6446
-VSCALEFSSZrr 6447
-VSCALEFSSZrrb_Int 6448
-VSCALEFSSZrrbk_Int 6449
-VSCALEFSSZrrbkz_Int 6450
-VSCALEFSSZrrk 6451
-VSCALEFSSZrrkz 6452
-VSCATTERDPDZ 6453
-VSCATTERDPDZmr 6454
-VSCATTERDPSZ 6455
-VSCATTERDPSZmr 6456
-VSCATTERPF 6457
-VSCATTERQPDZ 6458
-VSCATTERQPDZmr 6459
-VSCATTERQPSZ 6460
-VSCATTERQPSZmr 6461
-VSHA 6462
-VSHUFF 6463
-VSHUFI 6464
-VSHUFPDYrmi 6465
-VSHUFPDYrri 6466
-VSHUFPDZ 6467
-VSHUFPDZrmbi 6468
-VSHUFPDZrmbik 6469
-VSHUFPDZrmbikz 6470
-VSHUFPDZrmi 6471
-VSHUFPDZrmik 6472
-VSHUFPDZrmikz 6473
-VSHUFPDZrri 6474
-VSHUFPDZrrik 6475
-VSHUFPDZrrikz 6476
-VSHUFPDrmi 6477
-VSHUFPDrri 6478
-VSHUFPSYrmi 6479
-VSHUFPSYrri 6480
-VSHUFPSZ 6481
-VSHUFPSZrmbi 6482
-VSHUFPSZrmbik 6483
-VSHUFPSZrmbikz 6484
-VSHUFPSZrmi 6485
-VSHUFPSZrmik 6486
-VSHUFPSZrmikz 6487
-VSHUFPSZrri 6488
-VSHUFPSZrrik 6489
-VSHUFPSZrrikz 6490
-VSHUFPSrmi 6491
-VSHUFPSrri 6492
-VSM 6493
-VSQRTBF 6494
-VSQRTPDYm 6495
-VSQRTPDYr 6496
-VSQRTPDZ 6497
-VSQRTPDZm 6498
-VSQRTPDZmb 6499
-VSQRTPDZmbk 6500
-VSQRTPDZmbkz 6501
-VSQRTPDZmk 6502
-VSQRTPDZmkz 6503
-VSQRTPDZr 6504
-VSQRTPDZrb 6505
-VSQRTPDZrbk 6506
-VSQRTPDZrbkz 6507
-VSQRTPDZrk 6508
-VSQRTPDZrkz 6509
-VSQRTPDm 6510
-VSQRTPDr 6511
-VSQRTPHZ 6512
-VSQRTPHZm 6513
-VSQRTPHZmb 6514
-VSQRTPHZmbk 6515
-VSQRTPHZmbkz 6516
-VSQRTPHZmk 6517
-VSQRTPHZmkz 6518
-VSQRTPHZr 6519
-VSQRTPHZrb 6520
-VSQRTPHZrbk 6521
-VSQRTPHZrbkz 6522
-VSQRTPHZrk 6523
-VSQRTPHZrkz 6524
-VSQRTPSYm 6525
-VSQRTPSYr 6526
-VSQRTPSZ 6527
-VSQRTPSZm 6528
-VSQRTPSZmb 6529
-VSQRTPSZmbk 6530
-VSQRTPSZmbkz 6531
-VSQRTPSZmk 6532
-VSQRTPSZmkz 6533
-VSQRTPSZr 6534
-VSQRTPSZrb 6535
-VSQRTPSZrbk 6536
-VSQRTPSZrbkz 6537
-VSQRTPSZrk 6538
-VSQRTPSZrkz 6539
-VSQRTPSm 6540
-VSQRTPSr 6541
-VSQRTSDZm 6542
-VSQRTSDZm_Int 6543
-VSQRTSDZmk_Int 6544
-VSQRTSDZmkz_Int 6545
-VSQRTSDZr 6546
-VSQRTSDZr_Int 6547
-VSQRTSDZrb_Int 6548
-VSQRTSDZrbk_Int 6549
-VSQRTSDZrbkz_Int 6550
-VSQRTSDZrk_Int 6551
-VSQRTSDZrkz_Int 6552
-VSQRTSDm 6553
-VSQRTSDm_Int 6554
-VSQRTSDr 6555
-VSQRTSDr_Int 6556
-VSQRTSHZm 6557
-VSQRTSHZm_Int 6558
-VSQRTSHZmk_Int 6559
-VSQRTSHZmkz_Int 6560
-VSQRTSHZr 6561
-VSQRTSHZr_Int 6562
-VSQRTSHZrb_Int 6563
-VSQRTSHZrbk_Int 6564
-VSQRTSHZrbkz_Int 6565
-VSQRTSHZrk_Int 6566
-VSQRTSHZrkz_Int 6567
-VSQRTSSZm 6568
-VSQRTSSZm_Int 6569
-VSQRTSSZmk_Int 6570
-VSQRTSSZmkz_Int 6571
-VSQRTSSZr 6572
-VSQRTSSZr_Int 6573
-VSQRTSSZrb_Int 6574
-VSQRTSSZrbk_Int 6575
-VSQRTSSZrbkz_Int 6576
-VSQRTSSZrk_Int 6577
-VSQRTSSZrkz_Int 6578
-VSQRTSSm 6579
-VSQRTSSm_Int 6580
-VSQRTSSr 6581
-VSQRTSSr_Int 6582
-VSTMXCSR 6583
-VSUBBF 6584
-VSUBPDYrm 6585
-VSUBPDYrr 6586
-VSUBPDZ 6587
-VSUBPDZrm 6588
-VSUBPDZrmb 6589
-VSUBPDZrmbk 6590
-VSUBPDZrmbkz 6591
-VSUBPDZrmk 6592
-VSUBPDZrmkz 6593
-VSUBPDZrr 6594
-VSUBPDZrrb 6595
-VSUBPDZrrbk 6596
-VSUBPDZrrbkz 6597
-VSUBPDZrrk 6598
-VSUBPDZrrkz 6599
-VSUBPDrm 6600
-VSUBPDrr 6601
-VSUBPHZ 6602
-VSUBPHZrm 6603
-VSUBPHZrmb 6604
-VSUBPHZrmbk 6605
-VSUBPHZrmbkz 6606
-VSUBPHZrmk 6607
-VSUBPHZrmkz 6608
-VSUBPHZrr 6609
-VSUBPHZrrb 6610
-VSUBPHZrrbk 6611
-VSUBPHZrrbkz 6612
-VSUBPHZrrk 6613
-VSUBPHZrrkz 6614
-VSUBPSYrm 6615
-VSUBPSYrr 6616
-VSUBPSZ 6617
-VSUBPSZrm 6618
-VSUBPSZrmb 6619
-VSUBPSZrmbk 6620
-VSUBPSZrmbkz 6621
-VSUBPSZrmk 6622
-VSUBPSZrmkz 6623
-VSUBPSZrr 6624
-VSUBPSZrrb 6625
-VSUBPSZrrbk 6626
-VSUBPSZrrbkz 6627
-VSUBPSZrrk 6628
-VSUBPSZrrkz 6629
-VSUBPSrm 6630
-VSUBPSrr 6631
-VSUBSDZrm 6632
-VSUBSDZrm_Int 6633
-VSUBSDZrmk_Int 6634
-VSUBSDZrmkz_Int 6635
-VSUBSDZrr 6636
-VSUBSDZrr_Int 6637
-VSUBSDZrrb_Int 6638
-VSUBSDZrrbk_Int 6639
-VSUBSDZrrbkz_Int 6640
-VSUBSDZrrk_Int 6641
-VSUBSDZrrkz_Int 6642
-VSUBSDrm 6643
-VSUBSDrm_Int 6644
-VSUBSDrr 6645
-VSUBSDrr_Int 6646
-VSUBSHZrm 6647
-VSUBSHZrm_Int 6648
-VSUBSHZrmk_Int 6649
-VSUBSHZrmkz_Int 6650
-VSUBSHZrr 6651
-VSUBSHZrr_Int 6652
-VSUBSHZrrb_Int 6653
-VSUBSHZrrbk_Int 6654
-VSUBSHZrrbkz_Int 6655
-VSUBSHZrrk_Int 6656
-VSUBSHZrrkz_Int 6657
-VSUBSSZrm 6658
-VSUBSSZrm_Int 6659
-VSUBSSZrmk_Int 6660
-VSUBSSZrmkz_Int 6661
-VSUBSSZrr 6662
-VSUBSSZrr_Int 6663
-VSUBSSZrrb_Int 6664
-VSUBSSZrrbk_Int 6665
-VSUBSSZrrbkz_Int 6666
-VSUBSSZrrk_Int 6667
-VSUBSSZrrkz_Int 6668
-VSUBSSrm 6669
-VSUBSSrm_Int 6670
-VSUBSSrr 6671
-VSUBSSrr_Int 6672
-VTESTPDYrm 6673
-VTESTPDYrr 6674
-VTESTPDrm 6675
-VTESTPDrr 6676
-VTESTPSYrm 6677
-VTESTPSYrr 6678
-VTESTPSrm 6679
-VTESTPSrr 6680
-VUCOMISDZrm 6681
-VUCOMISDZrm_Int 6682
-VUCOMISDZrr 6683
-VUCOMISDZrr_Int 6684
-VUCOMISDZrrb 6685
-VUCOMISDrm 6686
-VUCOMISDrm_Int 6687
-VUCOMISDrr 6688
-VUCOMISDrr_Int 6689
-VUCOMISHZrm 6690
-VUCOMISHZrm_Int 6691
-VUCOMISHZrr 6692
-VUCOMISHZrr_Int 6693
-VUCOMISHZrrb 6694
-VUCOMISSZrm 6695
-VUCOMISSZrm_Int 6696
-VUCOMISSZrr 6697
-VUCOMISSZrr_Int 6698
-VUCOMISSZrrb 6699
-VUCOMISSrm 6700
-VUCOMISSrm_Int 6701
-VUCOMISSrr 6702
-VUCOMISSrr_Int 6703
-VUCOMXSDZrm 6704
-VUCOMXSDZrm_Int 6705
-VUCOMXSDZrr 6706
-VUCOMXSDZrr_Int 6707
-VUCOMXSDZrrb_Int 6708
-VUCOMXSHZrm 6709
-VUCOMXSHZrm_Int 6710
-VUCOMXSHZrr 6711
-VUCOMXSHZrr_Int 6712
-VUCOMXSHZrrb_Int 6713
-VUCOMXSSZrm 6714
-VUCOMXSSZrm_Int 6715
-VUCOMXSSZrr 6716
-VUCOMXSSZrr_Int 6717
-VUCOMXSSZrrb_Int 6718
-VUNPCKHPDYrm 6719
-VUNPCKHPDYrr 6720
-VUNPCKHPDZ 6721
-VUNPCKHPDZrm 6722
-VUNPCKHPDZrmb 6723
-VUNPCKHPDZrmbk 6724
-VUNPCKHPDZrmbkz 6725
-VUNPCKHPDZrmk 6726
-VUNPCKHPDZrmkz 6727
-VUNPCKHPDZrr 6728
-VUNPCKHPDZrrk 6729
-VUNPCKHPDZrrkz 6730
-VUNPCKHPDrm 6731
-VUNPCKHPDrr 6732
-VUNPCKHPSYrm 6733
-VUNPCKHPSYrr 6734
-VUNPCKHPSZ 6735
-VUNPCKHPSZrm 6736
-VUNPCKHPSZrmb 6737
-VUNPCKHPSZrmbk 6738
-VUNPCKHPSZrmbkz 6739
-VUNPCKHPSZrmk 6740
-VUNPCKHPSZrmkz 6741
-VUNPCKHPSZrr 6742
-VUNPCKHPSZrrk 6743
-VUNPCKHPSZrrkz 6744
-VUNPCKHPSrm 6745
-VUNPCKHPSrr 6746
-VUNPCKLPDYrm 6747
-VUNPCKLPDYrr 6748
-VUNPCKLPDZ 6749
-VUNPCKLPDZrm 6750
-VUNPCKLPDZrmb 6751
-VUNPCKLPDZrmbk 6752
-VUNPCKLPDZrmbkz 6753
-VUNPCKLPDZrmk 6754
-VUNPCKLPDZrmkz 6755
-VUNPCKLPDZrr 6756
-VUNPCKLPDZrrk 6757
-VUNPCKLPDZrrkz 6758
-VUNPCKLPDrm 6759
-VUNPCKLPDrr 6760
-VUNPCKLPSYrm 6761
-VUNPCKLPSYrr 6762
-VUNPCKLPSZ 6763
-VUNPCKLPSZrm 6764
-VUNPCKLPSZrmb 6765
-VUNPCKLPSZrmbk 6766
-VUNPCKLPSZrmbkz 6767
-VUNPCKLPSZrmk 6768
-VUNPCKLPSZrmkz 6769
-VUNPCKLPSZrr 6770
-VUNPCKLPSZrrk 6771
-VUNPCKLPSZrrkz 6772
-VUNPCKLPSrm 6773
-VUNPCKLPSrr 6774
-VXORPDYrm 6775
-VXORPDYrr 6776
-VXORPDZ 6777
-VXORPDZrm 6778
-VXORPDZrmb 6779
-VXORPDZrmbk 6780
-VXORPDZrmbkz 6781
-VXORPDZrmk 6782
-VXORPDZrmkz 6783
-VXORPDZrr 6784
-VXORPDZrrk 6785
-VXORPDZrrkz 6786
-VXORPDrm 6787
-VXORPDrr 6788
-VXORPSYrm 6789
-VXORPSYrr 6790
-VXORPSZ 6791
-VXORPSZrm 6792
-VXORPSZrmb 6793
-VXORPSZrmbk 6794
-VXORPSZrmbkz 6795
-VXORPSZrmk 6796
-VXORPSZrmkz 6797
-VXORPSZrr 6798
-VXORPSZrrk 6799
-VXORPSZrrkz 6800
-VXORPSrm 6801
-VXORPSrr 6802
-VZEROALL 6803
-VZEROUPPER 6804
-V_SET 6805
-V_SETALLONES 6806
-WAIT 6807
-WBINVD 6808
-WBNOINVD 6809
-WRFLAGS 6810
-WRFSBASE 6811
-WRGSBASE 6812
-WRMSR 6813
-WRMSRLIST 6814
-WRMSRNS 6815
-WRMSRNSir 6816
-WRMSRNSir_EVEX 6817
-WRPKRUr 6818
-WRSSD 6819
-WRSSD_EVEX 6820
-WRSSQ 6821
-WRSSQ_EVEX 6822
-WRUSSD 6823
-WRUSSD_EVEX 6824
-WRUSSQ 6825
-WRUSSQ_EVEX 6826
-XABORT 6827
-XABORT_DEF 6828
-XACQUIRE_PREFIX 6829
-XADD 6830
-XAM_F 6831
-XAM_Fp 6832
-XBEGIN 6833
-XCHG 6834
-XCH_F 6835
-XCRYPTCBC 6836
-XCRYPTCFB 6837
-XCRYPTCTR 6838
-XCRYPTECB 6839
-XCRYPTOFB 6840
-XEND 6841
-XGETBV 6842
-XLAT 6843
-XOR 6844
-XORPDrm 6845
-XORPDrr 6846
-XORPSrm 6847
-XORPSrr 6848
-XRELEASE_PREFIX 6849
-XRESLDTRK 6850
-XRSTOR 6851
-XRSTORS 6852
-XSAVE 6853
-XSAVEC 6854
-XSAVEOPT 6855
-XSAVES 6856
-XSETBV 6857
-XSHA 6858
-XSTORE 6859
-XSUSLDTRK 6860
-XTEST 6861
-Immediate 6862
-CImmediate 6863
-FPImmediate 6864
-MBB 6865
-FrameIndex 6866
-ConstantPoolIndex 6867
-TargetIndex 6868
-JumpTableIndex 6869
-ExternalSymbol 6870
-GlobalAddress 6871
-BlockAddress 6872
-RegisterMask 6873
-RegisterLiveOut 6874
-Metadata 6875
-MCSymbol 6876
-CFIIndex 6877
-IntrinsicID 6878
-Predicate 6879
-ShuffleMask 6880
-PhyReg_GR8 6881
-PhyReg_GRH8 6882
-PhyReg_GR8_NOREX2 6883
-PhyReg_GR8_NOREX 6884
-PhyReg_GR8_ABCD_H 6885
-PhyReg_GR8_ABCD_L 6886
-PhyReg_GRH16 6887
-PhyReg_GR16 6888
-PhyReg_GR16_NOREX2 6889
-PhyReg_GR16_NOREX 6890
-PhyReg_VK1 6891
-PhyReg_VK16 6892
-PhyReg_VK2 6893
-PhyReg_VK4 6894
-PhyReg_VK8 6895
-PhyReg_VK16WM 6896
-PhyReg_VK1WM 6897
-PhyReg_VK2WM 6898
-PhyReg_VK4WM 6899
-PhyReg_VK8WM 6900
-PhyReg_SEGMENT_REG 6901
-PhyReg_GR16_ABCD 6902
-PhyReg_FPCCR 6903
-PhyReg_FR16X 6904
-PhyReg_FR16 6905
-PhyReg_VK16PAIR 6906
-PhyReg_VK1PAIR 6907
-PhyReg_VK2PAIR 6908
-PhyReg_VK4PAIR 6909
-PhyReg_VK8PAIR 6910
-PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6911
-PhyReg_LOW32_ADDR_ACCESS_RBP 6912
-PhyReg_LOW32_ADDR_ACCESS 6913
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6914
-PhyReg_FR32X 6915
-PhyReg_GR32 6916
-PhyReg_GR32_NOSP 6917
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6918
-PhyReg_DEBUG_REG 6919
-PhyReg_FR32 6920
-PhyReg_GR32_NOREX2 6921
-PhyReg_GR32_NOREX2_NOSP 6922
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6923
-PhyReg_GR32_NOREX 6924
-PhyReg_VK32 6925
-PhyReg_GR32_NOREX_NOSP 6926
-PhyReg_RFP32 6927
-PhyReg_VK32WM 6928
-PhyReg_GR32_ABCD 6929
-PhyReg_GR32_TC 6930
-PhyReg_GR32_ABCD_and_GR32_TC 6931
-PhyReg_GR32_AD 6932
-PhyReg_GR32_ArgRef 6933
-PhyReg_GR32_BPSP 6934
-PhyReg_GR32_BSI 6935
-PhyReg_GR32_CB 6936
-PhyReg_GR32_DC 6937
-PhyReg_GR32_DIBP 6938
-PhyReg_GR32_SIDI 6939
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6940
-PhyReg_CCR 6941
-PhyReg_DFCCR 6942
-PhyReg_GR32_ABCD_and_GR32_BSI 6943
-PhyReg_GR32_AD_and_GR32_ArgRef 6944
-PhyReg_GR32_ArgRef_and_GR32_CB 6945
-PhyReg_GR32_BPSP_and_GR32_DIBP 6946
-PhyReg_GR32_BPSP_and_GR32_TC 6947
-PhyReg_GR32_BSI_and_GR32_SIDI 6948
-PhyReg_GR32_DIBP_and_GR32_SIDI 6949
-PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6950
-PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6951
-PhyReg_RFP64 6952
-PhyReg_GR64 6953
-PhyReg_FR64X 6954
-PhyReg_GR64_with_sub_8bit 6955
-PhyReg_GR64_NOSP 6956
-PhyReg_GR64_NOREX2 6957
-PhyReg_CONTROL_REG 6958
-PhyReg_FR64 6959
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6960
-PhyReg_GR64_NOREX2_NOSP 6961
-PhyReg_GR64PLTSafe 6962
-PhyReg_GR64_TC 6963
-PhyReg_GR64_NOREX 6964
-PhyReg_GR64_TCW64 6965
-PhyReg_GR64_TC_with_sub_8bit 6966
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6967
-PhyReg_GR64_TCW64_with_sub_8bit 6968
-PhyReg_GR64_TC_and_GR64_TCW64 6969
-PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6970
-PhyReg_VK64 6971
-PhyReg_VR64 6972
-PhyReg_GR64PLTSafe_and_GR64_TC 6973
-PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6974
-PhyReg_GR64_NOREX_NOSP 6975
-PhyReg_GR64_NOREX_and_GR64_TC 6976
-PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6977
-PhyReg_VK64WM 6978
-PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6979
-PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6980
-PhyReg_GR64PLTSafe_and_GR64_TCW64 6981
-PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6982
-PhyReg_GR64_NOREX_and_GR64_TCW64 6983
-PhyReg_GR64_ABCD 6984
-PhyReg_GR64_with_sub_32bit_in_GR32_TC 6985
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6986
-PhyReg_GR64_AD 6987
-PhyReg_GR64_ArgRef 6988
-PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6989
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6990
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6991
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6992
-PhyReg_GR64_with_sub_32bit_in_GR32_CB 6993
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6994
-PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6995
-PhyReg_GR64_A 6996
-PhyReg_GR64_ArgRef_and_GR64_TC 6997
-PhyReg_GR64_and_LOW32_ADDR_ACCESS 6998
-PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 6999
-PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7000
-PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7001
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7002
-PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7003
-PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7004
-PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7005
-PhyReg_RST 7006
-PhyReg_RFP80 7007
-PhyReg_RFP80_7 7008
-PhyReg_VR128X 7009
-PhyReg_VR128 7010
-PhyReg_VR256X 7011
-PhyReg_VR256 7012
-PhyReg_VR512 7013
-PhyReg_VR512_0_15 7014
-PhyReg_TILE 7015
-VirtReg_GR8 7016
-VirtReg_GRH8 7017
-VirtReg_GR8_NOREX2 7018
-VirtReg_GR8_NOREX 7019
-VirtReg_GR8_ABCD_H 7020
-VirtReg_GR8_ABCD_L 7021
-VirtReg_GRH16 7022
-VirtReg_GR16 7023
-VirtReg_GR16_NOREX2 7024
-VirtReg_GR16_NOREX 7025
-VirtReg_VK1 7026
-VirtReg_VK16 7027
-VirtReg_VK2 7028
-VirtReg_VK4 7029
-VirtReg_VK8 7030
-VirtReg_VK16WM 7031
-VirtReg_VK1WM 7032
-VirtReg_VK2WM 7033
-VirtReg_VK4WM 7034
-VirtReg_VK8WM 7035
-VirtReg_SEGMENT_REG 7036
-VirtReg_GR16_ABCD 7037
-VirtReg_FPCCR 7038
-VirtReg_FR16X 7039
-VirtReg_FR16 7040
-VirtReg_VK16PAIR 7041
-VirtReg_VK1PAIR 7042
-VirtReg_VK2PAIR 7043
-VirtReg_VK4PAIR 7044
-VirtReg_VK8PAIR 7045
-VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7046
-VirtReg_LOW32_ADDR_ACCESS_RBP 7047
-VirtReg_LOW32_ADDR_ACCESS 7048
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7049
-VirtReg_FR32X 7050
-VirtReg_GR32 7051
-VirtReg_GR32_NOSP 7052
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7053
-VirtReg_DEBUG_REG 7054
-VirtReg_FR32 7055
-VirtReg_GR32_NOREX2 7056
-VirtReg_GR32_NOREX2_NOSP 7057
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7058
-VirtReg_GR32_NOREX 7059
-VirtReg_VK32 7060
-VirtReg_GR32_NOREX_NOSP 7061
-VirtReg_RFP32 7062
-VirtReg_VK32WM 7063
-VirtReg_GR32_ABCD 7064
-VirtReg_GR32_TC 7065
-VirtReg_GR32_ABCD_and_GR32_TC 7066
-VirtReg_GR32_AD 7067
-VirtReg_GR32_ArgRef 7068
-VirtReg_GR32_BPSP 7069
-VirtReg_GR32_BSI 7070
-VirtReg_GR32_CB 7071
-VirtReg_GR32_DC 7072
-VirtReg_GR32_DIBP 7073
-VirtReg_GR32_SIDI 7074
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7075
-VirtReg_CCR 7076
-VirtReg_DFCCR 7077
-VirtReg_GR32_ABCD_and_GR32_BSI 7078
-VirtReg_GR32_AD_and_GR32_ArgRef 7079
-VirtReg_GR32_ArgRef_and_GR32_CB 7080
-VirtReg_GR32_BPSP_and_GR32_DIBP 7081
-VirtReg_GR32_BPSP_and_GR32_TC 7082
-VirtReg_GR32_BSI_and_GR32_SIDI 7083
-VirtReg_GR32_DIBP_and_GR32_SIDI 7084
-VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7085
-VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7086
-VirtReg_RFP64 7087
-VirtReg_GR64 7088
-VirtReg_FR64X 7089
-VirtReg_GR64_with_sub_8bit 7090
-VirtReg_GR64_NOSP 7091
-VirtReg_GR64_NOREX2 7092
-VirtReg_CONTROL_REG 7093
-VirtReg_FR64 7094
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7095
-VirtReg_GR64_NOREX2_NOSP 7096
-VirtReg_GR64PLTSafe 7097
-VirtReg_GR64_TC 7098
-VirtReg_GR64_NOREX 7099
-VirtReg_GR64_TCW64 7100
-VirtReg_GR64_TC_with_sub_8bit 7101
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7102
-VirtReg_GR64_TCW64_with_sub_8bit 7103
-VirtReg_GR64_TC_and_GR64_TCW64 7104
-VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7105
-VirtReg_VK64 7106
-VirtReg_VR64 7107
-VirtReg_GR64PLTSafe_and_GR64_TC 7108
-VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7109
-VirtReg_GR64_NOREX_NOSP 7110
-VirtReg_GR64_NOREX_and_GR64_TC 7111
-VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7112
-VirtReg_VK64WM 7113
-VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7114
-VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7115
-VirtReg_GR64PLTSafe_and_GR64_TCW64 7116
-VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7117
-VirtReg_GR64_NOREX_and_GR64_TCW64 7118
-VirtReg_GR64_ABCD 7119
-VirtReg_GR64_with_sub_32bit_in_GR32_TC 7120
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7121
-VirtReg_GR64_AD 7122
-VirtReg_GR64_ArgRef 7123
-VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7124
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7125
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7126
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7127
-VirtReg_GR64_with_sub_32bit_in_GR32_CB 7128
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7129
-VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7130
-VirtReg_GR64_A 7131
-VirtReg_GR64_ArgRef_and_GR64_TC 7132
-VirtReg_GR64_and_LOW32_ADDR_ACCESS 7133
-VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7134
-VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7135
-VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7136
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7137
-VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7138
-VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7139
-VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7140
-VirtReg_RST 7141
-VirtReg_RFP80 7142
-VirtReg_RFP80_7 7143
-VirtReg_VR128X 7144
-VirtReg_VR128 7145
-VirtReg_VR256X 7146
-VirtReg_VR256 7147
-VirtReg_VR512 7148
-VirtReg_VR512_0_15 7149
-VirtReg_TILE 7150
+G_SAVGCEIL 492
+G_SAVGFLOOR 493
+G_SBFX 494
+G_SCMP 495
+G_SDIV 496
+G_SDIVFIX 497
+G_SDIVFIXSAT 498
+G_SDIVREM 499
+G_SELECT 500
+G_SET_FPENV 501
+G_SET_FPMODE 502
+G_SET_ROUNDING 503
+G_SEXT 504
+G_SEXTLOAD 505
+G_SEXT_INREG 506
+G_SHL 507
+G_SHUFFLE_VECTOR 508
+G_SITOFP 509
+G_SMAX 510
+G_SMIN 511
+G_SMULFIX 512
+G_SMULFIXSAT 513
+G_SMULH 514
+G_SMULO 515
+G_SPLAT_VECTOR 516
+G_SREM 517
+G_SSHLSAT 518
+G_SSUBE 519
+G_SSUBO 520
+G_SSUBSAT 521
+G_STACKRESTORE 522
+G_STACKSAVE 523
+G_STEP_VECTOR 524
+G_STORE 525
+G_STRICT_FADD 526
+G_STRICT_FDIV 527
+G_STRICT_FLDEXP 528
+G_STRICT_FMA 529
+G_STRICT_FMUL 530
+G_STRICT_FREM 531
+G_STRICT_FSQRT 532
+G_STRICT_FSUB 533
+G_SUB 534
+G_TRAP 535
+G_TRUNC 536
+G_TRUNC_SSAT_S 537
+G_TRUNC_SSAT_U 538
+G_TRUNC_USAT_U 539
+G_UADDE 540
+G_UADDO 541
+G_UADDSAT 542
+G_UAVGCEIL 543
+G_UAVGFLOOR 544
+G_UBFX 545
+G_UBSANTRAP 546
+G_UCMP 547
+G_UDIV 548
+G_UDIVFIX 549
+G_UDIVFIXSAT 550
+G_UDIVREM 551
+G_UITOFP 552
+G_UMAX 553
+G_UMIN 554
+G_UMULFIX 555
+G_UMULFIXSAT 556
+G_UMULH 557
+G_UMULO 558
+G_UNMERGE_VALUES 559
+G_UREM 560
+G_USHLSAT 561
+G_USUBE 562
+G_USUBO 563
+G_USUBSAT 564
+G_VAARG 565
+G_VASTART 566
+G_VECREDUCE_ADD 567
+G_VECREDUCE_AND 568
+G_VECREDUCE_FADD 569
+G_VECREDUCE_FMAX 570
+G_VECREDUCE_FMAXIMUM 571
+G_VECREDUCE_FMIN 572
+G_VECREDUCE_FMINIMUM 573
+G_VECREDUCE_FMUL 574
+G_VECREDUCE_MUL 575
+G_VECREDUCE_OR 576
+G_VECREDUCE_SEQ_FADD 577
+G_VECREDUCE_SEQ_FMUL 578
+G_VECREDUCE_SMAX 579
+G_VECREDUCE_SMIN 580
+G_VECREDUCE_UMAX 581
+G_VECREDUCE_UMIN 582
+G_VECREDUCE_XOR 583
+G_VECTOR_COMPRESS 584
+G_VSCALE 585
+G_WRITE_REGISTER 586
+G_XOR 587
+G_ZEXT 588
+G_ZEXTLOAD 589
+HADDPDrm 590
+HADDPDrr 591
+HADDPSrm 592
+HADDPSrr 593
+HLT 594
+HRESET 595
+HSUBPDrm 596
+HSUBPDrr 597
+HSUBPSrm 598
+HSUBPSrr 599
+ICALL_BRANCH_FUNNEL 600
+IDIV 601
+ILD_F 602
+ILD_Fp 603
+IMPLICIT_DEF 604
+IMUL 605
+IMULZU 606
+IN 607
+INC 608
+INCSSPD 609
+INCSSPQ 610
+INDIRECT_THUNK_CALL 611
+INDIRECT_THUNK_TCRETURN 612
+INIT_UNDEF 613
+INLINEASM 614
+INLINEASM_BR 615
+INSB 616
+INSERTPSrmi 617
+INSERTPSrri 618
+INSERTQ 619
+INSERTQI 620
+INSERT_SUBREG 621
+INSL 622
+INSW 623
+INT 624
+INTO 625
+INVD 626
+INVEPT 627
+INVLPG 628
+INVLPGA 629
+INVLPGB 630
+INVPCID 631
+INVVPID 632
+IRET 633
+ISTT_FP 634
+ISTT_Fp 635
+IST_F 636
+IST_FP 637
+IST_Fp 638
+Int_eh_sjlj_setup_dispatch 639
+JCC 640
+JCXZ 641
+JECXZ 642
+JMP 643
+JMPABS 644
+JRCXZ 645
+JUMP_TABLE_DEBUG_INFO 646
+KADDBkk 647
+KADDDkk 648
+KADDQkk 649
+KADDWkk 650
+KANDBkk 651
+KANDDkk 652
+KANDNBkk 653
+KANDNDkk 654
+KANDNQkk 655
+KANDNWkk 656
+KANDQkk 657
+KANDWkk 658
+KCFI_CHECK 659
+KILL 660
+KMOVBkk 661
+KMOVBkk_EVEX 662
+KMOVBkm 663
+KMOVBkm_EVEX 664
+KMOVBkr 665
+KMOVBkr_EVEX 666
+KMOVBmk 667
+KMOVBmk_EVEX 668
+KMOVBrk 669
+KMOVBrk_EVEX 670
+KMOVDkk 671
+KMOVDkk_EVEX 672
+KMOVDkm 673
+KMOVDkm_EVEX 674
+KMOVDkr 675
+KMOVDkr_EVEX 676
+KMOVDmk 677
+KMOVDmk_EVEX 678
+KMOVDrk 679
+KMOVDrk_EVEX 680
+KMOVQkk 681
+KMOVQkk_EVEX 682
+KMOVQkm 683
+KMOVQkm_EVEX 684
+KMOVQkr 685
+KMOVQkr_EVEX 686
+KMOVQmk 687
+KMOVQmk_EVEX 688
+KMOVQrk 689
+KMOVQrk_EVEX 690
+KMOVWkk 691
+KMOVWkk_EVEX 692
+KMOVWkm 693
+KMOVWkm_EVEX 694
+KMOVWkr 695
+KMOVWkr_EVEX 696
+KMOVWmk 697
+KMOVWmk_EVEX 698
+KMOVWrk 699
+KMOVWrk_EVEX 700
+KNOTBkk 701
+KNOTDkk 702
+KNOTQkk 703
+KNOTWkk 704
+KORBkk 705
+KORDkk 706
+KORQkk 707
+KORTESTBkk 708
+KORTESTDkk 709
+KORTESTQkk 710
+KORTESTWkk 711
+KORWkk 712
+KSET 713
+KSHIFTLBki 714
+KSHIFTLDki 715
+KSHIFTLQki 716
+KSHIFTLWki 717
+KSHIFTRBki 718
+KSHIFTRDki 719
+KSHIFTRQki 720
+KSHIFTRWki 721
+KTESTBkk 722
+KTESTDkk 723
+KTESTQkk 724
+KTESTWkk 725
+KUNPCKBWkk 726
+KUNPCKDQkk 727
+KUNPCKWDkk 728
+KXNORBkk 729
+KXNORDkk 730
+KXNORQkk 731
+KXNORWkk 732
+KXORBkk 733
+KXORDkk 734
+KXORQkk 735
+KXORWkk 736
+LAHF 737
+LAR 738
+LCMPXCHG 739
+LDDQUrm 740
+LDMXCSR 741
+LDS 742
+LDTILECFG 743
+LDTILECFG_EVEX 744
+LD_F 745
+LD_Fp 746
+LD_Frr 747
+LEA 748
+LEAVE 749
+LES 750
+LFENCE 751
+LFS 752
+LGDT 753
+LGS 754
+LIDT 755
+LIFETIME_END 756
+LIFETIME_START 757
+LKGS 758
+LLDT 759
+LLWPCB 760
+LMSW 761
+LOADIWKEY 762
+LOAD_STACK_GUARD 763
+LOCAL_ESCAPE 764
+LOCK_ADD 765
+LOCK_AND 766
+LOCK_BTC 767
+LOCK_BTC_RM 768
+LOCK_BTR 769
+LOCK_BTR_RM 770
+LOCK_BTS 771
+LOCK_BTS_RM 772
+LOCK_DEC 773
+LOCK_INC 774
+LOCK_OR 775
+LOCK_PREFIX 776
+LOCK_SUB 777
+LOCK_XOR 778
+LODSB 779
+LODSL 780
+LODSQ 781
+LODSW 782
+LOOP 783
+LOOPE 784
+LOOPNE 785
+LRET 786
+LRETI 787
+LSL 788
+LSS 789
+LTRm 790
+LTRr 791
+LWPINS 792
+LWPVAL 793
+LXADD 794
+LZCNT 795
+MASKMOVDQU 796
+MASKPAIR 797
+MAXCPDrm 798
+MAXCPDrr 799
+MAXCPSrm 800
+MAXCPSrr 801
+MAXCSDrm 802
+MAXCSDrr 803
+MAXCSSrm 804
+MAXCSSrr 805
+MAXPDrm 806
+MAXPDrr 807
+MAXPSrm 808
+MAXPSrr 809
+MAXSDrm 810
+MAXSDrm_Int 811
+MAXSDrr 812
+MAXSDrr_Int 813
+MAXSSrm 814
+MAXSSrm_Int 815
+MAXSSrr 816
+MAXSSrr_Int 817
+MEMBARRIER 818
+MFENCE 819
+MINCPDrm 820
+MINCPDrr 821
+MINCPSrm 822
+MINCPSrr 823
+MINCSDrm 824
+MINCSDrr 825
+MINCSSrm 826
+MINCSSrr 827
+MINPDrm 828
+MINPDrr 829
+MINPSrm 830
+MINPSrr 831
+MINSDrm 832
+MINSDrm_Int 833
+MINSDrr 834
+MINSDrr_Int 835
+MINSSrm 836
+MINSSrm_Int 837
+MINSSrr 838
+MINSSrr_Int 839
+MMX_CVTPD 840
+MMX_CVTPI 841
+MMX_CVTPS 842
+MMX_CVTTPD 843
+MMX_CVTTPS 844
+MMX_EMMS 845
+MMX_MASKMOVQ 846
+MMX_MOVD 847
+MMX_MOVDQ 848
+MMX_MOVFR 849
+MMX_MOVNTQmr 850
+MMX_MOVQ 851
+MMX_PABSBrm 852
+MMX_PABSBrr 853
+MMX_PABSDrm 854
+MMX_PABSDrr 855
+MMX_PABSWrm 856
+MMX_PABSWrr 857
+MMX_PACKSSDWrm 858
+MMX_PACKSSDWrr 859
+MMX_PACKSSWBrm 860
+MMX_PACKSSWBrr 861
+MMX_PACKUSWBrm 862
+MMX_PACKUSWBrr 863
+MMX_PADDBrm 864
+MMX_PADDBrr 865
+MMX_PADDDrm 866
+MMX_PADDDrr 867
+MMX_PADDQrm 868
+MMX_PADDQrr 869
+MMX_PADDSBrm 870
+MMX_PADDSBrr 871
+MMX_PADDSWrm 872
+MMX_PADDSWrr 873
+MMX_PADDUSBrm 874
+MMX_PADDUSBrr 875
+MMX_PADDUSWrm 876
+MMX_PADDUSWrr 877
+MMX_PADDWrm 878
+MMX_PADDWrr 879
+MMX_PALIGNRrmi 880
+MMX_PALIGNRrri 881
+MMX_PANDNrm 882
+MMX_PANDNrr 883
+MMX_PANDrm 884
+MMX_PANDrr 885
+MMX_PAVGBrm 886
+MMX_PAVGBrr 887
+MMX_PAVGWrm 888
+MMX_PAVGWrr 889
+MMX_PCMPEQBrm 890
+MMX_PCMPEQBrr 891
+MMX_PCMPEQDrm 892
+MMX_PCMPEQDrr 893
+MMX_PCMPEQWrm 894
+MMX_PCMPEQWrr 895
+MMX_PCMPGTBrm 896
+MMX_PCMPGTBrr 897
+MMX_PCMPGTDrm 898
+MMX_PCMPGTDrr 899
+MMX_PCMPGTWrm 900
+MMX_PCMPGTWrr 901
+MMX_PEXTRWrri 902
+MMX_PHADDDrm 903
+MMX_PHADDDrr 904
+MMX_PHADDSWrm 905
+MMX_PHADDSWrr 906
+MMX_PHADDWrm 907
+MMX_PHADDWrr 908
+MMX_PHSUBDrm 909
+MMX_PHSUBDrr 910
+MMX_PHSUBSWrm 911
+MMX_PHSUBSWrr 912
+MMX_PHSUBWrm 913
+MMX_PHSUBWrr 914
+MMX_PINSRWrmi 915
+MMX_PINSRWrri 916
+MMX_PMADDUBSWrm 917
+MMX_PMADDUBSWrr 918
+MMX_PMADDWDrm 919
+MMX_PMADDWDrr 920
+MMX_PMAXSWrm 921
+MMX_PMAXSWrr 922
+MMX_PMAXUBrm 923
+MMX_PMAXUBrr 924
+MMX_PMINSWrm 925
+MMX_PMINSWrr 926
+MMX_PMINUBrm 927
+MMX_PMINUBrr 928
+MMX_PMOVMSKBrr 929
+MMX_PMULHRSWrm 930
+MMX_PMULHRSWrr 931
+MMX_PMULHUWrm 932
+MMX_PMULHUWrr 933
+MMX_PMULHWrm 934
+MMX_PMULHWrr 935
+MMX_PMULLWrm 936
+MMX_PMULLWrr 937
+MMX_PMULUDQrm 938
+MMX_PMULUDQrr 939
+MMX_PORrm 940
+MMX_PORrr 941
+MMX_PSADBWrm 942
+MMX_PSADBWrr 943
+MMX_PSHUFBrm 944
+MMX_PSHUFBrr 945
+MMX_PSHUFWmi 946
+MMX_PSHUFWri 947
+MMX_PSIGNBrm 948
+MMX_PSIGNBrr 949
+MMX_PSIGNDrm 950
+MMX_PSIGNDrr 951
+MMX_PSIGNWrm 952
+MMX_PSIGNWrr 953
+MMX_PSLLDri 954
+MMX_PSLLDrm 955
+MMX_PSLLDrr 956
+MMX_PSLLQri 957
+MMX_PSLLQrm 958
+MMX_PSLLQrr 959
+MMX_PSLLWri 960
+MMX_PSLLWrm 961
+MMX_PSLLWrr 962
+MMX_PSRADri 963
+MMX_PSRADrm 964
+MMX_PSRADrr 965
+MMX_PSRAWri 966
+MMX_PSRAWrm 967
+MMX_PSRAWrr 968
+MMX_PSRLDri 969
+MMX_PSRLDrm 970
+MMX_PSRLDrr 971
+MMX_PSRLQri 972
+MMX_PSRLQrm 973
+MMX_PSRLQrr 974
+MMX_PSRLWri 975
+MMX_PSRLWrm 976
+MMX_PSRLWrr 977
+MMX_PSUBBrm 978
+MMX_PSUBBrr 979
+MMX_PSUBDrm 980
+MMX_PSUBDrr 981
+MMX_PSUBQrm 982
+MMX_PSUBQrr 983
+MMX_PSUBSBrm 984
+MMX_PSUBSBrr 985
+MMX_PSUBSWrm 986
+MMX_PSUBSWrr 987
+MMX_PSUBUSBrm 988
+MMX_PSUBUSBrr 989
+MMX_PSUBUSWrm 990
+MMX_PSUBUSWrr 991
+MMX_PSUBWrm 992
+MMX_PSUBWrr 993
+MMX_PUNPCKHBWrm 994
+MMX_PUNPCKHBWrr 995
+MMX_PUNPCKHDQrm 996
+MMX_PUNPCKHDQrr 997
+MMX_PUNPCKHWDrm 998
+MMX_PUNPCKHWDrr 999
+MMX_PUNPCKLBWrm 1000
+MMX_PUNPCKLBWrr 1001
+MMX_PUNPCKLDQrm 1002
+MMX_PUNPCKLDQrr 1003
+MMX_PUNPCKLWDrm 1004
+MMX_PUNPCKLWDrr 1005
+MMX_PXORrm 1006
+MMX_PXORrr 1007
+MMX_SET 1008
+MONITOR 1009
+MONITORX 1010
+MONTMUL 1011
+MORESTACK_RET 1012
+MORESTACK_RET_RESTORE_R 1013
+MOV 1014
+MOVAPDmr 1015
+MOVAPDrm 1016
+MOVAPDrr 1017
+MOVAPDrr_REV 1018
+MOVAPSmr 1019
+MOVAPSrm 1020
+MOVAPSrr 1021
+MOVAPSrr_REV 1022
+MOVBE 1023
+MOVDDUPrm 1024
+MOVDDUPrr 1025
+MOVDI 1026
+MOVDIR 1027
+MOVDIRI 1028
+MOVDQAmr 1029
+MOVDQArm 1030
+MOVDQArr 1031
+MOVDQArr_REV 1032
+MOVDQUmr 1033
+MOVDQUrm 1034
+MOVDQUrr 1035
+MOVDQUrr_REV 1036
+MOVHLPSrr 1037
+MOVHPDmr 1038
+MOVHPDrm 1039
+MOVHPSmr 1040
+MOVHPSrm 1041
+MOVLHPSrr 1042
+MOVLPDmr 1043
+MOVLPDrm 1044
+MOVLPSmr 1045
+MOVLPSrm 1046
+MOVMSKPDrr 1047
+MOVMSKPSrr 1048
+MOVNTDQArm 1049
+MOVNTDQmr 1050
+MOVNTI 1051
+MOVNTImr 1052
+MOVNTPDmr 1053
+MOVNTPSmr 1054
+MOVNTSD 1055
+MOVNTSS 1056
+MOVPC 1057
+MOVPDI 1058
+MOVPQI 1059
+MOVPQIto 1060
+MOVQI 1061
+MOVRS 1062
+MOVSB 1063
+MOVSDmr 1064
+MOVSDrm 1065
+MOVSDrm_alt 1066
+MOVSDrr 1067
+MOVSDrr_REV 1068
+MOVSDto 1069
+MOVSHDUPrm 1070
+MOVSHDUPrr 1071
+MOVSHPmr 1072
+MOVSHPrm 1073
+MOVSL 1074
+MOVSLDUPrm 1075
+MOVSLDUPrr 1076
+MOVSQ 1077
+MOVSS 1078
+MOVSSmr 1079
+MOVSSrm 1080
+MOVSSrm_alt 1081
+MOVSSrr 1082
+MOVSSrr_REV 1083
+MOVSW 1084
+MOVSX 1085
+MOVUPDmr 1086
+MOVUPDrm 1087
+MOVUPDrr 1088
+MOVUPDrr_REV 1089
+MOVUPSmr 1090
+MOVUPSrm 1091
+MOVUPSrr 1092
+MOVUPSrr_REV 1093
+MOVZPQILo 1094
+MOVZX 1095
+MPSADBWrmi 1096
+MPSADBWrri 1097
+MUL 1098
+MULPDrm 1099
+MULPDrr 1100
+MULPSrm 1101
+MULPSrr 1102
+MULSDrm 1103
+MULSDrm_Int 1104
+MULSDrr 1105
+MULSDrr_Int 1106
+MULSSrm 1107
+MULSSrm_Int 1108
+MULSSrr 1109
+MULSSrr_Int 1110
+MULX 1111
+MUL_F 1112
+MUL_FI 1113
+MUL_FPrST 1114
+MUL_FST 1115
+MUL_Fp 1116
+MUL_FpI 1117
+MUL_FrST 1118
+MWAITX 1119
+MWAITX_SAVE_RBX 1120
+MWAITXrrr 1121
+MWAITrr 1122
+NEG 1123
+NOOP 1124
+NOOPL 1125
+NOOPLr 1126
+NOOPQ 1127
+NOOPQr 1128
+NOOPW 1129
+NOOPWr 1130
+NOT 1131
+OR 1132
+ORPDrm 1133
+ORPDrr 1134
+ORPSrm 1135
+ORPSrr 1136
+OUT 1137
+OUTSB 1138
+OUTSL 1139
+OUTSW 1140
+PABSBrm 1141
+PABSBrr 1142
+PABSDrm 1143
+PABSDrr 1144
+PABSWrm 1145
+PABSWrr 1146
+PACKSSDWrm 1147
+PACKSSDWrr 1148
+PACKSSWBrm 1149
+PACKSSWBrr 1150
+PACKUSDWrm 1151
+PACKUSDWrr 1152
+PACKUSWBrm 1153
+PACKUSWBrr 1154
+PADDBrm 1155
+PADDBrr 1156
+PADDDrm 1157
+PADDDrr 1158
+PADDQrm 1159
+PADDQrr 1160
+PADDSBrm 1161
+PADDSBrr 1162
+PADDSWrm 1163
+PADDSWrr 1164
+PADDUSBrm 1165
+PADDUSBrr 1166
+PADDUSWrm 1167
+PADDUSWrr 1168
+PADDWrm 1169
+PADDWrr 1170
+PALIGNRrmi 1171
+PALIGNRrri 1172
+PANDNrm 1173
+PANDNrr 1174
+PANDrm 1175
+PANDrr 1176
+PATCHABLE_EVENT_CALL 1177
+PATCHABLE_FUNCTION_ENTER 1178
+PATCHABLE_FUNCTION_EXIT 1179
+PATCHABLE_OP 1180
+PATCHABLE_RET 1181
+PATCHABLE_TAIL_CALL 1182
+PATCHABLE_TYPED_EVENT_CALL 1183
+PATCHPOINT 1184
+PAUSE 1185
+PAVGBrm 1186
+PAVGBrr 1187
+PAVGUSBrm 1188
+PAVGUSBrr 1189
+PAVGWrm 1190
+PAVGWrr 1191
+PBLENDVBrm 1192
+PBLENDVBrr 1193
+PBLENDWrmi 1194
+PBLENDWrri 1195
+PBNDKB 1196
+PCLMULQDQrmi 1197
+PCLMULQDQrri 1198
+PCMPEQBrm 1199
+PCMPEQBrr 1200
+PCMPEQDrm 1201
+PCMPEQDrr 1202
+PCMPEQQrm 1203
+PCMPEQQrr 1204
+PCMPEQWrm 1205
+PCMPEQWrr 1206
+PCMPESTRIrmi 1207
+PCMPESTRIrri 1208
+PCMPESTRMrmi 1209
+PCMPESTRMrri 1210
+PCMPGTBrm 1211
+PCMPGTBrr 1212
+PCMPGTDrm 1213
+PCMPGTDrr 1214
+PCMPGTQrm 1215
+PCMPGTQrr 1216
+PCMPGTWrm 1217
+PCMPGTWrr 1218
+PCMPISTRIrmi 1219
+PCMPISTRIrri 1220
+PCMPISTRMrmi 1221
+PCMPISTRMrri 1222
+PCONFIG 1223
+PDEP 1224
+PEXT 1225
+PEXTRBmri 1226
+PEXTRBrri 1227
+PEXTRDmri 1228
+PEXTRDrri 1229
+PEXTRQmri 1230
+PEXTRQrri 1231
+PEXTRWmri 1232
+PEXTRWrri 1233
+PEXTRWrri_REV 1234
+PF 1235
+PFACCrm 1236
+PFACCrr 1237
+PFADDrm 1238
+PFADDrr 1239
+PFCMPEQrm 1240
+PFCMPEQrr 1241
+PFCMPGErm 1242
+PFCMPGErr 1243
+PFCMPGTrm 1244
+PFCMPGTrr 1245
+PFMAXrm 1246
+PFMAXrr 1247
+PFMINrm 1248
+PFMINrr 1249
+PFMULrm 1250
+PFMULrr 1251
+PFNACCrm 1252
+PFNACCrr 1253
+PFPNACCrm 1254
+PFPNACCrr 1255
+PFRCPIT 1256
+PFRCPrm 1257
+PFRCPrr 1258
+PFRSQIT 1259
+PFRSQRTrm 1260
+PFRSQRTrr 1261
+PFSUBRrm 1262
+PFSUBRrr 1263
+PFSUBrm 1264
+PFSUBrr 1265
+PHADDDrm 1266
+PHADDDrr 1267
+PHADDSWrm 1268
+PHADDSWrr 1269
+PHADDWrm 1270
+PHADDWrr 1271
+PHI 1272
+PHMINPOSUWrm 1273
+PHMINPOSUWrr 1274
+PHSUBDrm 1275
+PHSUBDrr 1276
+PHSUBSWrm 1277
+PHSUBSWrr 1278
+PHSUBWrm 1279
+PHSUBWrr 1280
+PI 1281
+PINSRBrmi 1282
+PINSRBrri 1283
+PINSRDrmi 1284
+PINSRDrri 1285
+PINSRQrmi 1286
+PINSRQrri 1287
+PINSRWrmi 1288
+PINSRWrri 1289
+PLDTILECFGV 1290
+PLEA 1291
+PMADDUBSWrm 1292
+PMADDUBSWrr 1293
+PMADDWDrm 1294
+PMADDWDrr 1295
+PMAXSBrm 1296
+PMAXSBrr 1297
+PMAXSDrm 1298
+PMAXSDrr 1299
+PMAXSWrm 1300
+PMAXSWrr 1301
+PMAXUBrm 1302
+PMAXUBrr 1303
+PMAXUDrm 1304
+PMAXUDrr 1305
+PMAXUWrm 1306
+PMAXUWrr 1307
+PMINSBrm 1308
+PMINSBrr 1309
+PMINSDrm 1310
+PMINSDrr 1311
+PMINSWrm 1312
+PMINSWrr 1313
+PMINUBrm 1314
+PMINUBrr 1315
+PMINUDrm 1316
+PMINUDrr 1317
+PMINUWrm 1318
+PMINUWrr 1319
+PMOVMSKBrr 1320
+PMOVSXBDrm 1321
+PMOVSXBDrr 1322
+PMOVSXBQrm 1323
+PMOVSXBQrr 1324
+PMOVSXBWrm 1325
+PMOVSXBWrr 1326
+PMOVSXDQrm 1327
+PMOVSXDQrr 1328
+PMOVSXWDrm 1329
+PMOVSXWDrr 1330
+PMOVSXWQrm 1331
+PMOVSXWQrr 1332
+PMOVZXBDrm 1333
+PMOVZXBDrr 1334
+PMOVZXBQrm 1335
+PMOVZXBQrr 1336
+PMOVZXBWrm 1337
+PMOVZXBWrr 1338
+PMOVZXDQrm 1339
+PMOVZXDQrr 1340
+PMOVZXWDrm 1341
+PMOVZXWDrr 1342
+PMOVZXWQrm 1343
+PMOVZXWQrr 1344
+PMULDQrm 1345
+PMULDQrr 1346
+PMULHRSWrm 1347
+PMULHRSWrr 1348
+PMULHRWrm 1349
+PMULHRWrr 1350
+PMULHUWrm 1351
+PMULHUWrr 1352
+PMULHWrm 1353
+PMULHWrr 1354
+PMULLDrm 1355
+PMULLDrr 1356
+PMULLWrm 1357
+PMULLWrr 1358
+PMULUDQrm 1359
+PMULUDQrr 1360
+POP 1361
+POPA 1362
+POPCNT 1363
+POPDS 1364
+POPES 1365
+POPF 1366
+POPFS 1367
+POPGS 1368
+POPP 1369
+POPSS 1370
+PORrm 1371
+PORrr 1372
+PREALLOCATED_ARG 1373
+PREALLOCATED_SETUP 1374
+PREFETCH 1375
+PREFETCHIT 1376
+PREFETCHNTA 1377
+PREFETCHRST 1378
+PREFETCHT 1379
+PREFETCHW 1380
+PREFETCHWT 1381
+PROBED_ALLOCA 1382
+PSADBWrm 1383
+PSADBWrr 1384
+PSEUDO_PROBE 1385
+PSHUFBrm 1386
+PSHUFBrr 1387
+PSHUFDmi 1388
+PSHUFDri 1389
+PSHUFHWmi 1390
+PSHUFHWri 1391
+PSHUFLWmi 1392
+PSHUFLWri 1393
+PSIGNBrm 1394
+PSIGNBrr 1395
+PSIGNDrm 1396
+PSIGNDrr 1397
+PSIGNWrm 1398
+PSIGNWrr 1399
+PSLLDQri 1400
+PSLLDri 1401
+PSLLDrm 1402
+PSLLDrr 1403
+PSLLQri 1404
+PSLLQrm 1405
+PSLLQrr 1406
+PSLLWri 1407
+PSLLWrm 1408
+PSLLWrr 1409
+PSMASH 1410
+PSRADri 1411
+PSRADrm 1412
+PSRADrr 1413
+PSRAWri 1414
+PSRAWrm 1415
+PSRAWrr 1416
+PSRLDQri 1417
+PSRLDri 1418
+PSRLDrm 1419
+PSRLDrr 1420
+PSRLQri 1421
+PSRLQrm 1422
+PSRLQrr 1423
+PSRLWri 1424
+PSRLWrm 1425
+PSRLWrr 1426
+PSUBBrm 1427
+PSUBBrr 1428
+PSUBDrm 1429
+PSUBDrr 1430
+PSUBQrm 1431
+PSUBQrr 1432
+PSUBSBrm 1433
+PSUBSBrr 1434
+PSUBSWrm 1435
+PSUBSWrr 1436
+PSUBUSBrm 1437
+PSUBUSBrr 1438
+PSUBUSWrm 1439
+PSUBUSWrr 1440
+PSUBWrm 1441
+PSUBWrr 1442
+PSWAPDrm 1443
+PSWAPDrr 1444
+PTCMMIMFP 1445
+PTCMMRLFP 1446
+PTCVTROWD 1447
+PTCVTROWPS 1448
+PTDPBF 1449
+PTDPBHF 1450
+PTDPBSSD 1451
+PTDPBSSDV 1452
+PTDPBSUD 1453
+PTDPBSUDV 1454
+PTDPBUSD 1455
+PTDPBUSDV 1456
+PTDPBUUD 1457
+PTDPBUUDV 1458
+PTDPFP 1459
+PTDPHBF 1460
+PTDPHF 1461
+PTESTrm 1462
+PTESTrr 1463
+PTILELOADD 1464
+PTILELOADDRS 1465
+PTILELOADDRST 1466
+PTILELOADDRSV 1467
+PTILELOADDT 1468
+PTILELOADDV 1469
+PTILEMOVROWrre 1470
+PTILEMOVROWrreV 1471
+PTILEMOVROWrri 1472
+PTILEMOVROWrriV 1473
+PTILESTORED 1474
+PTILESTOREDV 1475
+PTILEZERO 1476
+PTILEZEROV 1477
+PTMMULTF 1478
+PTWRITE 1479
+PTWRITEm 1480
+PTWRITEr 1481
+PUNPCKHBWrm 1482
+PUNPCKHBWrr 1483
+PUNPCKHDQrm 1484
+PUNPCKHDQrr 1485
+PUNPCKHQDQrm 1486
+PUNPCKHQDQrr 1487
+PUNPCKHWDrm 1488
+PUNPCKHWDrr 1489
+PUNPCKLBWrm 1490
+PUNPCKLBWrr 1491
+PUNPCKLDQrm 1492
+PUNPCKLDQrr 1493
+PUNPCKLQDQrm 1494
+PUNPCKLQDQrr 1495
+PUNPCKLWDrm 1496
+PUNPCKLWDrr 1497
+PUSH 1498
+PUSHA 1499
+PUSHCS 1500
+PUSHDS 1501
+PUSHES 1502
+PUSHF 1503
+PUSHFS 1504
+PUSHGS 1505
+PUSHP 1506
+PUSHSS 1507
+PVALIDATE 1508
+PXORrm 1509
+PXORrr 1510
+RCL 1511
+RCPPSm 1512
+RCPPSr 1513
+RCPSSm 1514
+RCPSSm_Int 1515
+RCPSSr 1516
+RCPSSr_Int 1517
+RCR 1518
+RDFLAGS 1519
+RDFSBASE 1520
+RDGSBASE 1521
+RDMSR 1522
+RDMSRLIST 1523
+RDMSRri 1524
+RDMSRri_EVEX 1525
+RDPID 1526
+RDPKRUr 1527
+RDPMC 1528
+RDPRU 1529
+RDRAND 1530
+RDSEED 1531
+RDSSPD 1532
+RDSSPQ 1533
+RDTSC 1534
+RDTSCP 1535
+REG_SEQUENCE 1536
+REPNE_PREFIX 1537
+REP_MOVSB 1538
+REP_MOVSD 1539
+REP_MOVSQ 1540
+REP_MOVSW 1541
+REP_PREFIX 1542
+REP_STOSB 1543
+REP_STOSD 1544
+REP_STOSQ 1545
+REP_STOSW 1546
+RET 1547
+RETI 1548
+REX 1549
+RMPADJUST 1550
+RMPQUERY 1551
+RMPUPDATE 1552
+ROL 1553
+ROR 1554
+RORX 1555
+ROUNDPDmi 1556
+ROUNDPDri 1557
+ROUNDPSmi 1558
+ROUNDPSri 1559
+ROUNDSDmi 1560
+ROUNDSDmi_Int 1561
+ROUNDSDri 1562
+ROUNDSDri_Int 1563
+ROUNDSSmi 1564
+ROUNDSSmi_Int 1565
+ROUNDSSri 1566
+ROUNDSSri_Int 1567
+RSM 1568
+RSQRTPSm 1569
+RSQRTPSr 1570
+RSQRTSSm 1571
+RSQRTSSm_Int 1572
+RSQRTSSr 1573
+RSQRTSSr_Int 1574
+RSTORSSP 1575
+SAHF 1576
+SALC 1577
+SAR 1578
+SARX 1579
+SAVEPREVSSP 1580
+SBB 1581
+SCASB 1582
+SCASL 1583
+SCASQ 1584
+SCASW 1585
+SEAMCALL 1586
+SEAMOPS 1587
+SEAMRET 1588
+SEG_ALLOCA 1589
+SEH_BeginEpilogue 1590
+SEH_EndEpilogue 1591
+SEH_EndPrologue 1592
+SEH_PushFrame 1593
+SEH_PushReg 1594
+SEH_SaveReg 1595
+SEH_SaveXMM 1596
+SEH_SetFrame 1597
+SEH_StackAlign 1598
+SEH_StackAlloc 1599
+SEH_UnwindV 1600
+SEH_UnwindVersion 1601
+SENDUIPI 1602
+SERIALIZE 1603
+SETB_C 1604
+SETCCm 1605
+SETCCm_EVEX 1606
+SETCCr 1607
+SETCCr_EVEX 1608
+SETSSBSY 1609
+SETZUCCm 1610
+SETZUCCr 1611
+SFENCE 1612
+SGDT 1613
+SHA 1614
+SHL 1615
+SHLD 1616
+SHLDROT 1617
+SHLX 1618
+SHR 1619
+SHRD 1620
+SHRDROT 1621
+SHRX 1622
+SHUFPDrmi 1623
+SHUFPDrri 1624
+SHUFPSrmi 1625
+SHUFPSrri 1626
+SIDT 1627
+SKINIT 1628
+SLDT 1629
+SLWPCB 1630
+SMSW 1631
+SQRTPDm 1632
+SQRTPDr 1633
+SQRTPSm 1634
+SQRTPSr 1635
+SQRTSDm 1636
+SQRTSDm_Int 1637
+SQRTSDr 1638
+SQRTSDr_Int 1639
+SQRTSSm 1640
+SQRTSSm_Int 1641
+SQRTSSr 1642
+SQRTSSr_Int 1643
+SQRT_F 1644
+SQRT_Fp 1645
+SS_PREFIX 1646
+STAC 1647
+STACKALLOC_W_PROBING 1648
+STACKMAP 1649
+STATEPOINT 1650
+STC 1651
+STD 1652
+STGI 1653
+STI 1654
+STMXCSR 1655
+STOSB 1656
+STOSL 1657
+STOSQ 1658
+STOSW 1659
+STR 1660
+STRm 1661
+STTILECFG 1662
+STTILECFG_EVEX 1663
+STUI 1664
+ST_F 1665
+ST_FP 1666
+ST_FPrr 1667
+ST_Fp 1668
+ST_FpP 1669
+ST_Frr 1670
+SUB 1671
+SUBPDrm 1672
+SUBPDrr 1673
+SUBPSrm 1674
+SUBPSrr 1675
+SUBREG_TO_REG 1676
+SUBR_F 1677
+SUBR_FI 1678
+SUBR_FPrST 1679
+SUBR_FST 1680
+SUBR_Fp 1681
+SUBR_FpI 1682
+SUBR_FrST 1683
+SUBSDrm 1684
+SUBSDrm_Int 1685
+SUBSDrr 1686
+SUBSDrr_Int 1687
+SUBSSrm 1688
+SUBSSrm_Int 1689
+SUBSSrr 1690
+SUBSSrr_Int 1691
+SUB_F 1692
+SUB_FI 1693
+SUB_FPrST 1694
+SUB_FST 1695
+SUB_Fp 1696
+SUB_FpI 1697
+SUB_FrST 1698
+SWAPGS 1699
+SYSCALL 1700
+SYSENTER 1701
+SYSEXIT 1702
+SYSRET 1703
+T 1704
+TAILJMPd 1705
+TAILJMPd_CC 1706
+TAILJMPm 1707
+TAILJMPr 1708
+TCMMIMFP 1709
+TCMMRLFP 1710
+TCRETURN_HIPE 1711
+TCRETURN_WIN 1712
+TCRETURN_WINmi 1713
+TCRETURNdi 1714
+TCRETURNdicc 1715
+TCRETURNmi 1716
+TCRETURNri 1717
+TCVTROWD 1718
+TCVTROWPS 1719
+TDCALL 1720
+TDPBF 1721
+TDPBHF 1722
+TDPBSSD 1723
+TDPBSUD 1724
+TDPBUSD 1725
+TDPBUUD 1726
+TDPFP 1727
+TDPHBF 1728
+TDPHF 1729
+TEST 1730
+TESTUI 1731
+TILELOADD 1732
+TILELOADDRS 1733
+TILELOADDRST 1734
+TILELOADDRS_EVEX 1735
+TILELOADDT 1736
+TILELOADD_EVEX 1737
+TILEMOVROWrre 1738
+TILEMOVROWrri 1739
+TILERELEASE 1740
+TILESTORED 1741
+TILESTORED_EVEX 1742
+TILEZERO 1743
+TLBSYNC 1744
+TLSCall 1745
+TLS_addr 1746
+TLS_addrX 1747
+TLS_base_addr 1748
+TLS_base_addrX 1749
+TLS_desc 1750
+TMMULTF 1751
+TPAUSE 1752
+TRAP 1753
+TST_F 1754
+TST_Fp 1755
+TZCNT 1756
+TZMSK 1757
+UBSAN_UD 1758
+UCOMISDrm 1759
+UCOMISDrm_Int 1760
+UCOMISDrr 1761
+UCOMISDrr_Int 1762
+UCOMISSrm 1763
+UCOMISSrm_Int 1764
+UCOMISSrr 1765
+UCOMISSrr_Int 1766
+UCOM_FIPr 1767
+UCOM_FIr 1768
+UCOM_FPPr 1769
+UCOM_FPr 1770
+UCOM_FpIr 1771
+UCOM_Fpr 1772
+UCOM_Fr 1773
+UD 1774
+UIRET 1775
+UMONITOR 1776
+UMWAIT 1777
+UNPCKHPDrm 1778
+UNPCKHPDrr 1779
+UNPCKHPSrm 1780
+UNPCKHPSrr 1781
+UNPCKLPDrm 1782
+UNPCKLPDrr 1783
+UNPCKLPSrm 1784
+UNPCKLPSrr 1785
+URDMSRri 1786
+URDMSRri_EVEX 1787
+URDMSRrr 1788
+URDMSRrr_EVEX 1789
+UWRMSRir 1790
+UWRMSRir_EVEX 1791
+UWRMSRrr 1792
+UWRMSRrr_EVEX 1793
+V 1794
+VAARG 1795
+VAARG_X 1796
+VADDBF 1797
+VADDPDYrm 1798
+VADDPDYrr 1799
+VADDPDZ 1800
+VADDPDZrm 1801
+VADDPDZrmb 1802
+VADDPDZrmbk 1803
+VADDPDZrmbkz 1804
+VADDPDZrmk 1805
+VADDPDZrmkz 1806
+VADDPDZrr 1807
+VADDPDZrrb 1808
+VADDPDZrrbk 1809
+VADDPDZrrbkz 1810
+VADDPDZrrk 1811
+VADDPDZrrkz 1812
+VADDPDrm 1813
+VADDPDrr 1814
+VADDPHZ 1815
+VADDPHZrm 1816
+VADDPHZrmb 1817
+VADDPHZrmbk 1818
+VADDPHZrmbkz 1819
+VADDPHZrmk 1820
+VADDPHZrmkz 1821
+VADDPHZrr 1822
+VADDPHZrrb 1823
+VADDPHZrrbk 1824
+VADDPHZrrbkz 1825
+VADDPHZrrk 1826
+VADDPHZrrkz 1827
+VADDPSYrm 1828
+VADDPSYrr 1829
+VADDPSZ 1830
+VADDPSZrm 1831
+VADDPSZrmb 1832
+VADDPSZrmbk 1833
+VADDPSZrmbkz 1834
+VADDPSZrmk 1835
+VADDPSZrmkz 1836
+VADDPSZrr 1837
+VADDPSZrrb 1838
+VADDPSZrrbk 1839
+VADDPSZrrbkz 1840
+VADDPSZrrk 1841
+VADDPSZrrkz 1842
+VADDPSrm 1843
+VADDPSrr 1844
+VADDSDZrm 1845
+VADDSDZrm_Int 1846
+VADDSDZrmk_Int 1847
+VADDSDZrmkz_Int 1848
+VADDSDZrr 1849
+VADDSDZrr_Int 1850
+VADDSDZrrb_Int 1851
+VADDSDZrrbk_Int 1852
+VADDSDZrrbkz_Int 1853
+VADDSDZrrk_Int 1854
+VADDSDZrrkz_Int 1855
+VADDSDrm 1856
+VADDSDrm_Int 1857
+VADDSDrr 1858
+VADDSDrr_Int 1859
+VADDSHZrm 1860
+VADDSHZrm_Int 1861
+VADDSHZrmk_Int 1862
+VADDSHZrmkz_Int 1863
+VADDSHZrr 1864
+VADDSHZrr_Int 1865
+VADDSHZrrb_Int 1866
+VADDSHZrrbk_Int 1867
+VADDSHZrrbkz_Int 1868
+VADDSHZrrk_Int 1869
+VADDSHZrrkz_Int 1870
+VADDSSZrm 1871
+VADDSSZrm_Int 1872
+VADDSSZrmk_Int 1873
+VADDSSZrmkz_Int 1874
+VADDSSZrr 1875
+VADDSSZrr_Int 1876
+VADDSSZrrb_Int 1877
+VADDSSZrrbk_Int 1878
+VADDSSZrrbkz_Int 1879
+VADDSSZrrk_Int 1880
+VADDSSZrrkz_Int 1881
+VADDSSrm 1882
+VADDSSrm_Int 1883
+VADDSSrr 1884
+VADDSSrr_Int 1885
+VADDSUBPDYrm 1886
+VADDSUBPDYrr 1887
+VADDSUBPDrm 1888
+VADDSUBPDrr 1889
+VADDSUBPSYrm 1890
+VADDSUBPSYrr 1891
+VADDSUBPSrm 1892
+VADDSUBPSrr 1893
+VAESDECLASTYrm 1894
+VAESDECLASTYrr 1895
+VAESDECLASTZ 1896
+VAESDECLASTZrm 1897
+VAESDECLASTZrr 1898
+VAESDECLASTrm 1899
+VAESDECLASTrr 1900
+VAESDECYrm 1901
+VAESDECYrr 1902
+VAESDECZ 1903
+VAESDECZrm 1904
+VAESDECZrr 1905
+VAESDECrm 1906
+VAESDECrr 1907
+VAESENCLASTYrm 1908
+VAESENCLASTYrr 1909
+VAESENCLASTZ 1910
+VAESENCLASTZrm 1911
+VAESENCLASTZrr 1912
+VAESENCLASTrm 1913
+VAESENCLASTrr 1914
+VAESENCYrm 1915
+VAESENCYrr 1916
+VAESENCZ 1917
+VAESENCZrm 1918
+VAESENCZrr 1919
+VAESENCrm 1920
+VAESENCrr 1921
+VAESIMCrm 1922
+VAESIMCrr 1923
+VAESKEYGENASSISTrmi 1924
+VAESKEYGENASSISTrri 1925
+VALIGNDZ 1926
+VALIGNDZrmbi 1927
+VALIGNDZrmbik 1928
+VALIGNDZrmbikz 1929
+VALIGNDZrmi 1930
+VALIGNDZrmik 1931
+VALIGNDZrmikz 1932
+VALIGNDZrri 1933
+VALIGNDZrrik 1934
+VALIGNDZrrikz 1935
+VALIGNQZ 1936
+VALIGNQZrmbi 1937
+VALIGNQZrmbik 1938
+VALIGNQZrmbikz 1939
+VALIGNQZrmi 1940
+VALIGNQZrmik 1941
+VALIGNQZrmikz 1942
+VALIGNQZrri 1943
+VALIGNQZrrik 1944
+VALIGNQZrrikz 1945
+VANDNPDYrm 1946
+VANDNPDYrr 1947
+VANDNPDZ 1948
+VANDNPDZrm 1949
+VANDNPDZrmb 1950
+VANDNPDZrmbk 1951
+VANDNPDZrmbkz 1952
+VANDNPDZrmk 1953
+VANDNPDZrmkz 1954
+VANDNPDZrr 1955
+VANDNPDZrrk 1956
+VANDNPDZrrkz 1957
+VANDNPDrm 1958
+VANDNPDrr 1959
+VANDNPSYrm 1960
+VANDNPSYrr 1961
+VANDNPSZ 1962
+VANDNPSZrm 1963
+VANDNPSZrmb 1964
+VANDNPSZrmbk 1965
+VANDNPSZrmbkz 1966
+VANDNPSZrmk 1967
+VANDNPSZrmkz 1968
+VANDNPSZrr 1969
+VANDNPSZrrk 1970
+VANDNPSZrrkz 1971
+VANDNPSrm 1972
+VANDNPSrr 1973
+VANDPDYrm 1974
+VANDPDYrr 1975
+VANDPDZ 1976
+VANDPDZrm 1977
+VANDPDZrmb 1978
+VANDPDZrmbk 1979
+VANDPDZrmbkz 1980
+VANDPDZrmk 1981
+VANDPDZrmkz 1982
+VANDPDZrr 1983
+VANDPDZrrk 1984
+VANDPDZrrkz 1985
+VANDPDrm 1986
+VANDPDrr 1987
+VANDPSYrm 1988
+VANDPSYrr 1989
+VANDPSZ 1990
+VANDPSZrm 1991
+VANDPSZrmb 1992
+VANDPSZrmbk 1993
+VANDPSZrmbkz 1994
+VANDPSZrmk 1995
+VANDPSZrmkz 1996
+VANDPSZrr 1997
+VANDPSZrrk 1998
+VANDPSZrrkz 1999
+VANDPSrm 2000
+VANDPSrr 2001
+VASTART_SAVE_XMM_REGS 2002
+VBCSTNEBF 2003
+VBCSTNESH 2004
+VBLENDMPDZ 2005
+VBLENDMPDZrm 2006
+VBLENDMPDZrmb 2007
+VBLENDMPDZrmbk 2008
+VBLENDMPDZrmbkz 2009
+VBLENDMPDZrmk 2010
+VBLENDMPDZrmkz 2011
+VBLENDMPDZrr 2012
+VBLENDMPDZrrk 2013
+VBLENDMPDZrrkz 2014
+VBLENDMPSZ 2015
+VBLENDMPSZrm 2016
+VBLENDMPSZrmb 2017
+VBLENDMPSZrmbk 2018
+VBLENDMPSZrmbkz 2019
+VBLENDMPSZrmk 2020
+VBLENDMPSZrmkz 2021
+VBLENDMPSZrr 2022
+VBLENDMPSZrrk 2023
+VBLENDMPSZrrkz 2024
+VBLENDPDYrmi 2025
+VBLENDPDYrri 2026
+VBLENDPDrmi 2027
+VBLENDPDrri 2028
+VBLENDPSYrmi 2029
+VBLENDPSYrri 2030
+VBLENDPSrmi 2031
+VBLENDPSrri 2032
+VBLENDVPDYrmr 2033
+VBLENDVPDYrrr 2034
+VBLENDVPDrmr 2035
+VBLENDVPDrrr 2036
+VBLENDVPSYrmr 2037
+VBLENDVPSYrrr 2038
+VBLENDVPSrmr 2039
+VBLENDVPSrrr 2040
+VBROADCASTF 2041
+VBROADCASTI 2042
+VBROADCASTSDYrm 2043
+VBROADCASTSDYrr 2044
+VBROADCASTSDZ 2045
+VBROADCASTSDZrm 2046
+VBROADCASTSDZrmk 2047
+VBROADCASTSDZrmkz 2048
+VBROADCASTSDZrr 2049
+VBROADCASTSDZrrk 2050
+VBROADCASTSDZrrkz 2051
+VBROADCASTSSYrm 2052
+VBROADCASTSSYrr 2053
+VBROADCASTSSZ 2054
+VBROADCASTSSZrm 2055
+VBROADCASTSSZrmk 2056
+VBROADCASTSSZrmkz 2057
+VBROADCASTSSZrr 2058
+VBROADCASTSSZrrk 2059
+VBROADCASTSSZrrkz 2060
+VBROADCASTSSrm 2061
+VBROADCASTSSrr 2062
+VCMPBF 2063
+VCMPPDYrmi 2064
+VCMPPDYrri 2065
+VCMPPDZ 2066
+VCMPPDZrmbi 2067
+VCMPPDZrmbik 2068
+VCMPPDZrmi 2069
+VCMPPDZrmik 2070
+VCMPPDZrri 2071
+VCMPPDZrrib 2072
+VCMPPDZrribk 2073
+VCMPPDZrrik 2074
+VCMPPDrmi 2075
+VCMPPDrri 2076
+VCMPPHZ 2077
+VCMPPHZrmbi 2078
+VCMPPHZrmbik 2079
+VCMPPHZrmi 2080
+VCMPPHZrmik 2081
+VCMPPHZrri 2082
+VCMPPHZrrib 2083
+VCMPPHZrribk 2084
+VCMPPHZrrik 2085
+VCMPPSYrmi 2086
+VCMPPSYrri 2087
+VCMPPSZ 2088
+VCMPPSZrmbi 2089
+VCMPPSZrmbik 2090
+VCMPPSZrmi 2091
+VCMPPSZrmik 2092
+VCMPPSZrri 2093
+VCMPPSZrrib 2094
+VCMPPSZrribk 2095
+VCMPPSZrrik 2096
+VCMPPSrmi 2097
+VCMPPSrri 2098
+VCMPSDZrmi 2099
+VCMPSDZrmi_Int 2100
+VCMPSDZrmik_Int 2101
+VCMPSDZrri 2102
+VCMPSDZrri_Int 2103
+VCMPSDZrrib_Int 2104
+VCMPSDZrribk_Int 2105
+VCMPSDZrrik_Int 2106
+VCMPSDrmi 2107
+VCMPSDrmi_Int 2108
+VCMPSDrri 2109
+VCMPSDrri_Int 2110
+VCMPSHZrmi 2111
+VCMPSHZrmi_Int 2112
+VCMPSHZrmik_Int 2113
+VCMPSHZrri 2114
+VCMPSHZrri_Int 2115
+VCMPSHZrrib_Int 2116
+VCMPSHZrribk_Int 2117
+VCMPSHZrrik_Int 2118
+VCMPSSZrmi 2119
+VCMPSSZrmi_Int 2120
+VCMPSSZrmik_Int 2121
+VCMPSSZrri 2122
+VCMPSSZrri_Int 2123
+VCMPSSZrrib_Int 2124
+VCMPSSZrribk_Int 2125
+VCMPSSZrrik_Int 2126
+VCMPSSrmi 2127
+VCMPSSrmi_Int 2128
+VCMPSSrri 2129
+VCMPSSrri_Int 2130
+VCOMISBF 2131
+VCOMISDZrm 2132
+VCOMISDZrm_Int 2133
+VCOMISDZrr 2134
+VCOMISDZrr_Int 2135
+VCOMISDZrrb 2136
+VCOMISDrm 2137
+VCOMISDrm_Int 2138
+VCOMISDrr 2139
+VCOMISDrr_Int 2140
+VCOMISHZrm 2141
+VCOMISHZrm_Int 2142
+VCOMISHZrr 2143
+VCOMISHZrr_Int 2144
+VCOMISHZrrb 2145
+VCOMISSZrm 2146
+VCOMISSZrm_Int 2147
+VCOMISSZrr 2148
+VCOMISSZrr_Int 2149
+VCOMISSZrrb 2150
+VCOMISSrm 2151
+VCOMISSrm_Int 2152
+VCOMISSrr 2153
+VCOMISSrr_Int 2154
+VCOMPRESSPDZ 2155
+VCOMPRESSPDZmr 2156
+VCOMPRESSPDZmrk 2157
+VCOMPRESSPDZrr 2158
+VCOMPRESSPDZrrk 2159
+VCOMPRESSPDZrrkz 2160
+VCOMPRESSPSZ 2161
+VCOMPRESSPSZmr 2162
+VCOMPRESSPSZmrk 2163
+VCOMPRESSPSZrr 2164
+VCOMPRESSPSZrrk 2165
+VCOMPRESSPSZrrkz 2166
+VCOMXSDZrm_Int 2167
+VCOMXSDZrr_Int 2168
+VCOMXSDZrrb_Int 2169
+VCOMXSHZrm_Int 2170
+VCOMXSHZrr_Int 2171
+VCOMXSHZrrb_Int 2172
+VCOMXSSZrm_Int 2173
+VCOMXSSZrr_Int 2174
+VCOMXSSZrrb_Int 2175
+VCVT 2176
+VCVTBF 2177
+VCVTBIASPH 2178
+VCVTDQ 2179
+VCVTHF 2180
+VCVTNE 2181
+VCVTNEEBF 2182
+VCVTNEEPH 2183
+VCVTNEOBF 2184
+VCVTNEOPH 2185
+VCVTNEPS 2186
+VCVTPD 2187
+VCVTPH 2188
+VCVTPS 2189
+VCVTQQ 2190
+VCVTSD 2191
+VCVTSH 2192
+VCVTSI 2193
+VCVTSS 2194
+VCVTTBF 2195
+VCVTTPD 2196
+VCVTTPH 2197
+VCVTTPS 2198
+VCVTTSD 2199
+VCVTTSH 2200
+VCVTTSS 2201
+VCVTUDQ 2202
+VCVTUQQ 2203
+VCVTUSI 2204
+VCVTUW 2205
+VCVTW 2206
+VDBPSADBWZ 2207
+VDBPSADBWZrmi 2208
+VDBPSADBWZrmik 2209
+VDBPSADBWZrmikz 2210
+VDBPSADBWZrri 2211
+VDBPSADBWZrrik 2212
+VDBPSADBWZrrikz 2213
+VDIVBF 2214
+VDIVPDYrm 2215
+VDIVPDYrr 2216
+VDIVPDZ 2217
+VDIVPDZrm 2218
+VDIVPDZrmb 2219
+VDIVPDZrmbk 2220
+VDIVPDZrmbkz 2221
+VDIVPDZrmk 2222
+VDIVPDZrmkz 2223
+VDIVPDZrr 2224
+VDIVPDZrrb 2225
+VDIVPDZrrbk 2226
+VDIVPDZrrbkz 2227
+VDIVPDZrrk 2228
+VDIVPDZrrkz 2229
+VDIVPDrm 2230
+VDIVPDrr 2231
+VDIVPHZ 2232
+VDIVPHZrm 2233
+VDIVPHZrmb 2234
+VDIVPHZrmbk 2235
+VDIVPHZrmbkz 2236
+VDIVPHZrmk 2237
+VDIVPHZrmkz 2238
+VDIVPHZrr 2239
+VDIVPHZrrb 2240
+VDIVPHZrrbk 2241
+VDIVPHZrrbkz 2242
+VDIVPHZrrk 2243
+VDIVPHZrrkz 2244
+VDIVPSYrm 2245
+VDIVPSYrr 2246
+VDIVPSZ 2247
+VDIVPSZrm 2248
+VDIVPSZrmb 2249
+VDIVPSZrmbk 2250
+VDIVPSZrmbkz 2251
+VDIVPSZrmk 2252
+VDIVPSZrmkz 2253
+VDIVPSZrr 2254
+VDIVPSZrrb 2255
+VDIVPSZrrbk 2256
+VDIVPSZrrbkz 2257
+VDIVPSZrrk 2258
+VDIVPSZrrkz 2259
+VDIVPSrm 2260
+VDIVPSrr 2261
+VDIVSDZrm 2262
+VDIVSDZrm_Int 2263
+VDIVSDZrmk_Int 2264
+VDIVSDZrmkz_Int 2265
+VDIVSDZrr 2266
+VDIVSDZrr_Int 2267
+VDIVSDZrrb_Int 2268
+VDIVSDZrrbk_Int 2269
+VDIVSDZrrbkz_Int 2270
+VDIVSDZrrk_Int 2271
+VDIVSDZrrkz_Int 2272
+VDIVSDrm 2273
+VDIVSDrm_Int 2274
+VDIVSDrr 2275
+VDIVSDrr_Int 2276
+VDIVSHZrm 2277
+VDIVSHZrm_Int 2278
+VDIVSHZrmk_Int 2279
+VDIVSHZrmkz_Int 2280
+VDIVSHZrr 2281
+VDIVSHZrr_Int 2282
+VDIVSHZrrb_Int 2283
+VDIVSHZrrbk_Int 2284
+VDIVSHZrrbkz_Int 2285
+VDIVSHZrrk_Int 2286
+VDIVSHZrrkz_Int 2287
+VDIVSSZrm 2288
+VDIVSSZrm_Int 2289
+VDIVSSZrmk_Int 2290
+VDIVSSZrmkz_Int 2291
+VDIVSSZrr 2292
+VDIVSSZrr_Int 2293
+VDIVSSZrrb_Int 2294
+VDIVSSZrrbk_Int 2295
+VDIVSSZrrbkz_Int 2296
+VDIVSSZrrk_Int 2297
+VDIVSSZrrkz_Int 2298
+VDIVSSrm 2299
+VDIVSSrm_Int 2300
+VDIVSSrr 2301
+VDIVSSrr_Int 2302
+VDPBF 2303
+VDPPDrmi 2304
+VDPPDrri 2305
+VDPPHPSZ 2306
+VDPPHPSZm 2307
+VDPPHPSZmb 2308
+VDPPHPSZmbk 2309
+VDPPHPSZmbkz 2310
+VDPPHPSZmk 2311
+VDPPHPSZmkz 2312
+VDPPHPSZr 2313
+VDPPHPSZrk 2314
+VDPPHPSZrkz 2315
+VDPPSYrmi 2316
+VDPPSYrri 2317
+VDPPSrmi 2318
+VDPPSrri 2319
+VERRm 2320
+VERRr 2321
+VERWm 2322
+VERWr 2323
+VEXP 2324
+VEXPANDPDZ 2325
+VEXPANDPDZrm 2326
+VEXPANDPDZrmk 2327
+VEXPANDPDZrmkz 2328
+VEXPANDPDZrr 2329
+VEXPANDPDZrrk 2330
+VEXPANDPDZrrkz 2331
+VEXPANDPSZ 2332
+VEXPANDPSZrm 2333
+VEXPANDPSZrmk 2334
+VEXPANDPSZrmkz 2335
+VEXPANDPSZrr 2336
+VEXPANDPSZrrk 2337
+VEXPANDPSZrrkz 2338
+VEXTRACTF 2339
+VEXTRACTI 2340
+VEXTRACTPSZmri 2341
+VEXTRACTPSZrri 2342
+VEXTRACTPSmri 2343
+VEXTRACTPSrri 2344
+VFCMADDCPHZ 2345
+VFCMADDCPHZm 2346
+VFCMADDCPHZmb 2347
+VFCMADDCPHZmbk 2348
+VFCMADDCPHZmbkz 2349
+VFCMADDCPHZmk 2350
+VFCMADDCPHZmkz 2351
+VFCMADDCPHZr 2352
+VFCMADDCPHZrb 2353
+VFCMADDCPHZrbk 2354
+VFCMADDCPHZrbkz 2355
+VFCMADDCPHZrk 2356
+VFCMADDCPHZrkz 2357
+VFCMADDCSHZm 2358
+VFCMADDCSHZmk 2359
+VFCMADDCSHZmkz 2360
+VFCMADDCSHZr 2361
+VFCMADDCSHZrb 2362
+VFCMADDCSHZrbk 2363
+VFCMADDCSHZrbkz 2364
+VFCMADDCSHZrk 2365
+VFCMADDCSHZrkz 2366
+VFCMULCPHZ 2367
+VFCMULCPHZrm 2368
+VFCMULCPHZrmb 2369
+VFCMULCPHZrmbk 2370
+VFCMULCPHZrmbkz 2371
+VFCMULCPHZrmk 2372
+VFCMULCPHZrmkz 2373
+VFCMULCPHZrr 2374
+VFCMULCPHZrrb 2375
+VFCMULCPHZrrbk 2376
+VFCMULCPHZrrbkz 2377
+VFCMULCPHZrrk 2378
+VFCMULCPHZrrkz 2379
+VFCMULCSHZrm 2380
+VFCMULCSHZrmk 2381
+VFCMULCSHZrmkz 2382
+VFCMULCSHZrr 2383
+VFCMULCSHZrrb 2384
+VFCMULCSHZrrbk 2385
+VFCMULCSHZrrbkz 2386
+VFCMULCSHZrrk 2387
+VFCMULCSHZrrkz 2388
+VFIXUPIMMPDZ 2389
+VFIXUPIMMPDZrmbi 2390
+VFIXUPIMMPDZrmbik 2391
+VFIXUPIMMPDZrmbikz 2392
+VFIXUPIMMPDZrmi 2393
+VFIXUPIMMPDZrmik 2394
+VFIXUPIMMPDZrmikz 2395
+VFIXUPIMMPDZrri 2396
+VFIXUPIMMPDZrrib 2397
+VFIXUPIMMPDZrribk 2398
+VFIXUPIMMPDZrribkz 2399
+VFIXUPIMMPDZrrik 2400
+VFIXUPIMMPDZrrikz 2401
+VFIXUPIMMPSZ 2402
+VFIXUPIMMPSZrmbi 2403
+VFIXUPIMMPSZrmbik 2404
+VFIXUPIMMPSZrmbikz 2405
+VFIXUPIMMPSZrmi 2406
+VFIXUPIMMPSZrmik 2407
+VFIXUPIMMPSZrmikz 2408
+VFIXUPIMMPSZrri 2409
+VFIXUPIMMPSZrrib 2410
+VFIXUPIMMPSZrribk 2411
+VFIXUPIMMPSZrribkz 2412
+VFIXUPIMMPSZrrik 2413
+VFIXUPIMMPSZrrikz 2414
+VFIXUPIMMSDZrmi 2415
+VFIXUPIMMSDZrmik 2416
+VFIXUPIMMSDZrmikz 2417
+VFIXUPIMMSDZrri 2418
+VFIXUPIMMSDZrrib 2419
+VFIXUPIMMSDZrribk 2420
+VFIXUPIMMSDZrribkz 2421
+VFIXUPIMMSDZrrik 2422
+VFIXUPIMMSDZrrikz 2423
+VFIXUPIMMSSZrmi 2424
+VFIXUPIMMSSZrmik 2425
+VFIXUPIMMSSZrmikz 2426
+VFIXUPIMMSSZrri 2427
+VFIXUPIMMSSZrrib 2428
+VFIXUPIMMSSZrribk 2429
+VFIXUPIMMSSZrribkz 2430
+VFIXUPIMMSSZrrik 2431
+VFIXUPIMMSSZrrikz 2432
+VFMADD 2433
+VFMADDCPHZ 2434
+VFMADDCPHZm 2435
+VFMADDCPHZmb 2436
+VFMADDCPHZmbk 2437
+VFMADDCPHZmbkz 2438
+VFMADDCPHZmk 2439
+VFMADDCPHZmkz 2440
+VFMADDCPHZr 2441
+VFMADDCPHZrb 2442
+VFMADDCPHZrbk 2443
+VFMADDCPHZrbkz 2444
+VFMADDCPHZrk 2445
+VFMADDCPHZrkz 2446
+VFMADDCSHZm 2447
+VFMADDCSHZmk 2448
+VFMADDCSHZmkz 2449
+VFMADDCSHZr 2450
+VFMADDCSHZrb 2451
+VFMADDCSHZrbk 2452
+VFMADDCSHZrbkz 2453
+VFMADDCSHZrk 2454
+VFMADDCSHZrkz 2455
+VFMADDPD 2456
+VFMADDPS 2457
+VFMADDSD 2458
+VFMADDSS 2459
+VFMADDSUB 2460
+VFMADDSUBPD 2461
+VFMADDSUBPS 2462
+VFMSUB 2463
+VFMSUBADD 2464
+VFMSUBADDPD 2465
+VFMSUBADDPS 2466
+VFMSUBPD 2467
+VFMSUBPS 2468
+VFMSUBSD 2469
+VFMSUBSS 2470
+VFMULCPHZ 2471
+VFMULCPHZrm 2472
+VFMULCPHZrmb 2473
+VFMULCPHZrmbk 2474
+VFMULCPHZrmbkz 2475
+VFMULCPHZrmk 2476
+VFMULCPHZrmkz 2477
+VFMULCPHZrr 2478
+VFMULCPHZrrb 2479
+VFMULCPHZrrbk 2480
+VFMULCPHZrrbkz 2481
+VFMULCPHZrrk 2482
+VFMULCPHZrrkz 2483
+VFMULCSHZrm 2484
+VFMULCSHZrmk 2485
+VFMULCSHZrmkz 2486
+VFMULCSHZrr 2487
+VFMULCSHZrrb 2488
+VFMULCSHZrrbk 2489
+VFMULCSHZrrbkz 2490
+VFMULCSHZrrk 2491
+VFMULCSHZrrkz 2492
+VFNMADD 2493
+VFNMADDPD 2494
+VFNMADDPS 2495
+VFNMADDSD 2496
+VFNMADDSS 2497
+VFNMSUB 2498
+VFNMSUBPD 2499
+VFNMSUBPS 2500
+VFNMSUBSD 2501
+VFNMSUBSS 2502
+VFPCLASSBF 2503
+VFPCLASSPDZ 2504
+VFPCLASSPDZmbi 2505
+VFPCLASSPDZmbik 2506
+VFPCLASSPDZmi 2507
+VFPCLASSPDZmik 2508
+VFPCLASSPDZri 2509
+VFPCLASSPDZrik 2510
+VFPCLASSPHZ 2511
+VFPCLASSPHZmbi 2512
+VFPCLASSPHZmbik 2513
+VFPCLASSPHZmi 2514
+VFPCLASSPHZmik 2515
+VFPCLASSPHZri 2516
+VFPCLASSPHZrik 2517
+VFPCLASSPSZ 2518
+VFPCLASSPSZmbi 2519
+VFPCLASSPSZmbik 2520
+VFPCLASSPSZmi 2521
+VFPCLASSPSZmik 2522
+VFPCLASSPSZri 2523
+VFPCLASSPSZrik 2524
+VFPCLASSSDZmi 2525
+VFPCLASSSDZmik 2526
+VFPCLASSSDZri 2527
+VFPCLASSSDZrik 2528
+VFPCLASSSHZmi 2529
+VFPCLASSSHZmik 2530
+VFPCLASSSHZri 2531
+VFPCLASSSHZrik 2532
+VFPCLASSSSZmi 2533
+VFPCLASSSSZmik 2534
+VFPCLASSSSZri 2535
+VFPCLASSSSZrik 2536
+VFRCZPDYrm 2537
+VFRCZPDYrr 2538
+VFRCZPDrm 2539
+VFRCZPDrr 2540
+VFRCZPSYrm 2541
+VFRCZPSYrr 2542
+VFRCZPSrm 2543
+VFRCZPSrr 2544
+VFRCZSDrm 2545
+VFRCZSDrr 2546
+VFRCZSSrm 2547
+VFRCZSSrr 2548
+VGATHERDPDYrm 2549
+VGATHERDPDZ 2550
+VGATHERDPDZrm 2551
+VGATHERDPDrm 2552
+VGATHERDPSYrm 2553
+VGATHERDPSZ 2554
+VGATHERDPSZrm 2555
+VGATHERDPSrm 2556
+VGATHERPF 2557
+VGATHERQPDYrm 2558
+VGATHERQPDZ 2559
+VGATHERQPDZrm 2560
+VGATHERQPDrm 2561
+VGATHERQPSYrm 2562
+VGATHERQPSZ 2563
+VGATHERQPSZrm 2564
+VGATHERQPSrm 2565
+VGETEXPBF 2566
+VGETEXPPDZ 2567
+VGETEXPPDZm 2568
+VGETEXPPDZmb 2569
+VGETEXPPDZmbk 2570
+VGETEXPPDZmbkz 2571
+VGETEXPPDZmk 2572
+VGETEXPPDZmkz 2573
+VGETEXPPDZr 2574
+VGETEXPPDZrb 2575
+VGETEXPPDZrbk 2576
+VGETEXPPDZrbkz 2577
+VGETEXPPDZrk 2578
+VGETEXPPDZrkz 2579
+VGETEXPPHZ 2580
+VGETEXPPHZm 2581
+VGETEXPPHZmb 2582
+VGETEXPPHZmbk 2583
+VGETEXPPHZmbkz 2584
+VGETEXPPHZmk 2585
+VGETEXPPHZmkz 2586
+VGETEXPPHZr 2587
+VGETEXPPHZrb 2588
+VGETEXPPHZrbk 2589
+VGETEXPPHZrbkz 2590
+VGETEXPPHZrk 2591
+VGETEXPPHZrkz 2592
+VGETEXPPSZ 2593
+VGETEXPPSZm 2594
+VGETEXPPSZmb 2595
+VGETEXPPSZmbk 2596
+VGETEXPPSZmbkz 2597
+VGETEXPPSZmk 2598
+VGETEXPPSZmkz 2599
+VGETEXPPSZr 2600
+VGETEXPPSZrb 2601
+VGETEXPPSZrbk 2602
+VGETEXPPSZrbkz 2603
+VGETEXPPSZrk 2604
+VGETEXPPSZrkz 2605
+VGETEXPSDZm 2606
+VGETEXPSDZmk 2607
+VGETEXPSDZmkz 2608
+VGETEXPSDZr 2609
+VGETEXPSDZrb 2610
+VGETEXPSDZrbk 2611
+VGETEXPSDZrbkz 2612
+VGETEXPSDZrk 2613
+VGETEXPSDZrkz 2614
+VGETEXPSHZm 2615
+VGETEXPSHZmk 2616
+VGETEXPSHZmkz 2617
+VGETEXPSHZr 2618
+VGETEXPSHZrb 2619
+VGETEXPSHZrbk 2620
+VGETEXPSHZrbkz 2621
+VGETEXPSHZrk 2622
+VGETEXPSHZrkz 2623
+VGETEXPSSZm 2624
+VGETEXPSSZmk 2625
+VGETEXPSSZmkz 2626
+VGETEXPSSZr 2627
+VGETEXPSSZrb 2628
+VGETEXPSSZrbk 2629
+VGETEXPSSZrbkz 2630
+VGETEXPSSZrk 2631
+VGETEXPSSZrkz 2632
+VGETMANTBF 2633
+VGETMANTPDZ 2634
+VGETMANTPDZrmbi 2635
+VGETMANTPDZrmbik 2636
+VGETMANTPDZrmbikz 2637
+VGETMANTPDZrmi 2638
+VGETMANTPDZrmik 2639
+VGETMANTPDZrmikz 2640
+VGETMANTPDZrri 2641
+VGETMANTPDZrrib 2642
+VGETMANTPDZrribk 2643
+VGETMANTPDZrribkz 2644
+VGETMANTPDZrrik 2645
+VGETMANTPDZrrikz 2646
+VGETMANTPHZ 2647
+VGETMANTPHZrmbi 2648
+VGETMANTPHZrmbik 2649
+VGETMANTPHZrmbikz 2650
+VGETMANTPHZrmi 2651
+VGETMANTPHZrmik 2652
+VGETMANTPHZrmikz 2653
+VGETMANTPHZrri 2654
+VGETMANTPHZrrib 2655
+VGETMANTPHZrribk 2656
+VGETMANTPHZrribkz 2657
+VGETMANTPHZrrik 2658
+VGETMANTPHZrrikz 2659
+VGETMANTPSZ 2660
+VGETMANTPSZrmbi 2661
+VGETMANTPSZrmbik 2662
+VGETMANTPSZrmbikz 2663
+VGETMANTPSZrmi 2664
+VGETMANTPSZrmik 2665
+VGETMANTPSZrmikz 2666
+VGETMANTPSZrri 2667
+VGETMANTPSZrrib 2668
+VGETMANTPSZrribk 2669
+VGETMANTPSZrribkz 2670
+VGETMANTPSZrrik 2671
+VGETMANTPSZrrikz 2672
+VGETMANTSDZrmi 2673
+VGETMANTSDZrmik 2674
+VGETMANTSDZrmikz 2675
+VGETMANTSDZrri 2676
+VGETMANTSDZrrib 2677
+VGETMANTSDZrribk 2678
+VGETMANTSDZrribkz 2679
+VGETMANTSDZrrik 2680
+VGETMANTSDZrrikz 2681
+VGETMANTSHZrmi 2682
+VGETMANTSHZrmik 2683
+VGETMANTSHZrmikz 2684
+VGETMANTSHZrri 2685
+VGETMANTSHZrrib 2686
+VGETMANTSHZrribk 2687
+VGETMANTSHZrribkz 2688
+VGETMANTSHZrrik 2689
+VGETMANTSHZrrikz 2690
+VGETMANTSSZrmi 2691
+VGETMANTSSZrmik 2692
+VGETMANTSSZrmikz 2693
+VGETMANTSSZrri 2694
+VGETMANTSSZrrib 2695
+VGETMANTSSZrribk 2696
+VGETMANTSSZrribkz 2697
+VGETMANTSSZrrik 2698
+VGETMANTSSZrrikz 2699
+VGF 2700
+VHADDPDYrm 2701
+VHADDPDYrr 2702
+VHADDPDrm 2703
+VHADDPDrr 2704
+VHADDPSYrm 2705
+VHADDPSYrr 2706
+VHADDPSrm 2707
+VHADDPSrr 2708
+VHSUBPDYrm 2709
+VHSUBPDYrr 2710
+VHSUBPDrm 2711
+VHSUBPDrr 2712
+VHSUBPSYrm 2713
+VHSUBPSYrr 2714
+VHSUBPSrm 2715
+VHSUBPSrr 2716
+VINSERTF 2717
+VINSERTI 2718
+VINSERTPSZrmi 2719
+VINSERTPSZrri 2720
+VINSERTPSrmi 2721
+VINSERTPSrri 2722
+VLDDQUYrm 2723
+VLDDQUrm 2724
+VLDMXCSR 2725
+VMASKMOVDQU 2726
+VMASKMOVPDYmr 2727
+VMASKMOVPDYrm 2728
+VMASKMOVPDmr 2729
+VMASKMOVPDrm 2730
+VMASKMOVPSYmr 2731
+VMASKMOVPSYrm 2732
+VMASKMOVPSmr 2733
+VMASKMOVPSrm 2734
+VMAXBF 2735
+VMAXCPDYrm 2736
+VMAXCPDYrr 2737
+VMAXCPDZ 2738
+VMAXCPDZrm 2739
+VMAXCPDZrmb 2740
+VMAXCPDZrmbk 2741
+VMAXCPDZrmbkz 2742
+VMAXCPDZrmk 2743
+VMAXCPDZrmkz 2744
+VMAXCPDZrr 2745
+VMAXCPDZrrk 2746
+VMAXCPDZrrkz 2747
+VMAXCPDrm 2748
+VMAXCPDrr 2749
+VMAXCPHZ 2750
+VMAXCPHZrm 2751
+VMAXCPHZrmb 2752
+VMAXCPHZrmbk 2753
+VMAXCPHZrmbkz 2754
+VMAXCPHZrmk 2755
+VMAXCPHZrmkz 2756
+VMAXCPHZrr 2757
+VMAXCPHZrrk 2758
+VMAXCPHZrrkz 2759
+VMAXCPSYrm 2760
+VMAXCPSYrr 2761
+VMAXCPSZ 2762
+VMAXCPSZrm 2763
+VMAXCPSZrmb 2764
+VMAXCPSZrmbk 2765
+VMAXCPSZrmbkz 2766
+VMAXCPSZrmk 2767
+VMAXCPSZrmkz 2768
+VMAXCPSZrr 2769
+VMAXCPSZrrk 2770
+VMAXCPSZrrkz 2771
+VMAXCPSrm 2772
+VMAXCPSrr 2773
+VMAXCSDZrm 2774
+VMAXCSDZrr 2775
+VMAXCSDrm 2776
+VMAXCSDrr 2777
+VMAXCSHZrm 2778
+VMAXCSHZrr 2779
+VMAXCSSZrm 2780
+VMAXCSSZrr 2781
+VMAXCSSrm 2782
+VMAXCSSrr 2783
+VMAXPDYrm 2784
+VMAXPDYrr 2785
+VMAXPDZ 2786
+VMAXPDZrm 2787
+VMAXPDZrmb 2788
+VMAXPDZrmbk 2789
+VMAXPDZrmbkz 2790
+VMAXPDZrmk 2791
+VMAXPDZrmkz 2792
+VMAXPDZrr 2793
+VMAXPDZrrb 2794
+VMAXPDZrrbk 2795
+VMAXPDZrrbkz 2796
+VMAXPDZrrk 2797
+VMAXPDZrrkz 2798
+VMAXPDrm 2799
+VMAXPDrr 2800
+VMAXPHZ 2801
+VMAXPHZrm 2802
+VMAXPHZrmb 2803
+VMAXPHZrmbk 2804
+VMAXPHZrmbkz 2805
+VMAXPHZrmk 2806
+VMAXPHZrmkz 2807
+VMAXPHZrr 2808
+VMAXPHZrrb 2809
+VMAXPHZrrbk 2810
+VMAXPHZrrbkz 2811
+VMAXPHZrrk 2812
+VMAXPHZrrkz 2813
+VMAXPSYrm 2814
+VMAXPSYrr 2815
+VMAXPSZ 2816
+VMAXPSZrm 2817
+VMAXPSZrmb 2818
+VMAXPSZrmbk 2819
+VMAXPSZrmbkz 2820
+VMAXPSZrmk 2821
+VMAXPSZrmkz 2822
+VMAXPSZrr 2823
+VMAXPSZrrb 2824
+VMAXPSZrrbk 2825
+VMAXPSZrrbkz 2826
+VMAXPSZrrk 2827
+VMAXPSZrrkz 2828
+VMAXPSrm 2829
+VMAXPSrr 2830
+VMAXSDZrm 2831
+VMAXSDZrm_Int 2832
+VMAXSDZrmk_Int 2833
+VMAXSDZrmkz_Int 2834
+VMAXSDZrr 2835
+VMAXSDZrr_Int 2836
+VMAXSDZrrb_Int 2837
+VMAXSDZrrbk_Int 2838
+VMAXSDZrrbkz_Int 2839
+VMAXSDZrrk_Int 2840
+VMAXSDZrrkz_Int 2841
+VMAXSDrm 2842
+VMAXSDrm_Int 2843
+VMAXSDrr 2844
+VMAXSDrr_Int 2845
+VMAXSHZrm 2846
+VMAXSHZrm_Int 2847
+VMAXSHZrmk_Int 2848
+VMAXSHZrmkz_Int 2849
+VMAXSHZrr 2850
+VMAXSHZrr_Int 2851
+VMAXSHZrrb_Int 2852
+VMAXSHZrrbk_Int 2853
+VMAXSHZrrbkz_Int 2854
+VMAXSHZrrk_Int 2855
+VMAXSHZrrkz_Int 2856
+VMAXSSZrm 2857
+VMAXSSZrm_Int 2858
+VMAXSSZrmk_Int 2859
+VMAXSSZrmkz_Int 2860
+VMAXSSZrr 2861
+VMAXSSZrr_Int 2862
+VMAXSSZrrb_Int 2863
+VMAXSSZrrbk_Int 2864
+VMAXSSZrrbkz_Int 2865
+VMAXSSZrrk_Int 2866
+VMAXSSZrrkz_Int 2867
+VMAXSSrm 2868
+VMAXSSrm_Int 2869
+VMAXSSrr 2870
+VMAXSSrr_Int 2871
+VMCALL 2872
+VMCLEARm 2873
+VMFUNC 2874
+VMINBF 2875
+VMINCPDYrm 2876
+VMINCPDYrr 2877
+VMINCPDZ 2878
+VMINCPDZrm 2879
+VMINCPDZrmb 2880
+VMINCPDZrmbk 2881
+VMINCPDZrmbkz 2882
+VMINCPDZrmk 2883
+VMINCPDZrmkz 2884
+VMINCPDZrr 2885
+VMINCPDZrrk 2886
+VMINCPDZrrkz 2887
+VMINCPDrm 2888
+VMINCPDrr 2889
+VMINCPHZ 2890
+VMINCPHZrm 2891
+VMINCPHZrmb 2892
+VMINCPHZrmbk 2893
+VMINCPHZrmbkz 2894
+VMINCPHZrmk 2895
+VMINCPHZrmkz 2896
+VMINCPHZrr 2897
+VMINCPHZrrk 2898
+VMINCPHZrrkz 2899
+VMINCPSYrm 2900
+VMINCPSYrr 2901
+VMINCPSZ 2902
+VMINCPSZrm 2903
+VMINCPSZrmb 2904
+VMINCPSZrmbk 2905
+VMINCPSZrmbkz 2906
+VMINCPSZrmk 2907
+VMINCPSZrmkz 2908
+VMINCPSZrr 2909
+VMINCPSZrrk 2910
+VMINCPSZrrkz 2911
+VMINCPSrm 2912
+VMINCPSrr 2913
+VMINCSDZrm 2914
+VMINCSDZrr 2915
+VMINCSDrm 2916
+VMINCSDrr 2917
+VMINCSHZrm 2918
+VMINCSHZrr 2919
+VMINCSSZrm 2920
+VMINCSSZrr 2921
+VMINCSSrm 2922
+VMINCSSrr 2923
+VMINMAXBF 2924
+VMINMAXPDZ 2925
+VMINMAXPDZrmbi 2926
+VMINMAXPDZrmbik 2927
+VMINMAXPDZrmbikz 2928
+VMINMAXPDZrmi 2929
+VMINMAXPDZrmik 2930
+VMINMAXPDZrmikz 2931
+VMINMAXPDZrri 2932
+VMINMAXPDZrrib 2933
+VMINMAXPDZrribk 2934
+VMINMAXPDZrribkz 2935
+VMINMAXPDZrrik 2936
+VMINMAXPDZrrikz 2937
+VMINMAXPHZ 2938
+VMINMAXPHZrmbi 2939
+VMINMAXPHZrmbik 2940
+VMINMAXPHZrmbikz 2941
+VMINMAXPHZrmi 2942
+VMINMAXPHZrmik 2943
+VMINMAXPHZrmikz 2944
+VMINMAXPHZrri 2945
+VMINMAXPHZrrib 2946
+VMINMAXPHZrribk 2947
+VMINMAXPHZrribkz 2948
+VMINMAXPHZrrik 2949
+VMINMAXPHZrrikz 2950
+VMINMAXPSZ 2951
+VMINMAXPSZrmbi 2952
+VMINMAXPSZrmbik 2953
+VMINMAXPSZrmbikz 2954
+VMINMAXPSZrmi 2955
+VMINMAXPSZrmik 2956
+VMINMAXPSZrmikz 2957
+VMINMAXPSZrri 2958
+VMINMAXPSZrrib 2959
+VMINMAXPSZrribk 2960
+VMINMAXPSZrribkz 2961
+VMINMAXPSZrrik 2962
+VMINMAXPSZrrikz 2963
+VMINMAXSDrmi 2964
+VMINMAXSDrmi_Int 2965
+VMINMAXSDrmik_Int 2966
+VMINMAXSDrmikz_Int 2967
+VMINMAXSDrri 2968
+VMINMAXSDrri_Int 2969
+VMINMAXSDrrib_Int 2970
+VMINMAXSDrribk_Int 2971
+VMINMAXSDrribkz_Int 2972
+VMINMAXSDrrik_Int 2973
+VMINMAXSDrrikz_Int 2974
+VMINMAXSHrmi 2975
+VMINMAXSHrmi_Int 2976
+VMINMAXSHrmik_Int 2977
+VMINMAXSHrmikz_Int 2978
+VMINMAXSHrri 2979
+VMINMAXSHrri_Int 2980
+VMINMAXSHrrib_Int 2981
+VMINMAXSHrribk_Int 2982
+VMINMAXSHrribkz_Int 2983
+VMINMAXSHrrik_Int 2984
+VMINMAXSHrrikz_Int 2985
+VMINMAXSSrmi 2986
+VMINMAXSSrmi_Int 2987
+VMINMAXSSrmik_Int 2988
+VMINMAXSSrmikz_Int 2989
+VMINMAXSSrri 2990
+VMINMAXSSrri_Int 2991
+VMINMAXSSrrib_Int 2992
+VMINMAXSSrribk_Int 2993
+VMINMAXSSrribkz_Int 2994
+VMINMAXSSrrik_Int 2995
+VMINMAXSSrrikz_Int 2996
+VMINPDYrm 2997
+VMINPDYrr 2998
+VMINPDZ 2999
+VMINPDZrm 3000
+VMINPDZrmb 3001
+VMINPDZrmbk 3002
+VMINPDZrmbkz 3003
+VMINPDZrmk 3004
+VMINPDZrmkz 3005
+VMINPDZrr 3006
+VMINPDZrrb 3007
+VMINPDZrrbk 3008
+VMINPDZrrbkz 3009
+VMINPDZrrk 3010
+VMINPDZrrkz 3011
+VMINPDrm 3012
+VMINPDrr 3013
+VMINPHZ 3014
+VMINPHZrm 3015
+VMINPHZrmb 3016
+VMINPHZrmbk 3017
+VMINPHZrmbkz 3018
+VMINPHZrmk 3019
+VMINPHZrmkz 3020
+VMINPHZrr 3021
+VMINPHZrrb 3022
+VMINPHZrrbk 3023
+VMINPHZrrbkz 3024
+VMINPHZrrk 3025
+VMINPHZrrkz 3026
+VMINPSYrm 3027
+VMINPSYrr 3028
+VMINPSZ 3029
+VMINPSZrm 3030
+VMINPSZrmb 3031
+VMINPSZrmbk 3032
+VMINPSZrmbkz 3033
+VMINPSZrmk 3034
+VMINPSZrmkz 3035
+VMINPSZrr 3036
+VMINPSZrrb 3037
+VMINPSZrrbk 3038
+VMINPSZrrbkz 3039
+VMINPSZrrk 3040
+VMINPSZrrkz 3041
+VMINPSrm 3042
+VMINPSrr 3043
+VMINSDZrm 3044
+VMINSDZrm_Int 3045
+VMINSDZrmk_Int 3046
+VMINSDZrmkz_Int 3047
+VMINSDZrr 3048
+VMINSDZrr_Int 3049
+VMINSDZrrb_Int 3050
+VMINSDZrrbk_Int 3051
+VMINSDZrrbkz_Int 3052
+VMINSDZrrk_Int 3053
+VMINSDZrrkz_Int 3054
+VMINSDrm 3055
+VMINSDrm_Int 3056
+VMINSDrr 3057
+VMINSDrr_Int 3058
+VMINSHZrm 3059
+VMINSHZrm_Int 3060
+VMINSHZrmk_Int 3061
+VMINSHZrmkz_Int 3062
+VMINSHZrr 3063
+VMINSHZrr_Int 3064
+VMINSHZrrb_Int 3065
+VMINSHZrrbk_Int 3066
+VMINSHZrrbkz_Int 3067
+VMINSHZrrk_Int 3068
+VMINSHZrrkz_Int 3069
+VMINSSZrm 3070
+VMINSSZrm_Int 3071
+VMINSSZrmk_Int 3072
+VMINSSZrmkz_Int 3073
+VMINSSZrr 3074
+VMINSSZrr_Int 3075
+VMINSSZrrb_Int 3076
+VMINSSZrrbk_Int 3077
+VMINSSZrrbkz_Int 3078
+VMINSSZrrk_Int 3079
+VMINSSZrrkz_Int 3080
+VMINSSrm 3081
+VMINSSrm_Int 3082
+VMINSSrr 3083
+VMINSSrr_Int 3084
+VMLAUNCH 3085
+VMLOAD 3086
+VMMCALL 3087
+VMOV 3088
+VMOVAPDYmr 3089
+VMOVAPDYrm 3090
+VMOVAPDYrr 3091
+VMOVAPDYrr_REV 3092
+VMOVAPDZ 3093
+VMOVAPDZmr 3094
+VMOVAPDZmrk 3095
+VMOVAPDZrm 3096
+VMOVAPDZrmk 3097
+VMOVAPDZrmkz 3098
+VMOVAPDZrr 3099
+VMOVAPDZrr_REV 3100
+VMOVAPDZrrk 3101
+VMOVAPDZrrk_REV 3102
+VMOVAPDZrrkz 3103
+VMOVAPDZrrkz_REV 3104
+VMOVAPDmr 3105
+VMOVAPDrm 3106
+VMOVAPDrr 3107
+VMOVAPDrr_REV 3108
+VMOVAPSYmr 3109
+VMOVAPSYrm 3110
+VMOVAPSYrr 3111
+VMOVAPSYrr_REV 3112
+VMOVAPSZ 3113
+VMOVAPSZmr 3114
+VMOVAPSZmrk 3115
+VMOVAPSZrm 3116
+VMOVAPSZrmk 3117
+VMOVAPSZrmkz 3118
+VMOVAPSZrr 3119
+VMOVAPSZrr_REV 3120
+VMOVAPSZrrk 3121
+VMOVAPSZrrk_REV 3122
+VMOVAPSZrrkz 3123
+VMOVAPSZrrkz_REV 3124
+VMOVAPSmr 3125
+VMOVAPSrm 3126
+VMOVAPSrr 3127
+VMOVAPSrr_REV 3128
+VMOVDDUPYrm 3129
+VMOVDDUPYrr 3130
+VMOVDDUPZ 3131
+VMOVDDUPZrm 3132
+VMOVDDUPZrmk 3133
+VMOVDDUPZrmkz 3134
+VMOVDDUPZrr 3135
+VMOVDDUPZrrk 3136
+VMOVDDUPZrrkz 3137
+VMOVDDUPrm 3138
+VMOVDDUPrr 3139
+VMOVDI 3140
+VMOVDQA 3141
+VMOVDQAYmr 3142
+VMOVDQAYrm 3143
+VMOVDQAYrr 3144
+VMOVDQAYrr_REV 3145
+VMOVDQAmr 3146
+VMOVDQArm 3147
+VMOVDQArr 3148
+VMOVDQArr_REV 3149
+VMOVDQU 3150
+VMOVDQUYmr 3151
+VMOVDQUYrm 3152
+VMOVDQUYrr 3153
+VMOVDQUYrr_REV 3154
+VMOVDQUmr 3155
+VMOVDQUrm 3156
+VMOVDQUrr 3157
+VMOVDQUrr_REV 3158
+VMOVHLPSZrr 3159
+VMOVHLPSrr 3160
+VMOVHPDZ 3161
+VMOVHPDmr 3162
+VMOVHPDrm 3163
+VMOVHPSZ 3164
+VMOVHPSmr 3165
+VMOVHPSrm 3166
+VMOVLHPSZrr 3167
+VMOVLHPSrr 3168
+VMOVLPDZ 3169
+VMOVLPDmr 3170
+VMOVLPDrm 3171
+VMOVLPSZ 3172
+VMOVLPSmr 3173
+VMOVLPSrm 3174
+VMOVMSKPDYrr 3175
+VMOVMSKPDrr 3176
+VMOVMSKPSYrr 3177
+VMOVMSKPSrr 3178
+VMOVNTDQAYrm 3179
+VMOVNTDQAZ 3180
+VMOVNTDQAZrm 3181
+VMOVNTDQArm 3182
+VMOVNTDQYmr 3183
+VMOVNTDQZ 3184
+VMOVNTDQZmr 3185
+VMOVNTDQmr 3186
+VMOVNTPDYmr 3187
+VMOVNTPDZ 3188
+VMOVNTPDZmr 3189
+VMOVNTPDmr 3190
+VMOVNTPSYmr 3191
+VMOVNTPSZ 3192
+VMOVNTPSZmr 3193
+VMOVNTPSmr 3194
+VMOVPDI 3195
+VMOVPQI 3196
+VMOVPQIto 3197
+VMOVQI 3198
+VMOVRSBZ 3199
+VMOVRSBZm 3200
+VMOVRSBZmk 3201
+VMOVRSBZmkz 3202
+VMOVRSDZ 3203
+VMOVRSDZm 3204
+VMOVRSDZmk 3205
+VMOVRSDZmkz 3206
+VMOVRSQZ 3207
+VMOVRSQZm 3208
+VMOVRSQZmk 3209
+VMOVRSQZmkz 3210
+VMOVRSWZ 3211
+VMOVRSWZm 3212
+VMOVRSWZmk 3213
+VMOVRSWZmkz 3214
+VMOVSDZmr 3215
+VMOVSDZmrk 3216
+VMOVSDZrm 3217
+VMOVSDZrm_alt 3218
+VMOVSDZrmk 3219
+VMOVSDZrmkz 3220
+VMOVSDZrr 3221
+VMOVSDZrr_REV 3222
+VMOVSDZrrk 3223
+VMOVSDZrrk_REV 3224
+VMOVSDZrrkz 3225
+VMOVSDZrrkz_REV 3226
+VMOVSDmr 3227
+VMOVSDrm 3228
+VMOVSDrm_alt 3229
+VMOVSDrr 3230
+VMOVSDrr_REV 3231
+VMOVSDto 3232
+VMOVSH 3233
+VMOVSHDUPYrm 3234
+VMOVSHDUPYrr 3235
+VMOVSHDUPZ 3236
+VMOVSHDUPZrm 3237
+VMOVSHDUPZrmk 3238
+VMOVSHDUPZrmkz 3239
+VMOVSHDUPZrr 3240
+VMOVSHDUPZrrk 3241
+VMOVSHDUPZrrkz 3242
+VMOVSHDUPrm 3243
+VMOVSHDUPrr 3244
+VMOVSHZmr 3245
+VMOVSHZmrk 3246
+VMOVSHZrm 3247
+VMOVSHZrm_alt 3248
+VMOVSHZrmk 3249
+VMOVSHZrmkz 3250
+VMOVSHZrr 3251
+VMOVSHZrr_REV 3252
+VMOVSHZrrk 3253
+VMOVSHZrrk_REV 3254
+VMOVSHZrrkz 3255
+VMOVSHZrrkz_REV 3256
+VMOVSHtoW 3257
+VMOVSLDUPYrm 3258
+VMOVSLDUPYrr 3259
+VMOVSLDUPZ 3260
+VMOVSLDUPZrm 3261
+VMOVSLDUPZrmk 3262
+VMOVSLDUPZrmkz 3263
+VMOVSLDUPZrr 3264
+VMOVSLDUPZrrk 3265
+VMOVSLDUPZrrkz 3266
+VMOVSLDUPrm 3267
+VMOVSLDUPrr 3268
+VMOVSS 3269
+VMOVSSZmr 3270
+VMOVSSZmrk 3271
+VMOVSSZrm 3272
+VMOVSSZrm_alt 3273
+VMOVSSZrmk 3274
+VMOVSSZrmkz 3275
+VMOVSSZrr 3276
+VMOVSSZrr_REV 3277
+VMOVSSZrrk 3278
+VMOVSSZrrk_REV 3279
+VMOVSSZrrkz 3280
+VMOVSSZrrkz_REV 3281
+VMOVSSmr 3282
+VMOVSSrm 3283
+VMOVSSrm_alt 3284
+VMOVSSrr 3285
+VMOVSSrr_REV 3286
+VMOVUPDYmr 3287
+VMOVUPDYrm 3288
+VMOVUPDYrr 3289
+VMOVUPDYrr_REV 3290
+VMOVUPDZ 3291
+VMOVUPDZmr 3292
+VMOVUPDZmrk 3293
+VMOVUPDZrm 3294
+VMOVUPDZrmk 3295
+VMOVUPDZrmkz 3296
+VMOVUPDZrr 3297
+VMOVUPDZrr_REV 3298
+VMOVUPDZrrk 3299
+VMOVUPDZrrk_REV 3300
+VMOVUPDZrrkz 3301
+VMOVUPDZrrkz_REV 3302
+VMOVUPDmr 3303
+VMOVUPDrm 3304
+VMOVUPDrr 3305
+VMOVUPDrr_REV 3306
+VMOVUPSYmr 3307
+VMOVUPSYrm 3308
+VMOVUPSYrr 3309
+VMOVUPSYrr_REV 3310
+VMOVUPSZ 3311
+VMOVUPSZmr 3312
+VMOVUPSZmrk 3313
+VMOVUPSZrm 3314
+VMOVUPSZrmk 3315
+VMOVUPSZrmkz 3316
+VMOVUPSZrr 3317
+VMOVUPSZrr_REV 3318
+VMOVUPSZrrk 3319
+VMOVUPSZrrk_REV 3320
+VMOVUPSZrrkz 3321
+VMOVUPSZrrkz_REV 3322
+VMOVUPSmr 3323
+VMOVUPSrm 3324
+VMOVUPSrr 3325
+VMOVUPSrr_REV 3326
+VMOVW 3327
+VMOVWmr 3328
+VMOVWrm 3329
+VMOVZPDILo 3330
+VMOVZPQILo 3331
+VMOVZPWILo 3332
+VMPSADBWYrmi 3333
+VMPSADBWYrri 3334
+VMPSADBWZ 3335
+VMPSADBWZrmi 3336
+VMPSADBWZrmik 3337
+VMPSADBWZrmikz 3338
+VMPSADBWZrri 3339
+VMPSADBWZrrik 3340
+VMPSADBWZrrikz 3341
+VMPSADBWrmi 3342
+VMPSADBWrri 3343
+VMPTRLDm 3344
+VMPTRSTm 3345
+VMREAD 3346
+VMRESUME 3347
+VMRUN 3348
+VMSAVE 3349
+VMULBF 3350
+VMULPDYrm 3351
+VMULPDYrr 3352
+VMULPDZ 3353
+VMULPDZrm 3354
+VMULPDZrmb 3355
+VMULPDZrmbk 3356
+VMULPDZrmbkz 3357
+VMULPDZrmk 3358
+VMULPDZrmkz 3359
+VMULPDZrr 3360
+VMULPDZrrb 3361
+VMULPDZrrbk 3362
+VMULPDZrrbkz 3363
+VMULPDZrrk 3364
+VMULPDZrrkz 3365
+VMULPDrm 3366
+VMULPDrr 3367
+VMULPHZ 3368
+VMULPHZrm 3369
+VMULPHZrmb 3370
+VMULPHZrmbk 3371
+VMULPHZrmbkz 3372
+VMULPHZrmk 3373
+VMULPHZrmkz 3374
+VMULPHZrr 3375
+VMULPHZrrb 3376
+VMULPHZrrbk 3377
+VMULPHZrrbkz 3378
+VMULPHZrrk 3379
+VMULPHZrrkz 3380
+VMULPSYrm 3381
+VMULPSYrr 3382
+VMULPSZ 3383
+VMULPSZrm 3384
+VMULPSZrmb 3385
+VMULPSZrmbk 3386
+VMULPSZrmbkz 3387
+VMULPSZrmk 3388
+VMULPSZrmkz 3389
+VMULPSZrr 3390
+VMULPSZrrb 3391
+VMULPSZrrbk 3392
+VMULPSZrrbkz 3393
+VMULPSZrrk 3394
+VMULPSZrrkz 3395
+VMULPSrm 3396
+VMULPSrr 3397
+VMULSDZrm 3398
+VMULSDZrm_Int 3399
+VMULSDZrmk_Int 3400
+VMULSDZrmkz_Int 3401
+VMULSDZrr 3402
+VMULSDZrr_Int 3403
+VMULSDZrrb_Int 3404
+VMULSDZrrbk_Int 3405
+VMULSDZrrbkz_Int 3406
+VMULSDZrrk_Int 3407
+VMULSDZrrkz_Int 3408
+VMULSDrm 3409
+VMULSDrm_Int 3410
+VMULSDrr 3411
+VMULSDrr_Int 3412
+VMULSHZrm 3413
+VMULSHZrm_Int 3414
+VMULSHZrmk_Int 3415
+VMULSHZrmkz_Int 3416
+VMULSHZrr 3417
+VMULSHZrr_Int 3418
+VMULSHZrrb_Int 3419
+VMULSHZrrbk_Int 3420
+VMULSHZrrbkz_Int 3421
+VMULSHZrrk_Int 3422
+VMULSHZrrkz_Int 3423
+VMULSSZrm 3424
+VMULSSZrm_Int 3425
+VMULSSZrmk_Int 3426
+VMULSSZrmkz_Int 3427
+VMULSSZrr 3428
+VMULSSZrr_Int 3429
+VMULSSZrrb_Int 3430
+VMULSSZrrbk_Int 3431
+VMULSSZrrbkz_Int 3432
+VMULSSZrrk_Int 3433
+VMULSSZrrkz_Int 3434
+VMULSSrm 3435
+VMULSSrm_Int 3436
+VMULSSrr 3437
+VMULSSrr_Int 3438
+VMWRITE 3439
+VMXOFF 3440
+VMXON 3441
+VORPDYrm 3442
+VORPDYrr 3443
+VORPDZ 3444
+VORPDZrm 3445
+VORPDZrmb 3446
+VORPDZrmbk 3447
+VORPDZrmbkz 3448
+VORPDZrmk 3449
+VORPDZrmkz 3450
+VORPDZrr 3451
+VORPDZrrk 3452
+VORPDZrrkz 3453
+VORPDrm 3454
+VORPDrr 3455
+VORPSYrm 3456
+VORPSYrr 3457
+VORPSZ 3458
+VORPSZrm 3459
+VORPSZrmb 3460
+VORPSZrmbk 3461
+VORPSZrmbkz 3462
+VORPSZrmk 3463
+VORPSZrmkz 3464
+VORPSZrr 3465
+VORPSZrrk 3466
+VORPSZrrkz 3467
+VORPSrm 3468
+VORPSrr 3469
+VP 3470
+VPABSBYrm 3471
+VPABSBYrr 3472
+VPABSBZ 3473
+VPABSBZrm 3474
+VPABSBZrmk 3475
+VPABSBZrmkz 3476
+VPABSBZrr 3477
+VPABSBZrrk 3478
+VPABSBZrrkz 3479
+VPABSBrm 3480
+VPABSBrr 3481
+VPABSDYrm 3482
+VPABSDYrr 3483
+VPABSDZ 3484
+VPABSDZrm 3485
+VPABSDZrmb 3486
+VPABSDZrmbk 3487
+VPABSDZrmbkz 3488
+VPABSDZrmk 3489
+VPABSDZrmkz 3490
+VPABSDZrr 3491
+VPABSDZrrk 3492
+VPABSDZrrkz 3493
+VPABSDrm 3494
+VPABSDrr 3495
+VPABSQZ 3496
+VPABSQZrm 3497
+VPABSQZrmb 3498
+VPABSQZrmbk 3499
+VPABSQZrmbkz 3500
+VPABSQZrmk 3501
+VPABSQZrmkz 3502
+VPABSQZrr 3503
+VPABSQZrrk 3504
+VPABSQZrrkz 3505
+VPABSWYrm 3506
+VPABSWYrr 3507
+VPABSWZ 3508
+VPABSWZrm 3509
+VPABSWZrmk 3510
+VPABSWZrmkz 3511
+VPABSWZrr 3512
+VPABSWZrrk 3513
+VPABSWZrrkz 3514
+VPABSWrm 3515
+VPABSWrr 3516
+VPACKSSDWYrm 3517
+VPACKSSDWYrr 3518
+VPACKSSDWZ 3519
+VPACKSSDWZrm 3520
+VPACKSSDWZrmb 3521
+VPACKSSDWZrmbk 3522
+VPACKSSDWZrmbkz 3523
+VPACKSSDWZrmk 3524
+VPACKSSDWZrmkz 3525
+VPACKSSDWZrr 3526
+VPACKSSDWZrrk 3527
+VPACKSSDWZrrkz 3528
+VPACKSSDWrm 3529
+VPACKSSDWrr 3530
+VPACKSSWBYrm 3531
+VPACKSSWBYrr 3532
+VPACKSSWBZ 3533
+VPACKSSWBZrm 3534
+VPACKSSWBZrmk 3535
+VPACKSSWBZrmkz 3536
+VPACKSSWBZrr 3537
+VPACKSSWBZrrk 3538
+VPACKSSWBZrrkz 3539
+VPACKSSWBrm 3540
+VPACKSSWBrr 3541
+VPACKUSDWYrm 3542
+VPACKUSDWYrr 3543
+VPACKUSDWZ 3544
+VPACKUSDWZrm 3545
+VPACKUSDWZrmb 3546
+VPACKUSDWZrmbk 3547
+VPACKUSDWZrmbkz 3548
+VPACKUSDWZrmk 3549
+VPACKUSDWZrmkz 3550
+VPACKUSDWZrr 3551
+VPACKUSDWZrrk 3552
+VPACKUSDWZrrkz 3553
+VPACKUSDWrm 3554
+VPACKUSDWrr 3555
+VPACKUSWBYrm 3556
+VPACKUSWBYrr 3557
+VPACKUSWBZ 3558
+VPACKUSWBZrm 3559
+VPACKUSWBZrmk 3560
+VPACKUSWBZrmkz 3561
+VPACKUSWBZrr 3562
+VPACKUSWBZrrk 3563
+VPACKUSWBZrrkz 3564
+VPACKUSWBrm 3565
+VPACKUSWBrr 3566
+VPADDBYrm 3567
+VPADDBYrr 3568
+VPADDBZ 3569
+VPADDBZrm 3570
+VPADDBZrmk 3571
+VPADDBZrmkz 3572
+VPADDBZrr 3573
+VPADDBZrrk 3574
+VPADDBZrrkz 3575
+VPADDBrm 3576
+VPADDBrr 3577
+VPADDDYrm 3578
+VPADDDYrr 3579
+VPADDDZ 3580
+VPADDDZrm 3581
+VPADDDZrmb 3582
+VPADDDZrmbk 3583
+VPADDDZrmbkz 3584
+VPADDDZrmk 3585
+VPADDDZrmkz 3586
+VPADDDZrr 3587
+VPADDDZrrk 3588
+VPADDDZrrkz 3589
+VPADDDrm 3590
+VPADDDrr 3591
+VPADDQYrm 3592
+VPADDQYrr 3593
+VPADDQZ 3594
+VPADDQZrm 3595
+VPADDQZrmb 3596
+VPADDQZrmbk 3597
+VPADDQZrmbkz 3598
+VPADDQZrmk 3599
+VPADDQZrmkz 3600
+VPADDQZrr 3601
+VPADDQZrrk 3602
+VPADDQZrrkz 3603
+VPADDQrm 3604
+VPADDQrr 3605
+VPADDSBYrm 3606
+VPADDSBYrr 3607
+VPADDSBZ 3608
+VPADDSBZrm 3609
+VPADDSBZrmk 3610
+VPADDSBZrmkz 3611
+VPADDSBZrr 3612
+VPADDSBZrrk 3613
+VPADDSBZrrkz 3614
+VPADDSBrm 3615
+VPADDSBrr 3616
+VPADDSWYrm 3617
+VPADDSWYrr 3618
+VPADDSWZ 3619
+VPADDSWZrm 3620
+VPADDSWZrmk 3621
+VPADDSWZrmkz 3622
+VPADDSWZrr 3623
+VPADDSWZrrk 3624
+VPADDSWZrrkz 3625
+VPADDSWrm 3626
+VPADDSWrr 3627
+VPADDUSBYrm 3628
+VPADDUSBYrr 3629
+VPADDUSBZ 3630
+VPADDUSBZrm 3631
+VPADDUSBZrmk 3632
+VPADDUSBZrmkz 3633
+VPADDUSBZrr 3634
+VPADDUSBZrrk 3635
+VPADDUSBZrrkz 3636
+VPADDUSBrm 3637
+VPADDUSBrr 3638
+VPADDUSWYrm 3639
+VPADDUSWYrr 3640
+VPADDUSWZ 3641
+VPADDUSWZrm 3642
+VPADDUSWZrmk 3643
+VPADDUSWZrmkz 3644
+VPADDUSWZrr 3645
+VPADDUSWZrrk 3646
+VPADDUSWZrrkz 3647
+VPADDUSWrm 3648
+VPADDUSWrr 3649
+VPADDWYrm 3650
+VPADDWYrr 3651
+VPADDWZ 3652
+VPADDWZrm 3653
+VPADDWZrmk 3654
+VPADDWZrmkz 3655
+VPADDWZrr 3656
+VPADDWZrrk 3657
+VPADDWZrrkz 3658
+VPADDWrm 3659
+VPADDWrr 3660
+VPALIGNRYrmi 3661
+VPALIGNRYrri 3662
+VPALIGNRZ 3663
+VPALIGNRZrmi 3664
+VPALIGNRZrmik 3665
+VPALIGNRZrmikz 3666
+VPALIGNRZrri 3667
+VPALIGNRZrrik 3668
+VPALIGNRZrrikz 3669
+VPALIGNRrmi 3670
+VPALIGNRrri 3671
+VPANDDZ 3672
+VPANDDZrm 3673
+VPANDDZrmb 3674
+VPANDDZrmbk 3675
+VPANDDZrmbkz 3676
+VPANDDZrmk 3677
+VPANDDZrmkz 3678
+VPANDDZrr 3679
+VPANDDZrrk 3680
+VPANDDZrrkz 3681
+VPANDNDZ 3682
+VPANDNDZrm 3683
+VPANDNDZrmb 3684
+VPANDNDZrmbk 3685
+VPANDNDZrmbkz 3686
+VPANDNDZrmk 3687
+VPANDNDZrmkz 3688
+VPANDNDZrr 3689
+VPANDNDZrrk 3690
+VPANDNDZrrkz 3691
+VPANDNQZ 3692
+VPANDNQZrm 3693
+VPANDNQZrmb 3694
+VPANDNQZrmbk 3695
+VPANDNQZrmbkz 3696
+VPANDNQZrmk 3697
+VPANDNQZrmkz 3698
+VPANDNQZrr 3699
+VPANDNQZrrk 3700
+VPANDNQZrrkz 3701
+VPANDNYrm 3702
+VPANDNYrr 3703
+VPANDNrm 3704
+VPANDNrr 3705
+VPANDQZ 3706
+VPANDQZrm 3707
+VPANDQZrmb 3708
+VPANDQZrmbk 3709
+VPANDQZrmbkz 3710
+VPANDQZrmk 3711
+VPANDQZrmkz 3712
+VPANDQZrr 3713
+VPANDQZrrk 3714
+VPANDQZrrkz 3715
+VPANDYrm 3716
+VPANDYrr 3717
+VPANDrm 3718
+VPANDrr 3719
+VPAVGBYrm 3720
+VPAVGBYrr 3721
+VPAVGBZ 3722
+VPAVGBZrm 3723
+VPAVGBZrmk 3724
+VPAVGBZrmkz 3725
+VPAVGBZrr 3726
+VPAVGBZrrk 3727
+VPAVGBZrrkz 3728
+VPAVGBrm 3729
+VPAVGBrr 3730
+VPAVGWYrm 3731
+VPAVGWYrr 3732
+VPAVGWZ 3733
+VPAVGWZrm 3734
+VPAVGWZrmk 3735
+VPAVGWZrmkz 3736
+VPAVGWZrr 3737
+VPAVGWZrrk 3738
+VPAVGWZrrkz 3739
+VPAVGWrm 3740
+VPAVGWrr 3741
+VPBLENDDYrmi 3742
+VPBLENDDYrri 3743
+VPBLENDDrmi 3744
+VPBLENDDrri 3745
+VPBLENDMBZ 3746
+VPBLENDMBZrm 3747
+VPBLENDMBZrmk 3748
+VPBLENDMBZrmkz 3749
+VPBLENDMBZrr 3750
+VPBLENDMBZrrk 3751
+VPBLENDMBZrrkz 3752
+VPBLENDMDZ 3753
+VPBLENDMDZrm 3754
+VPBLENDMDZrmb 3755
+VPBLENDMDZrmbk 3756
+VPBLENDMDZrmbkz 3757
+VPBLENDMDZrmk 3758
+VPBLENDMDZrmkz 3759
+VPBLENDMDZrr 3760
+VPBLENDMDZrrk 3761
+VPBLENDMDZrrkz 3762
+VPBLENDMQZ 3763
+VPBLENDMQZrm 3764
+VPBLENDMQZrmb 3765
+VPBLENDMQZrmbk 3766
+VPBLENDMQZrmbkz 3767
+VPBLENDMQZrmk 3768
+VPBLENDMQZrmkz 3769
+VPBLENDMQZrr 3770
+VPBLENDMQZrrk 3771
+VPBLENDMQZrrkz 3772
+VPBLENDMWZ 3773
+VPBLENDMWZrm 3774
+VPBLENDMWZrmk 3775
+VPBLENDMWZrmkz 3776
+VPBLENDMWZrr 3777
+VPBLENDMWZrrk 3778
+VPBLENDMWZrrkz 3779
+VPBLENDVBYrmr 3780
+VPBLENDVBYrrr 3781
+VPBLENDVBrmr 3782
+VPBLENDVBrrr 3783
+VPBLENDWYrmi 3784
+VPBLENDWYrri 3785
+VPBLENDWrmi 3786
+VPBLENDWrri 3787
+VPBROADCASTBYrm 3788
+VPBROADCASTBYrr 3789
+VPBROADCASTBZ 3790
+VPBROADCASTBZrm 3791
+VPBROADCASTBZrmk 3792
+VPBROADCASTBZrmkz 3793
+VPBROADCASTBZrr 3794
+VPBROADCASTBZrrk 3795
+VPBROADCASTBZrrkz 3796
+VPBROADCASTBrZ 3797
+VPBROADCASTBrZrr 3798
+VPBROADCASTBrZrrk 3799
+VPBROADCASTBrZrrkz 3800
+VPBROADCASTBrm 3801
+VPBROADCASTBrr 3802
+VPBROADCASTDYrm 3803
+VPBROADCASTDYrr 3804
+VPBROADCASTDZ 3805
+VPBROADCASTDZrm 3806
+VPBROADCASTDZrmk 3807
+VPBROADCASTDZrmkz 3808
+VPBROADCASTDZrr 3809
+VPBROADCASTDZrrk 3810
+VPBROADCASTDZrrkz 3811
+VPBROADCASTDrZ 3812
+VPBROADCASTDrZrr 3813
+VPBROADCASTDrZrrk 3814
+VPBROADCASTDrZrrkz 3815
+VPBROADCASTDrm 3816
+VPBROADCASTDrr 3817
+VPBROADCASTMB 3818
+VPBROADCASTMW 3819
+VPBROADCASTQYrm 3820
+VPBROADCASTQYrr 3821
+VPBROADCASTQZ 3822
+VPBROADCASTQZrm 3823
+VPBROADCASTQZrmk 3824
+VPBROADCASTQZrmkz 3825
+VPBROADCASTQZrr 3826
+VPBROADCASTQZrrk 3827
+VPBROADCASTQZrrkz 3828
+VPBROADCASTQrZ 3829
+VPBROADCASTQrZrr 3830
+VPBROADCASTQrZrrk 3831
+VPBROADCASTQrZrrkz 3832
+VPBROADCASTQrm 3833
+VPBROADCASTQrr 3834
+VPBROADCASTWYrm 3835
+VPBROADCASTWYrr 3836
+VPBROADCASTWZ 3837
+VPBROADCASTWZrm 3838
+VPBROADCASTWZrmk 3839
+VPBROADCASTWZrmkz 3840
+VPBROADCASTWZrr 3841
+VPBROADCASTWZrrk 3842
+VPBROADCASTWZrrkz 3843
+VPBROADCASTWrZ 3844
+VPBROADCASTWrZrr 3845
+VPBROADCASTWrZrrk 3846
+VPBROADCASTWrZrrkz 3847
+VPBROADCASTWrm 3848
+VPBROADCASTWrr 3849
+VPCLMULQDQYrmi 3850
+VPCLMULQDQYrri 3851
+VPCLMULQDQZ 3852
+VPCLMULQDQZrmi 3853
+VPCLMULQDQZrri 3854
+VPCLMULQDQrmi 3855
+VPCLMULQDQrri 3856
+VPCMOVYrmr 3857
+VPCMOVYrrm 3858
+VPCMOVYrrr 3859
+VPCMOVYrrr_REV 3860
+VPCMOVrmr 3861
+VPCMOVrrm 3862
+VPCMOVrrr 3863
+VPCMOVrrr_REV 3864
+VPCMPBZ 3865
+VPCMPBZrmi 3866
+VPCMPBZrmik 3867
+VPCMPBZrri 3868
+VPCMPBZrrik 3869
+VPCMPDZ 3870
+VPCMPDZrmbi 3871
+VPCMPDZrmbik 3872
+VPCMPDZrmi 3873
+VPCMPDZrmik 3874
+VPCMPDZrri 3875
+VPCMPDZrrik 3876
+VPCMPEQBYrm 3877
+VPCMPEQBYrr 3878
+VPCMPEQBZ 3879
+VPCMPEQBZrm 3880
+VPCMPEQBZrmk 3881
+VPCMPEQBZrr 3882
+VPCMPEQBZrrk 3883
+VPCMPEQBrm 3884
+VPCMPEQBrr 3885
+VPCMPEQDYrm 3886
+VPCMPEQDYrr 3887
+VPCMPEQDZ 3888
+VPCMPEQDZrm 3889
+VPCMPEQDZrmb 3890
+VPCMPEQDZrmbk 3891
+VPCMPEQDZrmk 3892
+VPCMPEQDZrr 3893
+VPCMPEQDZrrk 3894
+VPCMPEQDrm 3895
+VPCMPEQDrr 3896
+VPCMPEQQYrm 3897
+VPCMPEQQYrr 3898
+VPCMPEQQZ 3899
+VPCMPEQQZrm 3900
+VPCMPEQQZrmb 3901
+VPCMPEQQZrmbk 3902
+VPCMPEQQZrmk 3903
+VPCMPEQQZrr 3904
+VPCMPEQQZrrk 3905
+VPCMPEQQrm 3906
+VPCMPEQQrr 3907
+VPCMPEQWYrm 3908
+VPCMPEQWYrr 3909
+VPCMPEQWZ 3910
+VPCMPEQWZrm 3911
+VPCMPEQWZrmk 3912
+VPCMPEQWZrr 3913
+VPCMPEQWZrrk 3914
+VPCMPEQWrm 3915
+VPCMPEQWrr 3916
+VPCMPESTRIrmi 3917
+VPCMPESTRIrri 3918
+VPCMPESTRMrmi 3919
+VPCMPESTRMrri 3920
+VPCMPGTBYrm 3921
+VPCMPGTBYrr 3922
+VPCMPGTBZ 3923
+VPCMPGTBZrm 3924
+VPCMPGTBZrmk 3925
+VPCMPGTBZrr 3926
+VPCMPGTBZrrk 3927
+VPCMPGTBrm 3928
+VPCMPGTBrr 3929
+VPCMPGTDYrm 3930
+VPCMPGTDYrr 3931
+VPCMPGTDZ 3932
+VPCMPGTDZrm 3933
+VPCMPGTDZrmb 3934
+VPCMPGTDZrmbk 3935
+VPCMPGTDZrmk 3936
+VPCMPGTDZrr 3937
+VPCMPGTDZrrk 3938
+VPCMPGTDrm 3939
+VPCMPGTDrr 3940
+VPCMPGTQYrm 3941
+VPCMPGTQYrr 3942
+VPCMPGTQZ 3943
+VPCMPGTQZrm 3944
+VPCMPGTQZrmb 3945
+VPCMPGTQZrmbk 3946
+VPCMPGTQZrmk 3947
+VPCMPGTQZrr 3948
+VPCMPGTQZrrk 3949
+VPCMPGTQrm 3950
+VPCMPGTQrr 3951
+VPCMPGTWYrm 3952
+VPCMPGTWYrr 3953
+VPCMPGTWZ 3954
+VPCMPGTWZrm 3955
+VPCMPGTWZrmk 3956
+VPCMPGTWZrr 3957
+VPCMPGTWZrrk 3958
+VPCMPGTWrm 3959
+VPCMPGTWrr 3960
+VPCMPISTRIrmi 3961
+VPCMPISTRIrri 3962
+VPCMPISTRMrmi 3963
+VPCMPISTRMrri 3964
+VPCMPQZ 3965
+VPCMPQZrmbi 3966
+VPCMPQZrmbik 3967
+VPCMPQZrmi 3968
+VPCMPQZrmik 3969
+VPCMPQZrri 3970
+VPCMPQZrrik 3971
+VPCMPUBZ 3972
+VPCMPUBZrmi 3973
+VPCMPUBZrmik 3974
+VPCMPUBZrri 3975
+VPCMPUBZrrik 3976
+VPCMPUDZ 3977
+VPCMPUDZrmbi 3978
+VPCMPUDZrmbik 3979
+VPCMPUDZrmi 3980
+VPCMPUDZrmik 3981
+VPCMPUDZrri 3982
+VPCMPUDZrrik 3983
+VPCMPUQZ 3984
+VPCMPUQZrmbi 3985
+VPCMPUQZrmbik 3986
+VPCMPUQZrmi 3987
+VPCMPUQZrmik 3988
+VPCMPUQZrri 3989
+VPCMPUQZrrik 3990
+VPCMPUWZ 3991
+VPCMPUWZrmi 3992
+VPCMPUWZrmik 3993
+VPCMPUWZrri 3994
+VPCMPUWZrrik 3995
+VPCMPWZ 3996
+VPCMPWZrmi 3997
+VPCMPWZrmik 3998
+VPCMPWZrri 3999
+VPCMPWZrrik 4000
+VPCOMBmi 4001
+VPCOMBri 4002
+VPCOMDmi 4003
+VPCOMDri 4004
+VPCOMPRESSBZ 4005
+VPCOMPRESSBZmr 4006
+VPCOMPRESSBZmrk 4007
+VPCOMPRESSBZrr 4008
+VPCOMPRESSBZrrk 4009
+VPCOMPRESSBZrrkz 4010
+VPCOMPRESSDZ 4011
+VPCOMPRESSDZmr 4012
+VPCOMPRESSDZmrk 4013
+VPCOMPRESSDZrr 4014
+VPCOMPRESSDZrrk 4015
+VPCOMPRESSDZrrkz 4016
+VPCOMPRESSQZ 4017
+VPCOMPRESSQZmr 4018
+VPCOMPRESSQZmrk 4019
+VPCOMPRESSQZrr 4020
+VPCOMPRESSQZrrk 4021
+VPCOMPRESSQZrrkz 4022
+VPCOMPRESSWZ 4023
+VPCOMPRESSWZmr 4024
+VPCOMPRESSWZmrk 4025
+VPCOMPRESSWZrr 4026
+VPCOMPRESSWZrrk 4027
+VPCOMPRESSWZrrkz 4028
+VPCOMQmi 4029
+VPCOMQri 4030
+VPCOMUBmi 4031
+VPCOMUBri 4032
+VPCOMUDmi 4033
+VPCOMUDri 4034
+VPCOMUQmi 4035
+VPCOMUQri 4036
+VPCOMUWmi 4037
+VPCOMUWri 4038
+VPCOMWmi 4039
+VPCOMWri 4040
+VPCONFLICTDZ 4041
+VPCONFLICTDZrm 4042
+VPCONFLICTDZrmb 4043
+VPCONFLICTDZrmbk 4044
+VPCONFLICTDZrmbkz 4045
+VPCONFLICTDZrmk 4046
+VPCONFLICTDZrmkz 4047
+VPCONFLICTDZrr 4048
+VPCONFLICTDZrrk 4049
+VPCONFLICTDZrrkz 4050
+VPCONFLICTQZ 4051
+VPCONFLICTQZrm 4052
+VPCONFLICTQZrmb 4053
+VPCONFLICTQZrmbk 4054
+VPCONFLICTQZrmbkz 4055
+VPCONFLICTQZrmk 4056
+VPCONFLICTQZrmkz 4057
+VPCONFLICTQZrr 4058
+VPCONFLICTQZrrk 4059
+VPCONFLICTQZrrkz 4060
+VPDPBSSDSYrm 4061
+VPDPBSSDSYrr 4062
+VPDPBSSDSZ 4063
+VPDPBSSDSZrm 4064
+VPDPBSSDSZrmb 4065
+VPDPBSSDSZrmbk 4066
+VPDPBSSDSZrmbkz 4067
+VPDPBSSDSZrmk 4068
+VPDPBSSDSZrmkz 4069
+VPDPBSSDSZrr 4070
+VPDPBSSDSZrrk 4071
+VPDPBSSDSZrrkz 4072
+VPDPBSSDSrm 4073
+VPDPBSSDSrr 4074
+VPDPBSSDYrm 4075
+VPDPBSSDYrr 4076
+VPDPBSSDZ 4077
+VPDPBSSDZrm 4078
+VPDPBSSDZrmb 4079
+VPDPBSSDZrmbk 4080
+VPDPBSSDZrmbkz 4081
+VPDPBSSDZrmk 4082
+VPDPBSSDZrmkz 4083
+VPDPBSSDZrr 4084
+VPDPBSSDZrrk 4085
+VPDPBSSDZrrkz 4086
+VPDPBSSDrm 4087
+VPDPBSSDrr 4088
+VPDPBSUDSYrm 4089
+VPDPBSUDSYrr 4090
+VPDPBSUDSZ 4091
+VPDPBSUDSZrm 4092
+VPDPBSUDSZrmb 4093
+VPDPBSUDSZrmbk 4094
+VPDPBSUDSZrmbkz 4095
+VPDPBSUDSZrmk 4096
+VPDPBSUDSZrmkz 4097
+VPDPBSUDSZrr 4098
+VPDPBSUDSZrrk 4099
+VPDPBSUDSZrrkz 4100
+VPDPBSUDSrm 4101
+VPDPBSUDSrr 4102
+VPDPBSUDYrm 4103
+VPDPBSUDYrr 4104
+VPDPBSUDZ 4105
+VPDPBSUDZrm 4106
+VPDPBSUDZrmb 4107
+VPDPBSUDZrmbk 4108
+VPDPBSUDZrmbkz 4109
+VPDPBSUDZrmk 4110
+VPDPBSUDZrmkz 4111
+VPDPBSUDZrr 4112
+VPDPBSUDZrrk 4113
+VPDPBSUDZrrkz 4114
+VPDPBSUDrm 4115
+VPDPBSUDrr 4116
+VPDPBUSDSYrm 4117
+VPDPBUSDSYrr 4118
+VPDPBUSDSZ 4119
+VPDPBUSDSZrm 4120
+VPDPBUSDSZrmb 4121
+VPDPBUSDSZrmbk 4122
+VPDPBUSDSZrmbkz 4123
+VPDPBUSDSZrmk 4124
+VPDPBUSDSZrmkz 4125
+VPDPBUSDSZrr 4126
+VPDPBUSDSZrrk 4127
+VPDPBUSDSZrrkz 4128
+VPDPBUSDSrm 4129
+VPDPBUSDSrr 4130
+VPDPBUSDYrm 4131
+VPDPBUSDYrr 4132
+VPDPBUSDZ 4133
+VPDPBUSDZrm 4134
+VPDPBUSDZrmb 4135
+VPDPBUSDZrmbk 4136
+VPDPBUSDZrmbkz 4137
+VPDPBUSDZrmk 4138
+VPDPBUSDZrmkz 4139
+VPDPBUSDZrr 4140
+VPDPBUSDZrrk 4141
+VPDPBUSDZrrkz 4142
+VPDPBUSDrm 4143
+VPDPBUSDrr 4144
+VPDPBUUDSYrm 4145
+VPDPBUUDSYrr 4146
+VPDPBUUDSZ 4147
+VPDPBUUDSZrm 4148
+VPDPBUUDSZrmb 4149
+VPDPBUUDSZrmbk 4150
+VPDPBUUDSZrmbkz 4151
+VPDPBUUDSZrmk 4152
+VPDPBUUDSZrmkz 4153
+VPDPBUUDSZrr 4154
+VPDPBUUDSZrrk 4155
+VPDPBUUDSZrrkz 4156
+VPDPBUUDSrm 4157
+VPDPBUUDSrr 4158
+VPDPBUUDYrm 4159
+VPDPBUUDYrr 4160
+VPDPBUUDZ 4161
+VPDPBUUDZrm 4162
+VPDPBUUDZrmb 4163
+VPDPBUUDZrmbk 4164
+VPDPBUUDZrmbkz 4165
+VPDPBUUDZrmk 4166
+VPDPBUUDZrmkz 4167
+VPDPBUUDZrr 4168
+VPDPBUUDZrrk 4169
+VPDPBUUDZrrkz 4170
+VPDPBUUDrm 4171
+VPDPBUUDrr 4172
+VPDPWSSDSYrm 4173
+VPDPWSSDSYrr 4174
+VPDPWSSDSZ 4175
+VPDPWSSDSZrm 4176
+VPDPWSSDSZrmb 4177
+VPDPWSSDSZrmbk 4178
+VPDPWSSDSZrmbkz 4179
+VPDPWSSDSZrmk 4180
+VPDPWSSDSZrmkz 4181
+VPDPWSSDSZrr 4182
+VPDPWSSDSZrrk 4183
+VPDPWSSDSZrrkz 4184
+VPDPWSSDSrm 4185
+VPDPWSSDSrr 4186
+VPDPWSSDYrm 4187
+VPDPWSSDYrr 4188
+VPDPWSSDZ 4189
+VPDPWSSDZrm 4190
+VPDPWSSDZrmb 4191
+VPDPWSSDZrmbk 4192
+VPDPWSSDZrmbkz 4193
+VPDPWSSDZrmk 4194
+VPDPWSSDZrmkz 4195
+VPDPWSSDZrr 4196
+VPDPWSSDZrrk 4197
+VPDPWSSDZrrkz 4198
+VPDPWSSDrm 4199
+VPDPWSSDrr 4200
+VPDPWSUDSYrm 4201
+VPDPWSUDSYrr 4202
+VPDPWSUDSZ 4203
+VPDPWSUDSZrm 4204
+VPDPWSUDSZrmb 4205
+VPDPWSUDSZrmbk 4206
+VPDPWSUDSZrmbkz 4207
+VPDPWSUDSZrmk 4208
+VPDPWSUDSZrmkz 4209
+VPDPWSUDSZrr 4210
+VPDPWSUDSZrrk 4211
+VPDPWSUDSZrrkz 4212
+VPDPWSUDSrm 4213
+VPDPWSUDSrr 4214
+VPDPWSUDYrm 4215
+VPDPWSUDYrr 4216
+VPDPWSUDZ 4217
+VPDPWSUDZrm 4218
+VPDPWSUDZrmb 4219
+VPDPWSUDZrmbk 4220
+VPDPWSUDZrmbkz 4221
+VPDPWSUDZrmk 4222
+VPDPWSUDZrmkz 4223
+VPDPWSUDZrr 4224
+VPDPWSUDZrrk 4225
+VPDPWSUDZrrkz 4226
+VPDPWSUDrm 4227
+VPDPWSUDrr 4228
+VPDPWUSDSYrm 4229
+VPDPWUSDSYrr 4230
+VPDPWUSDSZ 4231
+VPDPWUSDSZrm 4232
+VPDPWUSDSZrmb 4233
+VPDPWUSDSZrmbk 4234
+VPDPWUSDSZrmbkz 4235
+VPDPWUSDSZrmk 4236
+VPDPWUSDSZrmkz 4237
+VPDPWUSDSZrr 4238
+VPDPWUSDSZrrk 4239
+VPDPWUSDSZrrkz 4240
+VPDPWUSDSrm 4241
+VPDPWUSDSrr 4242
+VPDPWUSDYrm 4243
+VPDPWUSDYrr 4244
+VPDPWUSDZ 4245
+VPDPWUSDZrm 4246
+VPDPWUSDZrmb 4247
+VPDPWUSDZrmbk 4248
+VPDPWUSDZrmbkz 4249
+VPDPWUSDZrmk 4250
+VPDPWUSDZrmkz 4251
+VPDPWUSDZrr 4252
+VPDPWUSDZrrk 4253
+VPDPWUSDZrrkz 4254
+VPDPWUSDrm 4255
+VPDPWUSDrr 4256
+VPDPWUUDSYrm 4257
+VPDPWUUDSYrr 4258
+VPDPWUUDSZ 4259
+VPDPWUUDSZrm 4260
+VPDPWUUDSZrmb 4261
+VPDPWUUDSZrmbk 4262
+VPDPWUUDSZrmbkz 4263
+VPDPWUUDSZrmk 4264
+VPDPWUUDSZrmkz 4265
+VPDPWUUDSZrr 4266
+VPDPWUUDSZrrk 4267
+VPDPWUUDSZrrkz 4268
+VPDPWUUDSrm 4269
+VPDPWUUDSrr 4270
+VPDPWUUDYrm 4271
+VPDPWUUDYrr 4272
+VPDPWUUDZ 4273
+VPDPWUUDZrm 4274
+VPDPWUUDZrmb 4275
+VPDPWUUDZrmbk 4276
+VPDPWUUDZrmbkz 4277
+VPDPWUUDZrmk 4278
+VPDPWUUDZrmkz 4279
+VPDPWUUDZrr 4280
+VPDPWUUDZrrk 4281
+VPDPWUUDZrrkz 4282
+VPDPWUUDrm 4283
+VPDPWUUDrr 4284
+VPERM 4285
+VPERMBZ 4286
+VPERMBZrm 4287
+VPERMBZrmk 4288
+VPERMBZrmkz 4289
+VPERMBZrr 4290
+VPERMBZrrk 4291
+VPERMBZrrkz 4292
+VPERMDYrm 4293
+VPERMDYrr 4294
+VPERMDZ 4295
+VPERMDZrm 4296
+VPERMDZrmb 4297
+VPERMDZrmbk 4298
+VPERMDZrmbkz 4299
+VPERMDZrmk 4300
+VPERMDZrmkz 4301
+VPERMDZrr 4302
+VPERMDZrrk 4303
+VPERMDZrrkz 4304
+VPERMI 4305
+VPERMIL 4306
+VPERMILPDYmi 4307
+VPERMILPDYri 4308
+VPERMILPDYrm 4309
+VPERMILPDYrr 4310
+VPERMILPDZ 4311
+VPERMILPDZmbi 4312
+VPERMILPDZmbik 4313
+VPERMILPDZmbikz 4314
+VPERMILPDZmi 4315
+VPERMILPDZmik 4316
+VPERMILPDZmikz 4317
+VPERMILPDZri 4318
+VPERMILPDZrik 4319
+VPERMILPDZrikz 4320
+VPERMILPDZrm 4321
+VPERMILPDZrmb 4322
+VPERMILPDZrmbk 4323
+VPERMILPDZrmbkz 4324
+VPERMILPDZrmk 4325
+VPERMILPDZrmkz 4326
+VPERMILPDZrr 4327
+VPERMILPDZrrk 4328
+VPERMILPDZrrkz 4329
+VPERMILPDmi 4330
+VPERMILPDri 4331
+VPERMILPDrm 4332
+VPERMILPDrr 4333
+VPERMILPSYmi 4334
+VPERMILPSYri 4335
+VPERMILPSYrm 4336
+VPERMILPSYrr 4337
+VPERMILPSZ 4338
+VPERMILPSZmbi 4339
+VPERMILPSZmbik 4340
+VPERMILPSZmbikz 4341
+VPERMILPSZmi 4342
+VPERMILPSZmik 4343
+VPERMILPSZmikz 4344
+VPERMILPSZri 4345
+VPERMILPSZrik 4346
+VPERMILPSZrikz 4347
+VPERMILPSZrm 4348
+VPERMILPSZrmb 4349
+VPERMILPSZrmbk 4350
+VPERMILPSZrmbkz 4351
+VPERMILPSZrmk 4352
+VPERMILPSZrmkz 4353
+VPERMILPSZrr 4354
+VPERMILPSZrrk 4355
+VPERMILPSZrrkz 4356
+VPERMILPSmi 4357
+VPERMILPSri 4358
+VPERMILPSrm 4359
+VPERMILPSrr 4360
+VPERMPDYmi 4361
+VPERMPDYri 4362
+VPERMPDZ 4363
+VPERMPDZmbi 4364
+VPERMPDZmbik 4365
+VPERMPDZmbikz 4366
+VPERMPDZmi 4367
+VPERMPDZmik 4368
+VPERMPDZmikz 4369
+VPERMPDZri 4370
+VPERMPDZrik 4371
+VPERMPDZrikz 4372
+VPERMPDZrm 4373
+VPERMPDZrmb 4374
+VPERMPDZrmbk 4375
+VPERMPDZrmbkz 4376
+VPERMPDZrmk 4377
+VPERMPDZrmkz 4378
+VPERMPDZrr 4379
+VPERMPDZrrk 4380
+VPERMPDZrrkz 4381
+VPERMPSYrm 4382
+VPERMPSYrr 4383
+VPERMPSZ 4384
+VPERMPSZrm 4385
+VPERMPSZrmb 4386
+VPERMPSZrmbk 4387
+VPERMPSZrmbkz 4388
+VPERMPSZrmk 4389
+VPERMPSZrmkz 4390
+VPERMPSZrr 4391
+VPERMPSZrrk 4392
+VPERMPSZrrkz 4393
+VPERMQYmi 4394
+VPERMQYri 4395
+VPERMQZ 4396
+VPERMQZmbi 4397
+VPERMQZmbik 4398
+VPERMQZmbikz 4399
+VPERMQZmi 4400
+VPERMQZmik 4401
+VPERMQZmikz 4402
+VPERMQZri 4403
+VPERMQZrik 4404
+VPERMQZrikz 4405
+VPERMQZrm 4406
+VPERMQZrmb 4407
+VPERMQZrmbk 4408
+VPERMQZrmbkz 4409
+VPERMQZrmk 4410
+VPERMQZrmkz 4411
+VPERMQZrr 4412
+VPERMQZrrk 4413
+VPERMQZrrkz 4414
+VPERMT 4415
+VPERMWZ 4416
+VPERMWZrm 4417
+VPERMWZrmk 4418
+VPERMWZrmkz 4419
+VPERMWZrr 4420
+VPERMWZrrk 4421
+VPERMWZrrkz 4422
+VPEXPANDBZ 4423
+VPEXPANDBZrm 4424
+VPEXPANDBZrmk 4425
+VPEXPANDBZrmkz 4426
+VPEXPANDBZrr 4427
+VPEXPANDBZrrk 4428
+VPEXPANDBZrrkz 4429
+VPEXPANDDZ 4430
+VPEXPANDDZrm 4431
+VPEXPANDDZrmk 4432
+VPEXPANDDZrmkz 4433
+VPEXPANDDZrr 4434
+VPEXPANDDZrrk 4435
+VPEXPANDDZrrkz 4436
+VPEXPANDQZ 4437
+VPEXPANDQZrm 4438
+VPEXPANDQZrmk 4439
+VPEXPANDQZrmkz 4440
+VPEXPANDQZrr 4441
+VPEXPANDQZrrk 4442
+VPEXPANDQZrrkz 4443
+VPEXPANDWZ 4444
+VPEXPANDWZrm 4445
+VPEXPANDWZrmk 4446
+VPEXPANDWZrmkz 4447
+VPEXPANDWZrr 4448
+VPEXPANDWZrrk 4449
+VPEXPANDWZrrkz 4450
+VPEXTRBZmri 4451
+VPEXTRBZrri 4452
+VPEXTRBmri 4453
+VPEXTRBrri 4454
+VPEXTRDZmri 4455
+VPEXTRDZrri 4456
+VPEXTRDmri 4457
+VPEXTRDrri 4458
+VPEXTRQZmri 4459
+VPEXTRQZrri 4460
+VPEXTRQmri 4461
+VPEXTRQrri 4462
+VPEXTRWZmri 4463
+VPEXTRWZrri 4464
+VPEXTRWZrri_REV 4465
+VPEXTRWmri 4466
+VPEXTRWrri 4467
+VPEXTRWrri_REV 4468
+VPGATHERDDYrm 4469
+VPGATHERDDZ 4470
+VPGATHERDDZrm 4471
+VPGATHERDDrm 4472
+VPGATHERDQYrm 4473
+VPGATHERDQZ 4474
+VPGATHERDQZrm 4475
+VPGATHERDQrm 4476
+VPGATHERQDYrm 4477
+VPGATHERQDZ 4478
+VPGATHERQDZrm 4479
+VPGATHERQDrm 4480
+VPGATHERQQYrm 4481
+VPGATHERQQZ 4482
+VPGATHERQQZrm 4483
+VPGATHERQQrm 4484
+VPHADDBDrm 4485
+VPHADDBDrr 4486
+VPHADDBQrm 4487
+VPHADDBQrr 4488
+VPHADDBWrm 4489
+VPHADDBWrr 4490
+VPHADDDQrm 4491
+VPHADDDQrr 4492
+VPHADDDYrm 4493
+VPHADDDYrr 4494
+VPHADDDrm 4495
+VPHADDDrr 4496
+VPHADDSWYrm 4497
+VPHADDSWYrr 4498
+VPHADDSWrm 4499
+VPHADDSWrr 4500
+VPHADDUBDrm 4501
+VPHADDUBDrr 4502
+VPHADDUBQrm 4503
+VPHADDUBQrr 4504
+VPHADDUBWrm 4505
+VPHADDUBWrr 4506
+VPHADDUDQrm 4507
+VPHADDUDQrr 4508
+VPHADDUWDrm 4509
+VPHADDUWDrr 4510
+VPHADDUWQrm 4511
+VPHADDUWQrr 4512
+VPHADDWDrm 4513
+VPHADDWDrr 4514
+VPHADDWQrm 4515
+VPHADDWQrr 4516
+VPHADDWYrm 4517
+VPHADDWYrr 4518
+VPHADDWrm 4519
+VPHADDWrr 4520
+VPHMINPOSUWrm 4521
+VPHMINPOSUWrr 4522
+VPHSUBBWrm 4523
+VPHSUBBWrr 4524
+VPHSUBDQrm 4525
+VPHSUBDQrr 4526
+VPHSUBDYrm 4527
+VPHSUBDYrr 4528
+VPHSUBDrm 4529
+VPHSUBDrr 4530
+VPHSUBSWYrm 4531
+VPHSUBSWYrr 4532
+VPHSUBSWrm 4533
+VPHSUBSWrr 4534
+VPHSUBWDrm 4535
+VPHSUBWDrr 4536
+VPHSUBWYrm 4537
+VPHSUBWYrr 4538
+VPHSUBWrm 4539
+VPHSUBWrr 4540
+VPINSRBZrmi 4541
+VPINSRBZrri 4542
+VPINSRBrmi 4543
+VPINSRBrri 4544
+VPINSRDZrmi 4545
+VPINSRDZrri 4546
+VPINSRDrmi 4547
+VPINSRDrri 4548
+VPINSRQZrmi 4549
+VPINSRQZrri 4550
+VPINSRQrmi 4551
+VPINSRQrri 4552
+VPINSRWZrmi 4553
+VPINSRWZrri 4554
+VPINSRWrmi 4555
+VPINSRWrri 4556
+VPLZCNTDZ 4557
+VPLZCNTDZrm 4558
+VPLZCNTDZrmb 4559
+VPLZCNTDZrmbk 4560
+VPLZCNTDZrmbkz 4561
+VPLZCNTDZrmk 4562
+VPLZCNTDZrmkz 4563
+VPLZCNTDZrr 4564
+VPLZCNTDZrrk 4565
+VPLZCNTDZrrkz 4566
+VPLZCNTQZ 4567
+VPLZCNTQZrm 4568
+VPLZCNTQZrmb 4569
+VPLZCNTQZrmbk 4570
+VPLZCNTQZrmbkz 4571
+VPLZCNTQZrmk 4572
+VPLZCNTQZrmkz 4573
+VPLZCNTQZrr 4574
+VPLZCNTQZrrk 4575
+VPLZCNTQZrrkz 4576
+VPMACSDDrm 4577
+VPMACSDDrr 4578
+VPMACSDQHrm 4579
+VPMACSDQHrr 4580
+VPMACSDQLrm 4581
+VPMACSDQLrr 4582
+VPMACSSDDrm 4583
+VPMACSSDDrr 4584
+VPMACSSDQHrm 4585
+VPMACSSDQHrr 4586
+VPMACSSDQLrm 4587
+VPMACSSDQLrr 4588
+VPMACSSWDrm 4589
+VPMACSSWDrr 4590
+VPMACSSWWrm 4591
+VPMACSSWWrr 4592
+VPMACSWDrm 4593
+VPMACSWDrr 4594
+VPMACSWWrm 4595
+VPMACSWWrr 4596
+VPMADCSSWDrm 4597
+VPMADCSSWDrr 4598
+VPMADCSWDrm 4599
+VPMADCSWDrr 4600
+VPMADD 4601
+VPMADDUBSWYrm 4602
+VPMADDUBSWYrr 4603
+VPMADDUBSWZ 4604
+VPMADDUBSWZrm 4605
+VPMADDUBSWZrmk 4606
+VPMADDUBSWZrmkz 4607
+VPMADDUBSWZrr 4608
+VPMADDUBSWZrrk 4609
+VPMADDUBSWZrrkz 4610
+VPMADDUBSWrm 4611
+VPMADDUBSWrr 4612
+VPMADDWDYrm 4613
+VPMADDWDYrr 4614
+VPMADDWDZ 4615
+VPMADDWDZrm 4616
+VPMADDWDZrmk 4617
+VPMADDWDZrmkz 4618
+VPMADDWDZrr 4619
+VPMADDWDZrrk 4620
+VPMADDWDZrrkz 4621
+VPMADDWDrm 4622
+VPMADDWDrr 4623
+VPMASKMOVDYmr 4624
+VPMASKMOVDYrm 4625
+VPMASKMOVDmr 4626
+VPMASKMOVDrm 4627
+VPMASKMOVQYmr 4628
+VPMASKMOVQYrm 4629
+VPMASKMOVQmr 4630
+VPMASKMOVQrm 4631
+VPMAXSBYrm 4632
+VPMAXSBYrr 4633
+VPMAXSBZ 4634
+VPMAXSBZrm 4635
+VPMAXSBZrmk 4636
+VPMAXSBZrmkz 4637
+VPMAXSBZrr 4638
+VPMAXSBZrrk 4639
+VPMAXSBZrrkz 4640
+VPMAXSBrm 4641
+VPMAXSBrr 4642
+VPMAXSDYrm 4643
+VPMAXSDYrr 4644
+VPMAXSDZ 4645
+VPMAXSDZrm 4646
+VPMAXSDZrmb 4647
+VPMAXSDZrmbk 4648
+VPMAXSDZrmbkz 4649
+VPMAXSDZrmk 4650
+VPMAXSDZrmkz 4651
+VPMAXSDZrr 4652
+VPMAXSDZrrk 4653
+VPMAXSDZrrkz 4654
+VPMAXSDrm 4655
+VPMAXSDrr 4656
+VPMAXSQZ 4657
+VPMAXSQZrm 4658
+VPMAXSQZrmb 4659
+VPMAXSQZrmbk 4660
+VPMAXSQZrmbkz 4661
+VPMAXSQZrmk 4662
+VPMAXSQZrmkz 4663
+VPMAXSQZrr 4664
+VPMAXSQZrrk 4665
+VPMAXSQZrrkz 4666
+VPMAXSWYrm 4667
+VPMAXSWYrr 4668
+VPMAXSWZ 4669
+VPMAXSWZrm 4670
+VPMAXSWZrmk 4671
+VPMAXSWZrmkz 4672
+VPMAXSWZrr 4673
+VPMAXSWZrrk 4674
+VPMAXSWZrrkz 4675
+VPMAXSWrm 4676
+VPMAXSWrr 4677
+VPMAXUBYrm 4678
+VPMAXUBYrr 4679
+VPMAXUBZ 4680
+VPMAXUBZrm 4681
+VPMAXUBZrmk 4682
+VPMAXUBZrmkz 4683
+VPMAXUBZrr 4684
+VPMAXUBZrrk 4685
+VPMAXUBZrrkz 4686
+VPMAXUBrm 4687
+VPMAXUBrr 4688
+VPMAXUDYrm 4689
+VPMAXUDYrr 4690
+VPMAXUDZ 4691
+VPMAXUDZrm 4692
+VPMAXUDZrmb 4693
+VPMAXUDZrmbk 4694
+VPMAXUDZrmbkz 4695
+VPMAXUDZrmk 4696
+VPMAXUDZrmkz 4697
+VPMAXUDZrr 4698
+VPMAXUDZrrk 4699
+VPMAXUDZrrkz 4700
+VPMAXUDrm 4701
+VPMAXUDrr 4702
+VPMAXUQZ 4703
+VPMAXUQZrm 4704
+VPMAXUQZrmb 4705
+VPMAXUQZrmbk 4706
+VPMAXUQZrmbkz 4707
+VPMAXUQZrmk 4708
+VPMAXUQZrmkz 4709
+VPMAXUQZrr 4710
+VPMAXUQZrrk 4711
+VPMAXUQZrrkz 4712
+VPMAXUWYrm 4713
+VPMAXUWYrr 4714
+VPMAXUWZ 4715
+VPMAXUWZrm 4716
+VPMAXUWZrmk 4717
+VPMAXUWZrmkz 4718
+VPMAXUWZrr 4719
+VPMAXUWZrrk 4720
+VPMAXUWZrrkz 4721
+VPMAXUWrm 4722
+VPMAXUWrr 4723
+VPMINSBYrm 4724
+VPMINSBYrr 4725
+VPMINSBZ 4726
+VPMINSBZrm 4727
+VPMINSBZrmk 4728
+VPMINSBZrmkz 4729
+VPMINSBZrr 4730
+VPMINSBZrrk 4731
+VPMINSBZrrkz 4732
+VPMINSBrm 4733
+VPMINSBrr 4734
+VPMINSDYrm 4735
+VPMINSDYrr 4736
+VPMINSDZ 4737
+VPMINSDZrm 4738
+VPMINSDZrmb 4739
+VPMINSDZrmbk 4740
+VPMINSDZrmbkz 4741
+VPMINSDZrmk 4742
+VPMINSDZrmkz 4743
+VPMINSDZrr 4744
+VPMINSDZrrk 4745
+VPMINSDZrrkz 4746
+VPMINSDrm 4747
+VPMINSDrr 4748
+VPMINSQZ 4749
+VPMINSQZrm 4750
+VPMINSQZrmb 4751
+VPMINSQZrmbk 4752
+VPMINSQZrmbkz 4753
+VPMINSQZrmk 4754
+VPMINSQZrmkz 4755
+VPMINSQZrr 4756
+VPMINSQZrrk 4757
+VPMINSQZrrkz 4758
+VPMINSWYrm 4759
+VPMINSWYrr 4760
+VPMINSWZ 4761
+VPMINSWZrm 4762
+VPMINSWZrmk 4763
+VPMINSWZrmkz 4764
+VPMINSWZrr 4765
+VPMINSWZrrk 4766
+VPMINSWZrrkz 4767
+VPMINSWrm 4768
+VPMINSWrr 4769
+VPMINUBYrm 4770
+VPMINUBYrr 4771
+VPMINUBZ 4772
+VPMINUBZrm 4773
+VPMINUBZrmk 4774
+VPMINUBZrmkz 4775
+VPMINUBZrr 4776
+VPMINUBZrrk 4777
+VPMINUBZrrkz 4778
+VPMINUBrm 4779
+VPMINUBrr 4780
+VPMINUDYrm 4781
+VPMINUDYrr 4782
+VPMINUDZ 4783
+VPMINUDZrm 4784
+VPMINUDZrmb 4785
+VPMINUDZrmbk 4786
+VPMINUDZrmbkz 4787
+VPMINUDZrmk 4788
+VPMINUDZrmkz 4789
+VPMINUDZrr 4790
+VPMINUDZrrk 4791
+VPMINUDZrrkz 4792
+VPMINUDrm 4793
+VPMINUDrr 4794
+VPMINUQZ 4795
+VPMINUQZrm 4796
+VPMINUQZrmb 4797
+VPMINUQZrmbk 4798
+VPMINUQZrmbkz 4799
+VPMINUQZrmk 4800
+VPMINUQZrmkz 4801
+VPMINUQZrr 4802
+VPMINUQZrrk 4803
+VPMINUQZrrkz 4804
+VPMINUWYrm 4805
+VPMINUWYrr 4806
+VPMINUWZ 4807
+VPMINUWZrm 4808
+VPMINUWZrmk 4809
+VPMINUWZrmkz 4810
+VPMINUWZrr 4811
+VPMINUWZrrk 4812
+VPMINUWZrrkz 4813
+VPMINUWrm 4814
+VPMINUWrr 4815
+VPMOVB 4816
+VPMOVD 4817
+VPMOVDBZ 4818
+VPMOVDBZmr 4819
+VPMOVDBZmrk 4820
+VPMOVDBZrr 4821
+VPMOVDBZrrk 4822
+VPMOVDBZrrkz 4823
+VPMOVDWZ 4824
+VPMOVDWZmr 4825
+VPMOVDWZmrk 4826
+VPMOVDWZrr 4827
+VPMOVDWZrrk 4828
+VPMOVDWZrrkz 4829
+VPMOVM 4830
+VPMOVMSKBYrr 4831
+VPMOVMSKBrr 4832
+VPMOVQ 4833
+VPMOVQBZ 4834
+VPMOVQBZmr 4835
+VPMOVQBZmrk 4836
+VPMOVQBZrr 4837
+VPMOVQBZrrk 4838
+VPMOVQBZrrkz 4839
+VPMOVQDZ 4840
+VPMOVQDZmr 4841
+VPMOVQDZmrk 4842
+VPMOVQDZrr 4843
+VPMOVQDZrrk 4844
+VPMOVQDZrrkz 4845
+VPMOVQWZ 4846
+VPMOVQWZmr 4847
+VPMOVQWZmrk 4848
+VPMOVQWZrr 4849
+VPMOVQWZrrk 4850
+VPMOVQWZrrkz 4851
+VPMOVSDBZ 4852
+VPMOVSDBZmr 4853
+VPMOVSDBZmrk 4854
+VPMOVSDBZrr 4855
+VPMOVSDBZrrk 4856
+VPMOVSDBZrrkz 4857
+VPMOVSDWZ 4858
+VPMOVSDWZmr 4859
+VPMOVSDWZmrk 4860
+VPMOVSDWZrr 4861
+VPMOVSDWZrrk 4862
+VPMOVSDWZrrkz 4863
+VPMOVSQBZ 4864
+VPMOVSQBZmr 4865
+VPMOVSQBZmrk 4866
+VPMOVSQBZrr 4867
+VPMOVSQBZrrk 4868
+VPMOVSQBZrrkz 4869
+VPMOVSQDZ 4870
+VPMOVSQDZmr 4871
+VPMOVSQDZmrk 4872
+VPMOVSQDZrr 4873
+VPMOVSQDZrrk 4874
+VPMOVSQDZrrkz 4875
+VPMOVSQWZ 4876
+VPMOVSQWZmr 4877
+VPMOVSQWZmrk 4878
+VPMOVSQWZrr 4879
+VPMOVSQWZrrk 4880
+VPMOVSQWZrrkz 4881
+VPMOVSWBZ 4882
+VPMOVSWBZmr 4883
+VPMOVSWBZmrk 4884
+VPMOVSWBZrr 4885
+VPMOVSWBZrrk 4886
+VPMOVSWBZrrkz 4887
+VPMOVSXBDYrm 4888
+VPMOVSXBDYrr 4889
+VPMOVSXBDZ 4890
+VPMOVSXBDZrm 4891
+VPMOVSXBDZrmk 4892
+VPMOVSXBDZrmkz 4893
+VPMOVSXBDZrr 4894
+VPMOVSXBDZrrk 4895
+VPMOVSXBDZrrkz 4896
+VPMOVSXBDrm 4897
+VPMOVSXBDrr 4898
+VPMOVSXBQYrm 4899
+VPMOVSXBQYrr 4900
+VPMOVSXBQZ 4901
+VPMOVSXBQZrm 4902
+VPMOVSXBQZrmk 4903
+VPMOVSXBQZrmkz 4904
+VPMOVSXBQZrr 4905
+VPMOVSXBQZrrk 4906
+VPMOVSXBQZrrkz 4907
+VPMOVSXBQrm 4908
+VPMOVSXBQrr 4909
+VPMOVSXBWYrm 4910
+VPMOVSXBWYrr 4911
+VPMOVSXBWZ 4912
+VPMOVSXBWZrm 4913
+VPMOVSXBWZrmk 4914
+VPMOVSXBWZrmkz 4915
+VPMOVSXBWZrr 4916
+VPMOVSXBWZrrk 4917
+VPMOVSXBWZrrkz 4918
+VPMOVSXBWrm 4919
+VPMOVSXBWrr 4920
+VPMOVSXDQYrm 4921
+VPMOVSXDQYrr 4922
+VPMOVSXDQZ 4923
+VPMOVSXDQZrm 4924
+VPMOVSXDQZrmk 4925
+VPMOVSXDQZrmkz 4926
+VPMOVSXDQZrr 4927
+VPMOVSXDQZrrk 4928
+VPMOVSXDQZrrkz 4929
+VPMOVSXDQrm 4930
+VPMOVSXDQrr 4931
+VPMOVSXWDYrm 4932
+VPMOVSXWDYrr 4933
+VPMOVSXWDZ 4934
+VPMOVSXWDZrm 4935
+VPMOVSXWDZrmk 4936
+VPMOVSXWDZrmkz 4937
+VPMOVSXWDZrr 4938
+VPMOVSXWDZrrk 4939
+VPMOVSXWDZrrkz 4940
+VPMOVSXWDrm 4941
+VPMOVSXWDrr 4942
+VPMOVSXWQYrm 4943
+VPMOVSXWQYrr 4944
+VPMOVSXWQZ 4945
+VPMOVSXWQZrm 4946
+VPMOVSXWQZrmk 4947
+VPMOVSXWQZrmkz 4948
+VPMOVSXWQZrr 4949
+VPMOVSXWQZrrk 4950
+VPMOVSXWQZrrkz 4951
+VPMOVSXWQrm 4952
+VPMOVSXWQrr 4953
+VPMOVUSDBZ 4954
+VPMOVUSDBZmr 4955
+VPMOVUSDBZmrk 4956
+VPMOVUSDBZrr 4957
+VPMOVUSDBZrrk 4958
+VPMOVUSDBZrrkz 4959
+VPMOVUSDWZ 4960
+VPMOVUSDWZmr 4961
+VPMOVUSDWZmrk 4962
+VPMOVUSDWZrr 4963
+VPMOVUSDWZrrk 4964
+VPMOVUSDWZrrkz 4965
+VPMOVUSQBZ 4966
+VPMOVUSQBZmr 4967
+VPMOVUSQBZmrk 4968
+VPMOVUSQBZrr 4969
+VPMOVUSQBZrrk 4970
+VPMOVUSQBZrrkz 4971
+VPMOVUSQDZ 4972
+VPMOVUSQDZmr 4973
+VPMOVUSQDZmrk 4974
+VPMOVUSQDZrr 4975
+VPMOVUSQDZrrk 4976
+VPMOVUSQDZrrkz 4977
+VPMOVUSQWZ 4978
+VPMOVUSQWZmr 4979
+VPMOVUSQWZmrk 4980
+VPMOVUSQWZrr 4981
+VPMOVUSQWZrrk 4982
+VPMOVUSQWZrrkz 4983
+VPMOVUSWBZ 4984
+VPMOVUSWBZmr 4985
+VPMOVUSWBZmrk 4986
+VPMOVUSWBZrr 4987
+VPMOVUSWBZrrk 4988
+VPMOVUSWBZrrkz 4989
+VPMOVW 4990
+VPMOVWBZ 4991
+VPMOVWBZmr 4992
+VPMOVWBZmrk 4993
+VPMOVWBZrr 4994
+VPMOVWBZrrk 4995
+VPMOVWBZrrkz 4996
+VPMOVZXBDYrm 4997
+VPMOVZXBDYrr 4998
+VPMOVZXBDZ 4999
+VPMOVZXBDZrm 5000
+VPMOVZXBDZrmk 5001
+VPMOVZXBDZrmkz 5002
+VPMOVZXBDZrr 5003
+VPMOVZXBDZrrk 5004
+VPMOVZXBDZrrkz 5005
+VPMOVZXBDrm 5006
+VPMOVZXBDrr 5007
+VPMOVZXBQYrm 5008
+VPMOVZXBQYrr 5009
+VPMOVZXBQZ 5010
+VPMOVZXBQZrm 5011
+VPMOVZXBQZrmk 5012
+VPMOVZXBQZrmkz 5013
+VPMOVZXBQZrr 5014
+VPMOVZXBQZrrk 5015
+VPMOVZXBQZrrkz 5016
+VPMOVZXBQrm 5017
+VPMOVZXBQrr 5018
+VPMOVZXBWYrm 5019
+VPMOVZXBWYrr 5020
+VPMOVZXBWZ 5021
+VPMOVZXBWZrm 5022
+VPMOVZXBWZrmk 5023
+VPMOVZXBWZrmkz 5024
+VPMOVZXBWZrr 5025
+VPMOVZXBWZrrk 5026
+VPMOVZXBWZrrkz 5027
+VPMOVZXBWrm 5028
+VPMOVZXBWrr 5029
+VPMOVZXDQYrm 5030
+VPMOVZXDQYrr 5031
+VPMOVZXDQZ 5032
+VPMOVZXDQZrm 5033
+VPMOVZXDQZrmk 5034
+VPMOVZXDQZrmkz 5035
+VPMOVZXDQZrr 5036
+VPMOVZXDQZrrk 5037
+VPMOVZXDQZrrkz 5038
+VPMOVZXDQrm 5039
+VPMOVZXDQrr 5040
+VPMOVZXWDYrm 5041
+VPMOVZXWDYrr 5042
+VPMOVZXWDZ 5043
+VPMOVZXWDZrm 5044
+VPMOVZXWDZrmk 5045
+VPMOVZXWDZrmkz 5046
+VPMOVZXWDZrr 5047
+VPMOVZXWDZrrk 5048
+VPMOVZXWDZrrkz 5049
+VPMOVZXWDrm 5050
+VPMOVZXWDrr 5051
+VPMOVZXWQYrm 5052
+VPMOVZXWQYrr 5053
+VPMOVZXWQZ 5054
+VPMOVZXWQZrm 5055
+VPMOVZXWQZrmk 5056
+VPMOVZXWQZrmkz 5057
+VPMOVZXWQZrr 5058
+VPMOVZXWQZrrk 5059
+VPMOVZXWQZrrkz 5060
+VPMOVZXWQrm 5061
+VPMOVZXWQrr 5062
+VPMULDQYrm 5063
+VPMULDQYrr 5064
+VPMULDQZ 5065
+VPMULDQZrm 5066
+VPMULDQZrmb 5067
+VPMULDQZrmbk 5068
+VPMULDQZrmbkz 5069
+VPMULDQZrmk 5070
+VPMULDQZrmkz 5071
+VPMULDQZrr 5072
+VPMULDQZrrk 5073
+VPMULDQZrrkz 5074
+VPMULDQrm 5075
+VPMULDQrr 5076
+VPMULHRSWYrm 5077
+VPMULHRSWYrr 5078
+VPMULHRSWZ 5079
+VPMULHRSWZrm 5080
+VPMULHRSWZrmk 5081
+VPMULHRSWZrmkz 5082
+VPMULHRSWZrr 5083
+VPMULHRSWZrrk 5084
+VPMULHRSWZrrkz 5085
+VPMULHRSWrm 5086
+VPMULHRSWrr 5087
+VPMULHUWYrm 5088
+VPMULHUWYrr 5089
+VPMULHUWZ 5090
+VPMULHUWZrm 5091
+VPMULHUWZrmk 5092
+VPMULHUWZrmkz 5093
+VPMULHUWZrr 5094
+VPMULHUWZrrk 5095
+VPMULHUWZrrkz 5096
+VPMULHUWrm 5097
+VPMULHUWrr 5098
+VPMULHWYrm 5099
+VPMULHWYrr 5100
+VPMULHWZ 5101
+VPMULHWZrm 5102
+VPMULHWZrmk 5103
+VPMULHWZrmkz 5104
+VPMULHWZrr 5105
+VPMULHWZrrk 5106
+VPMULHWZrrkz 5107
+VPMULHWrm 5108
+VPMULHWrr 5109
+VPMULLDYrm 5110
+VPMULLDYrr 5111
+VPMULLDZ 5112
+VPMULLDZrm 5113
+VPMULLDZrmb 5114
+VPMULLDZrmbk 5115
+VPMULLDZrmbkz 5116
+VPMULLDZrmk 5117
+VPMULLDZrmkz 5118
+VPMULLDZrr 5119
+VPMULLDZrrk 5120
+VPMULLDZrrkz 5121
+VPMULLDrm 5122
+VPMULLDrr 5123
+VPMULLQZ 5124
+VPMULLQZrm 5125
+VPMULLQZrmb 5126
+VPMULLQZrmbk 5127
+VPMULLQZrmbkz 5128
+VPMULLQZrmk 5129
+VPMULLQZrmkz 5130
+VPMULLQZrr 5131
+VPMULLQZrrk 5132
+VPMULLQZrrkz 5133
+VPMULLWYrm 5134
+VPMULLWYrr 5135
+VPMULLWZ 5136
+VPMULLWZrm 5137
+VPMULLWZrmk 5138
+VPMULLWZrmkz 5139
+VPMULLWZrr 5140
+VPMULLWZrrk 5141
+VPMULLWZrrkz 5142
+VPMULLWrm 5143
+VPMULLWrr 5144
+VPMULTISHIFTQBZ 5145
+VPMULTISHIFTQBZrm 5146
+VPMULTISHIFTQBZrmb 5147
+VPMULTISHIFTQBZrmbk 5148
+VPMULTISHIFTQBZrmbkz 5149
+VPMULTISHIFTQBZrmk 5150
+VPMULTISHIFTQBZrmkz 5151
+VPMULTISHIFTQBZrr 5152
+VPMULTISHIFTQBZrrk 5153
+VPMULTISHIFTQBZrrkz 5154
+VPMULUDQYrm 5155
+VPMULUDQYrr 5156
+VPMULUDQZ 5157
+VPMULUDQZrm 5158
+VPMULUDQZrmb 5159
+VPMULUDQZrmbk 5160
+VPMULUDQZrmbkz 5161
+VPMULUDQZrmk 5162
+VPMULUDQZrmkz 5163
+VPMULUDQZrr 5164
+VPMULUDQZrrk 5165
+VPMULUDQZrrkz 5166
+VPMULUDQrm 5167
+VPMULUDQrr 5168
+VPOPCNTBZ 5169
+VPOPCNTBZrm 5170
+VPOPCNTBZrmk 5171
+VPOPCNTBZrmkz 5172
+VPOPCNTBZrr 5173
+VPOPCNTBZrrk 5174
+VPOPCNTBZrrkz 5175
+VPOPCNTDZ 5176
+VPOPCNTDZrm 5177
+VPOPCNTDZrmb 5178
+VPOPCNTDZrmbk 5179
+VPOPCNTDZrmbkz 5180
+VPOPCNTDZrmk 5181
+VPOPCNTDZrmkz 5182
+VPOPCNTDZrr 5183
+VPOPCNTDZrrk 5184
+VPOPCNTDZrrkz 5185
+VPOPCNTQZ 5186
+VPOPCNTQZrm 5187
+VPOPCNTQZrmb 5188
+VPOPCNTQZrmbk 5189
+VPOPCNTQZrmbkz 5190
+VPOPCNTQZrmk 5191
+VPOPCNTQZrmkz 5192
+VPOPCNTQZrr 5193
+VPOPCNTQZrrk 5194
+VPOPCNTQZrrkz 5195
+VPOPCNTWZ 5196
+VPOPCNTWZrm 5197
+VPOPCNTWZrmk 5198
+VPOPCNTWZrmkz 5199
+VPOPCNTWZrr 5200
+VPOPCNTWZrrk 5201
+VPOPCNTWZrrkz 5202
+VPORDZ 5203
+VPORDZrm 5204
+VPORDZrmb 5205
+VPORDZrmbk 5206
+VPORDZrmbkz 5207
+VPORDZrmk 5208
+VPORDZrmkz 5209
+VPORDZrr 5210
+VPORDZrrk 5211
+VPORDZrrkz 5212
+VPORQZ 5213
+VPORQZrm 5214
+VPORQZrmb 5215
+VPORQZrmbk 5216
+VPORQZrmbkz 5217
+VPORQZrmk 5218
+VPORQZrmkz 5219
+VPORQZrr 5220
+VPORQZrrk 5221
+VPORQZrrkz 5222
+VPORYrm 5223
+VPORYrr 5224
+VPORrm 5225
+VPORrr 5226
+VPPERMrmr 5227
+VPPERMrrm 5228
+VPPERMrrr 5229
+VPPERMrrr_REV 5230
+VPROLDZ 5231
+VPROLDZmbi 5232
+VPROLDZmbik 5233
+VPROLDZmbikz 5234
+VPROLDZmi 5235
+VPROLDZmik 5236
+VPROLDZmikz 5237
+VPROLDZri 5238
+VPROLDZrik 5239
+VPROLDZrikz 5240
+VPROLQZ 5241
+VPROLQZmbi 5242
+VPROLQZmbik 5243
+VPROLQZmbikz 5244
+VPROLQZmi 5245
+VPROLQZmik 5246
+VPROLQZmikz 5247
+VPROLQZri 5248
+VPROLQZrik 5249
+VPROLQZrikz 5250
+VPROLVDZ 5251
+VPROLVDZrm 5252
+VPROLVDZrmb 5253
+VPROLVDZrmbk 5254
+VPROLVDZrmbkz 5255
+VPROLVDZrmk 5256
+VPROLVDZrmkz 5257
+VPROLVDZrr 5258
+VPROLVDZrrk 5259
+VPROLVDZrrkz 5260
+VPROLVQZ 5261
+VPROLVQZrm 5262
+VPROLVQZrmb 5263
+VPROLVQZrmbk 5264
+VPROLVQZrmbkz 5265
+VPROLVQZrmk 5266
+VPROLVQZrmkz 5267
+VPROLVQZrr 5268
+VPROLVQZrrk 5269
+VPROLVQZrrkz 5270
+VPRORDZ 5271
+VPRORDZmbi 5272
+VPRORDZmbik 5273
+VPRORDZmbikz 5274
+VPRORDZmi 5275
+VPRORDZmik 5276
+VPRORDZmikz 5277
+VPRORDZri 5278
+VPRORDZrik 5279
+VPRORDZrikz 5280
+VPRORQZ 5281
+VPRORQZmbi 5282
+VPRORQZmbik 5283
+VPRORQZmbikz 5284
+VPRORQZmi 5285
+VPRORQZmik 5286
+VPRORQZmikz 5287
+VPRORQZri 5288
+VPRORQZrik 5289
+VPRORQZrikz 5290
+VPRORVDZ 5291
+VPRORVDZrm 5292
+VPRORVDZrmb 5293
+VPRORVDZrmbk 5294
+VPRORVDZrmbkz 5295
+VPRORVDZrmk 5296
+VPRORVDZrmkz 5297
+VPRORVDZrr 5298
+VPRORVDZrrk 5299
+VPRORVDZrrkz 5300
+VPRORVQZ 5301
+VPRORVQZrm 5302
+VPRORVQZrmb 5303
+VPRORVQZrmbk 5304
+VPRORVQZrmbkz 5305
+VPRORVQZrmk 5306
+VPRORVQZrmkz 5307
+VPRORVQZrr 5308
+VPRORVQZrrk 5309
+VPRORVQZrrkz 5310
+VPROTBmi 5311
+VPROTBmr 5312
+VPROTBri 5313
+VPROTBrm 5314
+VPROTBrr 5315
+VPROTBrr_REV 5316
+VPROTDmi 5317
+VPROTDmr 5318
+VPROTDri 5319
+VPROTDrm 5320
+VPROTDrr 5321
+VPROTDrr_REV 5322
+VPROTQmi 5323
+VPROTQmr 5324
+VPROTQri 5325
+VPROTQrm 5326
+VPROTQrr 5327
+VPROTQrr_REV 5328
+VPROTWmi 5329
+VPROTWmr 5330
+VPROTWri 5331
+VPROTWrm 5332
+VPROTWrr 5333
+VPROTWrr_REV 5334
+VPSADBWYrm 5335
+VPSADBWYrr 5336
+VPSADBWZ 5337
+VPSADBWZrm 5338
+VPSADBWZrr 5339
+VPSADBWrm 5340
+VPSADBWrr 5341
+VPSCATTERDDZ 5342
+VPSCATTERDDZmr 5343
+VPSCATTERDQZ 5344
+VPSCATTERDQZmr 5345
+VPSCATTERQDZ 5346
+VPSCATTERQDZmr 5347
+VPSCATTERQQZ 5348
+VPSCATTERQQZmr 5349
+VPSHABmr 5350
+VPSHABrm 5351
+VPSHABrr 5352
+VPSHABrr_REV 5353
+VPSHADmr 5354
+VPSHADrm 5355
+VPSHADrr 5356
+VPSHADrr_REV 5357
+VPSHAQmr 5358
+VPSHAQrm 5359
+VPSHAQrr 5360
+VPSHAQrr_REV 5361
+VPSHAWmr 5362
+VPSHAWrm 5363
+VPSHAWrr 5364
+VPSHAWrr_REV 5365
+VPSHLBmr 5366
+VPSHLBrm 5367
+VPSHLBrr 5368
+VPSHLBrr_REV 5369
+VPSHLDDZ 5370
+VPSHLDDZrmbi 5371
+VPSHLDDZrmbik 5372
+VPSHLDDZrmbikz 5373
+VPSHLDDZrmi 5374
+VPSHLDDZrmik 5375
+VPSHLDDZrmikz 5376
+VPSHLDDZrri 5377
+VPSHLDDZrrik 5378
+VPSHLDDZrrikz 5379
+VPSHLDQZ 5380
+VPSHLDQZrmbi 5381
+VPSHLDQZrmbik 5382
+VPSHLDQZrmbikz 5383
+VPSHLDQZrmi 5384
+VPSHLDQZrmik 5385
+VPSHLDQZrmikz 5386
+VPSHLDQZrri 5387
+VPSHLDQZrrik 5388
+VPSHLDQZrrikz 5389
+VPSHLDVDZ 5390
+VPSHLDVDZm 5391
+VPSHLDVDZmb 5392
+VPSHLDVDZmbk 5393
+VPSHLDVDZmbkz 5394
+VPSHLDVDZmk 5395
+VPSHLDVDZmkz 5396
+VPSHLDVDZr 5397
+VPSHLDVDZrk 5398
+VPSHLDVDZrkz 5399
+VPSHLDVQZ 5400
+VPSHLDVQZm 5401
+VPSHLDVQZmb 5402
+VPSHLDVQZmbk 5403
+VPSHLDVQZmbkz 5404
+VPSHLDVQZmk 5405
+VPSHLDVQZmkz 5406
+VPSHLDVQZr 5407
+VPSHLDVQZrk 5408
+VPSHLDVQZrkz 5409
+VPSHLDVWZ 5410
+VPSHLDVWZm 5411
+VPSHLDVWZmk 5412
+VPSHLDVWZmkz 5413
+VPSHLDVWZr 5414
+VPSHLDVWZrk 5415
+VPSHLDVWZrkz 5416
+VPSHLDWZ 5417
+VPSHLDWZrmi 5418
+VPSHLDWZrmik 5419
+VPSHLDWZrmikz 5420
+VPSHLDWZrri 5421
+VPSHLDWZrrik 5422
+VPSHLDWZrrikz 5423
+VPSHLDmr 5424
+VPSHLDrm 5425
+VPSHLDrr 5426
+VPSHLDrr_REV 5427
+VPSHLQmr 5428
+VPSHLQrm 5429
+VPSHLQrr 5430
+VPSHLQrr_REV 5431
+VPSHLWmr 5432
+VPSHLWrm 5433
+VPSHLWrr 5434
+VPSHLWrr_REV 5435
+VPSHRDDZ 5436
+VPSHRDDZrmbi 5437
+VPSHRDDZrmbik 5438
+VPSHRDDZrmbikz 5439
+VPSHRDDZrmi 5440
+VPSHRDDZrmik 5441
+VPSHRDDZrmikz 5442
+VPSHRDDZrri 5443
+VPSHRDDZrrik 5444
+VPSHRDDZrrikz 5445
+VPSHRDQZ 5446
+VPSHRDQZrmbi 5447
+VPSHRDQZrmbik 5448
+VPSHRDQZrmbikz 5449
+VPSHRDQZrmi 5450
+VPSHRDQZrmik 5451
+VPSHRDQZrmikz 5452
+VPSHRDQZrri 5453
+VPSHRDQZrrik 5454
+VPSHRDQZrrikz 5455
+VPSHRDVDZ 5456
+VPSHRDVDZm 5457
+VPSHRDVDZmb 5458
+VPSHRDVDZmbk 5459
+VPSHRDVDZmbkz 5460
+VPSHRDVDZmk 5461
+VPSHRDVDZmkz 5462
+VPSHRDVDZr 5463
+VPSHRDVDZrk 5464
+VPSHRDVDZrkz 5465
+VPSHRDVQZ 5466
+VPSHRDVQZm 5467
+VPSHRDVQZmb 5468
+VPSHRDVQZmbk 5469
+VPSHRDVQZmbkz 5470
+VPSHRDVQZmk 5471
+VPSHRDVQZmkz 5472
+VPSHRDVQZr 5473
+VPSHRDVQZrk 5474
+VPSHRDVQZrkz 5475
+VPSHRDVWZ 5476
+VPSHRDVWZm 5477
+VPSHRDVWZmk 5478
+VPSHRDVWZmkz 5479
+VPSHRDVWZr 5480
+VPSHRDVWZrk 5481
+VPSHRDVWZrkz 5482
+VPSHRDWZ 5483
+VPSHRDWZrmi 5484
+VPSHRDWZrmik 5485
+VPSHRDWZrmikz 5486
+VPSHRDWZrri 5487
+VPSHRDWZrrik 5488
+VPSHRDWZrrikz 5489
+VPSHUFBITQMBZ 5490
+VPSHUFBITQMBZrm 5491
+VPSHUFBITQMBZrmk 5492
+VPSHUFBITQMBZrr 5493
+VPSHUFBITQMBZrrk 5494
+VPSHUFBYrm 5495
+VPSHUFBYrr 5496
+VPSHUFBZ 5497
+VPSHUFBZrm 5498
+VPSHUFBZrmk 5499
+VPSHUFBZrmkz 5500
+VPSHUFBZrr 5501
+VPSHUFBZrrk 5502
+VPSHUFBZrrkz 5503
+VPSHUFBrm 5504
+VPSHUFBrr 5505
+VPSHUFDYmi 5506
+VPSHUFDYri 5507
+VPSHUFDZ 5508
+VPSHUFDZmbi 5509
+VPSHUFDZmbik 5510
+VPSHUFDZmbikz 5511
+VPSHUFDZmi 5512
+VPSHUFDZmik 5513
+VPSHUFDZmikz 5514
+VPSHUFDZri 5515
+VPSHUFDZrik 5516
+VPSHUFDZrikz 5517
+VPSHUFDmi 5518
+VPSHUFDri 5519
+VPSHUFHWYmi 5520
+VPSHUFHWYri 5521
+VPSHUFHWZ 5522
+VPSHUFHWZmi 5523
+VPSHUFHWZmik 5524
+VPSHUFHWZmikz 5525
+VPSHUFHWZri 5526
+VPSHUFHWZrik 5527
+VPSHUFHWZrikz 5528
+VPSHUFHWmi 5529
+VPSHUFHWri 5530
+VPSHUFLWYmi 5531
+VPSHUFLWYri 5532
+VPSHUFLWZ 5533
+VPSHUFLWZmi 5534
+VPSHUFLWZmik 5535
+VPSHUFLWZmikz 5536
+VPSHUFLWZri 5537
+VPSHUFLWZrik 5538
+VPSHUFLWZrikz 5539
+VPSHUFLWmi 5540
+VPSHUFLWri 5541
+VPSIGNBYrm 5542
+VPSIGNBYrr 5543
+VPSIGNBrm 5544
+VPSIGNBrr 5545
+VPSIGNDYrm 5546
+VPSIGNDYrr 5547
+VPSIGNDrm 5548
+VPSIGNDrr 5549
+VPSIGNWYrm 5550
+VPSIGNWYrr 5551
+VPSIGNWrm 5552
+VPSIGNWrr 5553
+VPSLLDQYri 5554
+VPSLLDQZ 5555
+VPSLLDQZmi 5556
+VPSLLDQZri 5557
+VPSLLDQri 5558
+VPSLLDYri 5559
+VPSLLDYrm 5560
+VPSLLDYrr 5561
+VPSLLDZ 5562
+VPSLLDZmbi 5563
+VPSLLDZmbik 5564
+VPSLLDZmbikz 5565
+VPSLLDZmi 5566
+VPSLLDZmik 5567
+VPSLLDZmikz 5568
+VPSLLDZri 5569
+VPSLLDZrik 5570
+VPSLLDZrikz 5571
+VPSLLDZrm 5572
+VPSLLDZrmk 5573
+VPSLLDZrmkz 5574
+VPSLLDZrr 5575
+VPSLLDZrrk 5576
+VPSLLDZrrkz 5577
+VPSLLDri 5578
+VPSLLDrm 5579
+VPSLLDrr 5580
+VPSLLQYri 5581
+VPSLLQYrm 5582
+VPSLLQYrr 5583
+VPSLLQZ 5584
+VPSLLQZmbi 5585
+VPSLLQZmbik 5586
+VPSLLQZmbikz 5587
+VPSLLQZmi 5588
+VPSLLQZmik 5589
+VPSLLQZmikz 5590
+VPSLLQZri 5591
+VPSLLQZrik 5592
+VPSLLQZrikz 5593
+VPSLLQZrm 5594
+VPSLLQZrmk 5595
+VPSLLQZrmkz 5596
+VPSLLQZrr 5597
+VPSLLQZrrk 5598
+VPSLLQZrrkz 5599
+VPSLLQri 5600
+VPSLLQrm 5601
+VPSLLQrr 5602
+VPSLLVDYrm 5603
+VPSLLVDYrr 5604
+VPSLLVDZ 5605
+VPSLLVDZrm 5606
+VPSLLVDZrmb 5607
+VPSLLVDZrmbk 5608
+VPSLLVDZrmbkz 5609
+VPSLLVDZrmk 5610
+VPSLLVDZrmkz 5611
+VPSLLVDZrr 5612
+VPSLLVDZrrk 5613
+VPSLLVDZrrkz 5614
+VPSLLVDrm 5615
+VPSLLVDrr 5616
+VPSLLVQYrm 5617
+VPSLLVQYrr 5618
+VPSLLVQZ 5619
+VPSLLVQZrm 5620
+VPSLLVQZrmb 5621
+VPSLLVQZrmbk 5622
+VPSLLVQZrmbkz 5623
+VPSLLVQZrmk 5624
+VPSLLVQZrmkz 5625
+VPSLLVQZrr 5626
+VPSLLVQZrrk 5627
+VPSLLVQZrrkz 5628
+VPSLLVQrm 5629
+VPSLLVQrr 5630
+VPSLLVWZ 5631
+VPSLLVWZrm 5632
+VPSLLVWZrmk 5633
+VPSLLVWZrmkz 5634
+VPSLLVWZrr 5635
+VPSLLVWZrrk 5636
+VPSLLVWZrrkz 5637
+VPSLLWYri 5638
+VPSLLWYrm 5639
+VPSLLWYrr 5640
+VPSLLWZ 5641
+VPSLLWZmi 5642
+VPSLLWZmik 5643
+VPSLLWZmikz 5644
+VPSLLWZri 5645
+VPSLLWZrik 5646
+VPSLLWZrikz 5647
+VPSLLWZrm 5648
+VPSLLWZrmk 5649
+VPSLLWZrmkz 5650
+VPSLLWZrr 5651
+VPSLLWZrrk 5652
+VPSLLWZrrkz 5653
+VPSLLWri 5654
+VPSLLWrm 5655
+VPSLLWrr 5656
+VPSRADYri 5657
+VPSRADYrm 5658
+VPSRADYrr 5659
+VPSRADZ 5660
+VPSRADZmbi 5661
+VPSRADZmbik 5662
+VPSRADZmbikz 5663
+VPSRADZmi 5664
+VPSRADZmik 5665
+VPSRADZmikz 5666
+VPSRADZri 5667
+VPSRADZrik 5668
+VPSRADZrikz 5669
+VPSRADZrm 5670
+VPSRADZrmk 5671
+VPSRADZrmkz 5672
+VPSRADZrr 5673
+VPSRADZrrk 5674
+VPSRADZrrkz 5675
+VPSRADri 5676
+VPSRADrm 5677
+VPSRADrr 5678
+VPSRAQZ 5679
+VPSRAQZmbi 5680
+VPSRAQZmbik 5681
+VPSRAQZmbikz 5682
+VPSRAQZmi 5683
+VPSRAQZmik 5684
+VPSRAQZmikz 5685
+VPSRAQZri 5686
+VPSRAQZrik 5687
+VPSRAQZrikz 5688
+VPSRAQZrm 5689
+VPSRAQZrmk 5690
+VPSRAQZrmkz 5691
+VPSRAQZrr 5692
+VPSRAQZrrk 5693
+VPSRAQZrrkz 5694
+VPSRAVDYrm 5695
+VPSRAVDYrr 5696
+VPSRAVDZ 5697
+VPSRAVDZrm 5698
+VPSRAVDZrmb 5699
+VPSRAVDZrmbk 5700
+VPSRAVDZrmbkz 5701
+VPSRAVDZrmk 5702
+VPSRAVDZrmkz 5703
+VPSRAVDZrr 5704
+VPSRAVDZrrk 5705
+VPSRAVDZrrkz 5706
+VPSRAVDrm 5707
+VPSRAVDrr 5708
+VPSRAVQZ 5709
+VPSRAVQZrm 5710
+VPSRAVQZrmb 5711
+VPSRAVQZrmbk 5712
+VPSRAVQZrmbkz 5713
+VPSRAVQZrmk 5714
+VPSRAVQZrmkz 5715
+VPSRAVQZrr 5716
+VPSRAVQZrrk 5717
+VPSRAVQZrrkz 5718
+VPSRAVWZ 5719
+VPSRAVWZrm 5720
+VPSRAVWZrmk 5721
+VPSRAVWZrmkz 5722
+VPSRAVWZrr 5723
+VPSRAVWZrrk 5724
+VPSRAVWZrrkz 5725
+VPSRAWYri 5726
+VPSRAWYrm 5727
+VPSRAWYrr 5728
+VPSRAWZ 5729
+VPSRAWZmi 5730
+VPSRAWZmik 5731
+VPSRAWZmikz 5732
+VPSRAWZri 5733
+VPSRAWZrik 5734
+VPSRAWZrikz 5735
+VPSRAWZrm 5736
+VPSRAWZrmk 5737
+VPSRAWZrmkz 5738
+VPSRAWZrr 5739
+VPSRAWZrrk 5740
+VPSRAWZrrkz 5741
+VPSRAWri 5742
+VPSRAWrm 5743
+VPSRAWrr 5744
+VPSRLDQYri 5745
+VPSRLDQZ 5746
+VPSRLDQZmi 5747
+VPSRLDQZri 5748
+VPSRLDQri 5749
+VPSRLDYri 5750
+VPSRLDYrm 5751
+VPSRLDYrr 5752
+VPSRLDZ 5753
+VPSRLDZmbi 5754
+VPSRLDZmbik 5755
+VPSRLDZmbikz 5756
+VPSRLDZmi 5757
+VPSRLDZmik 5758
+VPSRLDZmikz 5759
+VPSRLDZri 5760
+VPSRLDZrik 5761
+VPSRLDZrikz 5762
+VPSRLDZrm 5763
+VPSRLDZrmk 5764
+VPSRLDZrmkz 5765
+VPSRLDZrr 5766
+VPSRLDZrrk 5767
+VPSRLDZrrkz 5768
+VPSRLDri 5769
+VPSRLDrm 5770
+VPSRLDrr 5771
+VPSRLQYri 5772
+VPSRLQYrm 5773
+VPSRLQYrr 5774
+VPSRLQZ 5775
+VPSRLQZmbi 5776
+VPSRLQZmbik 5777
+VPSRLQZmbikz 5778
+VPSRLQZmi 5779
+VPSRLQZmik 5780
+VPSRLQZmikz 5781
+VPSRLQZri 5782
+VPSRLQZrik 5783
+VPSRLQZrikz 5784
+VPSRLQZrm 5785
+VPSRLQZrmk 5786
+VPSRLQZrmkz 5787
+VPSRLQZrr 5788
+VPSRLQZrrk 5789
+VPSRLQZrrkz 5790
+VPSRLQri 5791
+VPSRLQrm 5792
+VPSRLQrr 5793
+VPSRLVDYrm 5794
+VPSRLVDYrr 5795
+VPSRLVDZ 5796
+VPSRLVDZrm 5797
+VPSRLVDZrmb 5798
+VPSRLVDZrmbk 5799
+VPSRLVDZrmbkz 5800
+VPSRLVDZrmk 5801
+VPSRLVDZrmkz 5802
+VPSRLVDZrr 5803
+VPSRLVDZrrk 5804
+VPSRLVDZrrkz 5805
+VPSRLVDrm 5806
+VPSRLVDrr 5807
+VPSRLVQYrm 5808
+VPSRLVQYrr 5809
+VPSRLVQZ 5810
+VPSRLVQZrm 5811
+VPSRLVQZrmb 5812
+VPSRLVQZrmbk 5813
+VPSRLVQZrmbkz 5814
+VPSRLVQZrmk 5815
+VPSRLVQZrmkz 5816
+VPSRLVQZrr 5817
+VPSRLVQZrrk 5818
+VPSRLVQZrrkz 5819
+VPSRLVQrm 5820
+VPSRLVQrr 5821
+VPSRLVWZ 5822
+VPSRLVWZrm 5823
+VPSRLVWZrmk 5824
+VPSRLVWZrmkz 5825
+VPSRLVWZrr 5826
+VPSRLVWZrrk 5827
+VPSRLVWZrrkz 5828
+VPSRLWYri 5829
+VPSRLWYrm 5830
+VPSRLWYrr 5831
+VPSRLWZ 5832
+VPSRLWZmi 5833
+VPSRLWZmik 5834
+VPSRLWZmikz 5835
+VPSRLWZri 5836
+VPSRLWZrik 5837
+VPSRLWZrikz 5838
+VPSRLWZrm 5839
+VPSRLWZrmk 5840
+VPSRLWZrmkz 5841
+VPSRLWZrr 5842
+VPSRLWZrrk 5843
+VPSRLWZrrkz 5844
+VPSRLWri 5845
+VPSRLWrm 5846
+VPSRLWrr 5847
+VPSUBBYrm 5848
+VPSUBBYrr 5849
+VPSUBBZ 5850
+VPSUBBZrm 5851
+VPSUBBZrmk 5852
+VPSUBBZrmkz 5853
+VPSUBBZrr 5854
+VPSUBBZrrk 5855
+VPSUBBZrrkz 5856
+VPSUBBrm 5857
+VPSUBBrr 5858
+VPSUBDYrm 5859
+VPSUBDYrr 5860
+VPSUBDZ 5861
+VPSUBDZrm 5862
+VPSUBDZrmb 5863
+VPSUBDZrmbk 5864
+VPSUBDZrmbkz 5865
+VPSUBDZrmk 5866
+VPSUBDZrmkz 5867
+VPSUBDZrr 5868
+VPSUBDZrrk 5869
+VPSUBDZrrkz 5870
+VPSUBDrm 5871
+VPSUBDrr 5872
+VPSUBQYrm 5873
+VPSUBQYrr 5874
+VPSUBQZ 5875
+VPSUBQZrm 5876
+VPSUBQZrmb 5877
+VPSUBQZrmbk 5878
+VPSUBQZrmbkz 5879
+VPSUBQZrmk 5880
+VPSUBQZrmkz 5881
+VPSUBQZrr 5882
+VPSUBQZrrk 5883
+VPSUBQZrrkz 5884
+VPSUBQrm 5885
+VPSUBQrr 5886
+VPSUBSBYrm 5887
+VPSUBSBYrr 5888
+VPSUBSBZ 5889
+VPSUBSBZrm 5890
+VPSUBSBZrmk 5891
+VPSUBSBZrmkz 5892
+VPSUBSBZrr 5893
+VPSUBSBZrrk 5894
+VPSUBSBZrrkz 5895
+VPSUBSBrm 5896
+VPSUBSBrr 5897
+VPSUBSWYrm 5898
+VPSUBSWYrr 5899
+VPSUBSWZ 5900
+VPSUBSWZrm 5901
+VPSUBSWZrmk 5902
+VPSUBSWZrmkz 5903
+VPSUBSWZrr 5904
+VPSUBSWZrrk 5905
+VPSUBSWZrrkz 5906
+VPSUBSWrm 5907
+VPSUBSWrr 5908
+VPSUBUSBYrm 5909
+VPSUBUSBYrr 5910
+VPSUBUSBZ 5911
+VPSUBUSBZrm 5912
+VPSUBUSBZrmk 5913
+VPSUBUSBZrmkz 5914
+VPSUBUSBZrr 5915
+VPSUBUSBZrrk 5916
+VPSUBUSBZrrkz 5917
+VPSUBUSBrm 5918
+VPSUBUSBrr 5919
+VPSUBUSWYrm 5920
+VPSUBUSWYrr 5921
+VPSUBUSWZ 5922
+VPSUBUSWZrm 5923
+VPSUBUSWZrmk 5924
+VPSUBUSWZrmkz 5925
+VPSUBUSWZrr 5926
+VPSUBUSWZrrk 5927
+VPSUBUSWZrrkz 5928
+VPSUBUSWrm 5929
+VPSUBUSWrr 5930
+VPSUBWYrm 5931
+VPSUBWYrr 5932
+VPSUBWZ 5933
+VPSUBWZrm 5934
+VPSUBWZrmk 5935
+VPSUBWZrmkz 5936
+VPSUBWZrr 5937
+VPSUBWZrrk 5938
+VPSUBWZrrkz 5939
+VPSUBWrm 5940
+VPSUBWrr 5941
+VPTERNLOGDZ 5942
+VPTERNLOGDZrmbi 5943
+VPTERNLOGDZrmbik 5944
+VPTERNLOGDZrmbikz 5945
+VPTERNLOGDZrmi 5946
+VPTERNLOGDZrmik 5947
+VPTERNLOGDZrmikz 5948
+VPTERNLOGDZrri 5949
+VPTERNLOGDZrrik 5950
+VPTERNLOGDZrrikz 5951
+VPTERNLOGQZ 5952
+VPTERNLOGQZrmbi 5953
+VPTERNLOGQZrmbik 5954
+VPTERNLOGQZrmbikz 5955
+VPTERNLOGQZrmi 5956
+VPTERNLOGQZrmik 5957
+VPTERNLOGQZrmikz 5958
+VPTERNLOGQZrri 5959
+VPTERNLOGQZrrik 5960
+VPTERNLOGQZrrikz 5961
+VPTESTMBZ 5962
+VPTESTMBZrm 5963
+VPTESTMBZrmk 5964
+VPTESTMBZrr 5965
+VPTESTMBZrrk 5966
+VPTESTMDZ 5967
+VPTESTMDZrm 5968
+VPTESTMDZrmb 5969
+VPTESTMDZrmbk 5970
+VPTESTMDZrmk 5971
+VPTESTMDZrr 5972
+VPTESTMDZrrk 5973
+VPTESTMQZ 5974
+VPTESTMQZrm 5975
+VPTESTMQZrmb 5976
+VPTESTMQZrmbk 5977
+VPTESTMQZrmk 5978
+VPTESTMQZrr 5979
+VPTESTMQZrrk 5980
+VPTESTMWZ 5981
+VPTESTMWZrm 5982
+VPTESTMWZrmk 5983
+VPTESTMWZrr 5984
+VPTESTMWZrrk 5985
+VPTESTNMBZ 5986
+VPTESTNMBZrm 5987
+VPTESTNMBZrmk 5988
+VPTESTNMBZrr 5989
+VPTESTNMBZrrk 5990
+VPTESTNMDZ 5991
+VPTESTNMDZrm 5992
+VPTESTNMDZrmb 5993
+VPTESTNMDZrmbk 5994
+VPTESTNMDZrmk 5995
+VPTESTNMDZrr 5996
+VPTESTNMDZrrk 5997
+VPTESTNMQZ 5998
+VPTESTNMQZrm 5999
+VPTESTNMQZrmb 6000
+VPTESTNMQZrmbk 6001
+VPTESTNMQZrmk 6002
+VPTESTNMQZrr 6003
+VPTESTNMQZrrk 6004
+VPTESTNMWZ 6005
+VPTESTNMWZrm 6006
+VPTESTNMWZrmk 6007
+VPTESTNMWZrr 6008
+VPTESTNMWZrrk 6009
+VPTESTYrm 6010
+VPTESTYrr 6011
+VPTESTrm 6012
+VPTESTrr 6013
+VPUNPCKHBWYrm 6014
+VPUNPCKHBWYrr 6015
+VPUNPCKHBWZ 6016
+VPUNPCKHBWZrm 6017
+VPUNPCKHBWZrmk 6018
+VPUNPCKHBWZrmkz 6019
+VPUNPCKHBWZrr 6020
+VPUNPCKHBWZrrk 6021
+VPUNPCKHBWZrrkz 6022
+VPUNPCKHBWrm 6023
+VPUNPCKHBWrr 6024
+VPUNPCKHDQYrm 6025
+VPUNPCKHDQYrr 6026
+VPUNPCKHDQZ 6027
+VPUNPCKHDQZrm 6028
+VPUNPCKHDQZrmb 6029
+VPUNPCKHDQZrmbk 6030
+VPUNPCKHDQZrmbkz 6031
+VPUNPCKHDQZrmk 6032
+VPUNPCKHDQZrmkz 6033
+VPUNPCKHDQZrr 6034
+VPUNPCKHDQZrrk 6035
+VPUNPCKHDQZrrkz 6036
+VPUNPCKHDQrm 6037
+VPUNPCKHDQrr 6038
+VPUNPCKHQDQYrm 6039
+VPUNPCKHQDQYrr 6040
+VPUNPCKHQDQZ 6041
+VPUNPCKHQDQZrm 6042
+VPUNPCKHQDQZrmb 6043
+VPUNPCKHQDQZrmbk 6044
+VPUNPCKHQDQZrmbkz 6045
+VPUNPCKHQDQZrmk 6046
+VPUNPCKHQDQZrmkz 6047
+VPUNPCKHQDQZrr 6048
+VPUNPCKHQDQZrrk 6049
+VPUNPCKHQDQZrrkz 6050
+VPUNPCKHQDQrm 6051
+VPUNPCKHQDQrr 6052
+VPUNPCKHWDYrm 6053
+VPUNPCKHWDYrr 6054
+VPUNPCKHWDZ 6055
+VPUNPCKHWDZrm 6056
+VPUNPCKHWDZrmk 6057
+VPUNPCKHWDZrmkz 6058
+VPUNPCKHWDZrr 6059
+VPUNPCKHWDZrrk 6060
+VPUNPCKHWDZrrkz 6061
+VPUNPCKHWDrm 6062
+VPUNPCKHWDrr 6063
+VPUNPCKLBWYrm 6064
+VPUNPCKLBWYrr 6065
+VPUNPCKLBWZ 6066
+VPUNPCKLBWZrm 6067
+VPUNPCKLBWZrmk 6068
+VPUNPCKLBWZrmkz 6069
+VPUNPCKLBWZrr 6070
+VPUNPCKLBWZrrk 6071
+VPUNPCKLBWZrrkz 6072
+VPUNPCKLBWrm 6073
+VPUNPCKLBWrr 6074
+VPUNPCKLDQYrm 6075
+VPUNPCKLDQYrr 6076
+VPUNPCKLDQZ 6077
+VPUNPCKLDQZrm 6078
+VPUNPCKLDQZrmb 6079
+VPUNPCKLDQZrmbk 6080
+VPUNPCKLDQZrmbkz 6081
+VPUNPCKLDQZrmk 6082
+VPUNPCKLDQZrmkz 6083
+VPUNPCKLDQZrr 6084
+VPUNPCKLDQZrrk 6085
+VPUNPCKLDQZrrkz 6086
+VPUNPCKLDQrm 6087
+VPUNPCKLDQrr 6088
+VPUNPCKLQDQYrm 6089
+VPUNPCKLQDQYrr 6090
+VPUNPCKLQDQZ 6091
+VPUNPCKLQDQZrm 6092
+VPUNPCKLQDQZrmb 6093
+VPUNPCKLQDQZrmbk 6094
+VPUNPCKLQDQZrmbkz 6095
+VPUNPCKLQDQZrmk 6096
+VPUNPCKLQDQZrmkz 6097
+VPUNPCKLQDQZrr 6098
+VPUNPCKLQDQZrrk 6099
+VPUNPCKLQDQZrrkz 6100
+VPUNPCKLQDQrm 6101
+VPUNPCKLQDQrr 6102
+VPUNPCKLWDYrm 6103
+VPUNPCKLWDYrr 6104
+VPUNPCKLWDZ 6105
+VPUNPCKLWDZrm 6106
+VPUNPCKLWDZrmk 6107
+VPUNPCKLWDZrmkz 6108
+VPUNPCKLWDZrr 6109
+VPUNPCKLWDZrrk 6110
+VPUNPCKLWDZrrkz 6111
+VPUNPCKLWDrm 6112
+VPUNPCKLWDrr 6113
+VPXORDZ 6114
+VPXORDZrm 6115
+VPXORDZrmb 6116
+VPXORDZrmbk 6117
+VPXORDZrmbkz 6118
+VPXORDZrmk 6119
+VPXORDZrmkz 6120
+VPXORDZrr 6121
+VPXORDZrrk 6122
+VPXORDZrrkz 6123
+VPXORQZ 6124
+VPXORQZrm 6125
+VPXORQZrmb 6126
+VPXORQZrmbk 6127
+VPXORQZrmbkz 6128
+VPXORQZrmk 6129
+VPXORQZrmkz 6130
+VPXORQZrr 6131
+VPXORQZrrk 6132
+VPXORQZrrkz 6133
+VPXORYrm 6134
+VPXORYrr 6135
+VPXORrm 6136
+VPXORrr 6137
+VRANGEPDZ 6138
+VRANGEPDZrmbi 6139
+VRANGEPDZrmbik 6140
+VRANGEPDZrmbikz 6141
+VRANGEPDZrmi 6142
+VRANGEPDZrmik 6143
+VRANGEPDZrmikz 6144
+VRANGEPDZrri 6145
+VRANGEPDZrrib 6146
+VRANGEPDZrribk 6147
+VRANGEPDZrribkz 6148
+VRANGEPDZrrik 6149
+VRANGEPDZrrikz 6150
+VRANGEPSZ 6151
+VRANGEPSZrmbi 6152
+VRANGEPSZrmbik 6153
+VRANGEPSZrmbikz 6154
+VRANGEPSZrmi 6155
+VRANGEPSZrmik 6156
+VRANGEPSZrmikz 6157
+VRANGEPSZrri 6158
+VRANGEPSZrrib 6159
+VRANGEPSZrribk 6160
+VRANGEPSZrribkz 6161
+VRANGEPSZrrik 6162
+VRANGEPSZrrikz 6163
+VRANGESDZrmi 6164
+VRANGESDZrmik 6165
+VRANGESDZrmikz 6166
+VRANGESDZrri 6167
+VRANGESDZrrib 6168
+VRANGESDZrribk 6169
+VRANGESDZrribkz 6170
+VRANGESDZrrik 6171
+VRANGESDZrrikz 6172
+VRANGESSZrmi 6173
+VRANGESSZrmik 6174
+VRANGESSZrmikz 6175
+VRANGESSZrri 6176
+VRANGESSZrrib 6177
+VRANGESSZrribk 6178
+VRANGESSZrribkz 6179
+VRANGESSZrrik 6180
+VRANGESSZrrikz 6181
+VRCP 6182
+VRCPBF 6183
+VRCPPHZ 6184
+VRCPPHZm 6185
+VRCPPHZmb 6186
+VRCPPHZmbk 6187
+VRCPPHZmbkz 6188
+VRCPPHZmk 6189
+VRCPPHZmkz 6190
+VRCPPHZr 6191
+VRCPPHZrk 6192
+VRCPPHZrkz 6193
+VRCPPSYm 6194
+VRCPPSYr 6195
+VRCPPSm 6196
+VRCPPSr 6197
+VRCPSHZrm 6198
+VRCPSHZrmk 6199
+VRCPSHZrmkz 6200
+VRCPSHZrr 6201
+VRCPSHZrrk 6202
+VRCPSHZrrkz 6203
+VRCPSSm 6204
+VRCPSSm_Int 6205
+VRCPSSr 6206
+VRCPSSr_Int 6207
+VREDUCEBF 6208
+VREDUCEPDZ 6209
+VREDUCEPDZrmbi 6210
+VREDUCEPDZrmbik 6211
+VREDUCEPDZrmbikz 6212
+VREDUCEPDZrmi 6213
+VREDUCEPDZrmik 6214
+VREDUCEPDZrmikz 6215
+VREDUCEPDZrri 6216
+VREDUCEPDZrrib 6217
+VREDUCEPDZrribk 6218
+VREDUCEPDZrribkz 6219
+VREDUCEPDZrrik 6220
+VREDUCEPDZrrikz 6221
+VREDUCEPHZ 6222
+VREDUCEPHZrmbi 6223
+VREDUCEPHZrmbik 6224
+VREDUCEPHZrmbikz 6225
+VREDUCEPHZrmi 6226
+VREDUCEPHZrmik 6227
+VREDUCEPHZrmikz 6228
+VREDUCEPHZrri 6229
+VREDUCEPHZrrib 6230
+VREDUCEPHZrribk 6231
+VREDUCEPHZrribkz 6232
+VREDUCEPHZrrik 6233
+VREDUCEPHZrrikz 6234
+VREDUCEPSZ 6235
+VREDUCEPSZrmbi 6236
+VREDUCEPSZrmbik 6237
+VREDUCEPSZrmbikz 6238
+VREDUCEPSZrmi 6239
+VREDUCEPSZrmik 6240
+VREDUCEPSZrmikz 6241
+VREDUCEPSZrri 6242
+VREDUCEPSZrrib 6243
+VREDUCEPSZrribk 6244
+VREDUCEPSZrribkz 6245
+VREDUCEPSZrrik 6246
+VREDUCEPSZrrikz 6247
+VREDUCESDZrmi 6248
+VREDUCESDZrmik 6249
+VREDUCESDZrmikz 6250
+VREDUCESDZrri 6251
+VREDUCESDZrrib 6252
+VREDUCESDZrribk 6253
+VREDUCESDZrribkz 6254
+VREDUCESDZrrik 6255
+VREDUCESDZrrikz 6256
+VREDUCESHZrmi 6257
+VREDUCESHZrmik 6258
+VREDUCESHZrmikz 6259
+VREDUCESHZrri 6260
+VREDUCESHZrrib 6261
+VREDUCESHZrribk 6262
+VREDUCESHZrribkz 6263
+VREDUCESHZrrik 6264
+VREDUCESHZrrikz 6265
+VREDUCESSZrmi 6266
+VREDUCESSZrmik 6267
+VREDUCESSZrmikz 6268
+VREDUCESSZrri 6269
+VREDUCESSZrrib 6270
+VREDUCESSZrribk 6271
+VREDUCESSZrribkz 6272
+VREDUCESSZrrik 6273
+VREDUCESSZrrikz 6274
+VRNDSCALEBF 6275
+VRNDSCALEPDZ 6276
+VRNDSCALEPDZrmbi 6277
+VRNDSCALEPDZrmbik 6278
+VRNDSCALEPDZrmbikz 6279
+VRNDSCALEPDZrmi 6280
+VRNDSCALEPDZrmik 6281
+VRNDSCALEPDZrmikz 6282
+VRNDSCALEPDZrri 6283
+VRNDSCALEPDZrrib 6284
+VRNDSCALEPDZrribk 6285
+VRNDSCALEPDZrribkz 6286
+VRNDSCALEPDZrrik 6287
+VRNDSCALEPDZrrikz 6288
+VRNDSCALEPHZ 6289
+VRNDSCALEPHZrmbi 6290
+VRNDSCALEPHZrmbik 6291
+VRNDSCALEPHZrmbikz 6292
+VRNDSCALEPHZrmi 6293
+VRNDSCALEPHZrmik 6294
+VRNDSCALEPHZrmikz 6295
+VRNDSCALEPHZrri 6296
+VRNDSCALEPHZrrib 6297
+VRNDSCALEPHZrribk 6298
+VRNDSCALEPHZrribkz 6299
+VRNDSCALEPHZrrik 6300
+VRNDSCALEPHZrrikz 6301
+VRNDSCALEPSZ 6302
+VRNDSCALEPSZrmbi 6303
+VRNDSCALEPSZrmbik 6304
+VRNDSCALEPSZrmbikz 6305
+VRNDSCALEPSZrmi 6306
+VRNDSCALEPSZrmik 6307
+VRNDSCALEPSZrmikz 6308
+VRNDSCALEPSZrri 6309
+VRNDSCALEPSZrrib 6310
+VRNDSCALEPSZrribk 6311
+VRNDSCALEPSZrribkz 6312
+VRNDSCALEPSZrrik 6313
+VRNDSCALEPSZrrikz 6314
+VRNDSCALESDZrmi 6315
+VRNDSCALESDZrmi_Int 6316
+VRNDSCALESDZrmik_Int 6317
+VRNDSCALESDZrmikz_Int 6318
+VRNDSCALESDZrri 6319
+VRNDSCALESDZrri_Int 6320
+VRNDSCALESDZrrib_Int 6321
+VRNDSCALESDZrribk_Int 6322
+VRNDSCALESDZrribkz_Int 6323
+VRNDSCALESDZrrik_Int 6324
+VRNDSCALESDZrrikz_Int 6325
+VRNDSCALESHZrmi 6326
+VRNDSCALESHZrmi_Int 6327
+VRNDSCALESHZrmik_Int 6328
+VRNDSCALESHZrmikz_Int 6329
+VRNDSCALESHZrri 6330
+VRNDSCALESHZrri_Int 6331
+VRNDSCALESHZrrib_Int 6332
+VRNDSCALESHZrribk_Int 6333
+VRNDSCALESHZrribkz_Int 6334
+VRNDSCALESHZrrik_Int 6335
+VRNDSCALESHZrrikz_Int 6336
+VRNDSCALESSZrmi 6337
+VRNDSCALESSZrmi_Int 6338
+VRNDSCALESSZrmik_Int 6339
+VRNDSCALESSZrmikz_Int 6340
+VRNDSCALESSZrri 6341
+VRNDSCALESSZrri_Int 6342
+VRNDSCALESSZrrib_Int 6343
+VRNDSCALESSZrribk_Int 6344
+VRNDSCALESSZrribkz_Int 6345
+VRNDSCALESSZrrik_Int 6346
+VRNDSCALESSZrrikz_Int 6347
+VROUNDPDYmi 6348
+VROUNDPDYri 6349
+VROUNDPDmi 6350
+VROUNDPDri 6351
+VROUNDPSYmi 6352
+VROUNDPSYri 6353
+VROUNDPSmi 6354
+VROUNDPSri 6355
+VROUNDSDmi 6356
+VROUNDSDmi_Int 6357
+VROUNDSDri 6358
+VROUNDSDri_Int 6359
+VROUNDSSmi 6360
+VROUNDSSmi_Int 6361
+VROUNDSSri 6362
+VROUNDSSri_Int 6363
+VRSQRT 6364
+VRSQRTBF 6365
+VRSQRTPHZ 6366
+VRSQRTPHZm 6367
+VRSQRTPHZmb 6368
+VRSQRTPHZmbk 6369
+VRSQRTPHZmbkz 6370
+VRSQRTPHZmk 6371
+VRSQRTPHZmkz 6372
+VRSQRTPHZr 6373
+VRSQRTPHZrk 6374
+VRSQRTPHZrkz 6375
+VRSQRTPSYm 6376
+VRSQRTPSYr 6377
+VRSQRTPSm 6378
+VRSQRTPSr 6379
+VRSQRTSHZrm 6380
+VRSQRTSHZrmk 6381
+VRSQRTSHZrmkz 6382
+VRSQRTSHZrr 6383
+VRSQRTSHZrrk 6384
+VRSQRTSHZrrkz 6385
+VRSQRTSSm 6386
+VRSQRTSSm_Int 6387
+VRSQRTSSr 6388
+VRSQRTSSr_Int 6389
+VSCALEFBF 6390
+VSCALEFPDZ 6391
+VSCALEFPDZrm 6392
+VSCALEFPDZrmb 6393
+VSCALEFPDZrmbk 6394
+VSCALEFPDZrmbkz 6395
+VSCALEFPDZrmk 6396
+VSCALEFPDZrmkz 6397
+VSCALEFPDZrr 6398
+VSCALEFPDZrrb 6399
+VSCALEFPDZrrbk 6400
+VSCALEFPDZrrbkz 6401
+VSCALEFPDZrrk 6402
+VSCALEFPDZrrkz 6403
+VSCALEFPHZ 6404
+VSCALEFPHZrm 6405
+VSCALEFPHZrmb 6406
+VSCALEFPHZrmbk 6407
+VSCALEFPHZrmbkz 6408
+VSCALEFPHZrmk 6409
+VSCALEFPHZrmkz 6410
+VSCALEFPHZrr 6411
+VSCALEFPHZrrb 6412
+VSCALEFPHZrrbk 6413
+VSCALEFPHZrrbkz 6414
+VSCALEFPHZrrk 6415
+VSCALEFPHZrrkz 6416
+VSCALEFPSZ 6417
+VSCALEFPSZrm 6418
+VSCALEFPSZrmb 6419
+VSCALEFPSZrmbk 6420
+VSCALEFPSZrmbkz 6421
+VSCALEFPSZrmk 6422
+VSCALEFPSZrmkz 6423
+VSCALEFPSZrr 6424
+VSCALEFPSZrrb 6425
+VSCALEFPSZrrbk 6426
+VSCALEFPSZrrbkz 6427
+VSCALEFPSZrrk 6428
+VSCALEFPSZrrkz 6429
+VSCALEFSDZrm 6430
+VSCALEFSDZrmk 6431
+VSCALEFSDZrmkz 6432
+VSCALEFSDZrr 6433
+VSCALEFSDZrrb_Int 6434
+VSCALEFSDZrrbk_Int 6435
+VSCALEFSDZrrbkz_Int 6436
+VSCALEFSDZrrk 6437
+VSCALEFSDZrrkz 6438
+VSCALEFSHZrm 6439
+VSCALEFSHZrmk 6440
+VSCALEFSHZrmkz 6441
+VSCALEFSHZrr 6442
+VSCALEFSHZrrb_Int 6443
+VSCALEFSHZrrbk_Int 6444
+VSCALEFSHZrrbkz_Int 6445
+VSCALEFSHZrrk 6446
+VSCALEFSHZrrkz 6447
+VSCALEFSSZrm 6448
+VSCALEFSSZrmk 6449
+VSCALEFSSZrmkz 6450
+VSCALEFSSZrr 6451
+VSCALEFSSZrrb_Int 6452
+VSCALEFSSZrrbk_Int 6453
+VSCALEFSSZrrbkz_Int 6454
+VSCALEFSSZrrk 6455
+VSCALEFSSZrrkz 6456
+VSCATTERDPDZ 6457
+VSCATTERDPDZmr 6458
+VSCATTERDPSZ 6459
+VSCATTERDPSZmr 6460
+VSCATTERPF 6461
+VSCATTERQPDZ 6462
+VSCATTERQPDZmr 6463
+VSCATTERQPSZ 6464
+VSCATTERQPSZmr 6465
+VSHA 6466
+VSHUFF 6467
+VSHUFI 6468
+VSHUFPDYrmi 6469
+VSHUFPDYrri 6470
+VSHUFPDZ 6471
+VSHUFPDZrmbi 6472
+VSHUFPDZrmbik 6473
+VSHUFPDZrmbikz 6474
+VSHUFPDZrmi 6475
+VSHUFPDZrmik 6476
+VSHUFPDZrmikz 6477
+VSHUFPDZrri 6478
+VSHUFPDZrrik 6479
+VSHUFPDZrrikz 6480
+VSHUFPDrmi 6481
+VSHUFPDrri 6482
+VSHUFPSYrmi 6483
+VSHUFPSYrri 6484
+VSHUFPSZ 6485
+VSHUFPSZrmbi 6486
+VSHUFPSZrmbik 6487
+VSHUFPSZrmbikz 6488
+VSHUFPSZrmi 6489
+VSHUFPSZrmik 6490
+VSHUFPSZrmikz 6491
+VSHUFPSZrri 6492
+VSHUFPSZrrik 6493
+VSHUFPSZrrikz 6494
+VSHUFPSrmi 6495
+VSHUFPSrri 6496
+VSM 6497
+VSQRTBF 6498
+VSQRTPDYm 6499
+VSQRTPDYr 6500
+VSQRTPDZ 6501
+VSQRTPDZm 6502
+VSQRTPDZmb 6503
+VSQRTPDZmbk 6504
+VSQRTPDZmbkz 6505
+VSQRTPDZmk 6506
+VSQRTPDZmkz 6507
+VSQRTPDZr 6508
+VSQRTPDZrb 6509
+VSQRTPDZrbk 6510
+VSQRTPDZrbkz 6511
+VSQRTPDZrk 6512
+VSQRTPDZrkz 6513
+VSQRTPDm 6514
+VSQRTPDr 6515
+VSQRTPHZ 6516
+VSQRTPHZm 6517
+VSQRTPHZmb 6518
+VSQRTPHZmbk 6519
+VSQRTPHZmbkz 6520
+VSQRTPHZmk 6521
+VSQRTPHZmkz 6522
+VSQRTPHZr 6523
+VSQRTPHZrb 6524
+VSQRTPHZrbk 6525
+VSQRTPHZrbkz 6526
+VSQRTPHZrk 6527
+VSQRTPHZrkz 6528
+VSQRTPSYm 6529
+VSQRTPSYr 6530
+VSQRTPSZ 6531
+VSQRTPSZm 6532
+VSQRTPSZmb 6533
+VSQRTPSZmbk 6534
+VSQRTPSZmbkz 6535
+VSQRTPSZmk 6536
+VSQRTPSZmkz 6537
+VSQRTPSZr 6538
+VSQRTPSZrb 6539
+VSQRTPSZrbk 6540
+VSQRTPSZrbkz 6541
+VSQRTPSZrk 6542
+VSQRTPSZrkz 6543
+VSQRTPSm 6544
+VSQRTPSr 6545
+VSQRTSDZm 6546
+VSQRTSDZm_Int 6547
+VSQRTSDZmk_Int 6548
+VSQRTSDZmkz_Int 6549
+VSQRTSDZr 6550
+VSQRTSDZr_Int 6551
+VSQRTSDZrb_Int 6552
+VSQRTSDZrbk_Int 6553
+VSQRTSDZrbkz_Int 6554
+VSQRTSDZrk_Int 6555
+VSQRTSDZrkz_Int 6556
+VSQRTSDm 6557
+VSQRTSDm_Int 6558
+VSQRTSDr 6559
+VSQRTSDr_Int 6560
+VSQRTSHZm 6561
+VSQRTSHZm_Int 6562
+VSQRTSHZmk_Int 6563
+VSQRTSHZmkz_Int 6564
+VSQRTSHZr 6565
+VSQRTSHZr_Int 6566
+VSQRTSHZrb_Int 6567
+VSQRTSHZrbk_Int 6568
+VSQRTSHZrbkz_Int 6569
+VSQRTSHZrk_Int 6570
+VSQRTSHZrkz_Int 6571
+VSQRTSSZm 6572
+VSQRTSSZm_Int 6573
+VSQRTSSZmk_Int 6574
+VSQRTSSZmkz_Int 6575
+VSQRTSSZr 6576
+VSQRTSSZr_Int 6577
+VSQRTSSZrb_Int 6578
+VSQRTSSZrbk_Int 6579
+VSQRTSSZrbkz_Int 6580
+VSQRTSSZrk_Int 6581
+VSQRTSSZrkz_Int 6582
+VSQRTSSm 6583
+VSQRTSSm_Int 6584
+VSQRTSSr 6585
+VSQRTSSr_Int 6586
+VSTMXCSR 6587
+VSUBBF 6588
+VSUBPDYrm 6589
+VSUBPDYrr 6590
+VSUBPDZ 6591
+VSUBPDZrm 6592
+VSUBPDZrmb 6593
+VSUBPDZrmbk 6594
+VSUBPDZrmbkz 6595
+VSUBPDZrmk 6596
+VSUBPDZrmkz 6597
+VSUBPDZrr 6598
+VSUBPDZrrb 6599
+VSUBPDZrrbk 6600
+VSUBPDZrrbkz 6601
+VSUBPDZrrk 6602
+VSUBPDZrrkz 6603
+VSUBPDrm 6604
+VSUBPDrr 6605
+VSUBPHZ 6606
+VSUBPHZrm 6607
+VSUBPHZrmb 6608
+VSUBPHZrmbk 6609
+VSUBPHZrmbkz 6610
+VSUBPHZrmk 6611
+VSUBPHZrmkz 6612
+VSUBPHZrr 6613
+VSUBPHZrrb 6614
+VSUBPHZrrbk 6615
+VSUBPHZrrbkz 6616
+VSUBPHZrrk 6617
+VSUBPHZrrkz 6618
+VSUBPSYrm 6619
+VSUBPSYrr 6620
+VSUBPSZ 6621
+VSUBPSZrm 6622
+VSUBPSZrmb 6623
+VSUBPSZrmbk 6624
+VSUBPSZrmbkz 6625
+VSUBPSZrmk 6626
+VSUBPSZrmkz 6627
+VSUBPSZrr 6628
+VSUBPSZrrb 6629
+VSUBPSZrrbk 6630
+VSUBPSZrrbkz 6631
+VSUBPSZrrk 6632
+VSUBPSZrrkz 6633
+VSUBPSrm 6634
+VSUBPSrr 6635
+VSUBSDZrm 6636
+VSUBSDZrm_Int 6637
+VSUBSDZrmk_Int 6638
+VSUBSDZrmkz_Int 6639
+VSUBSDZrr 6640
+VSUBSDZrr_Int 6641
+VSUBSDZrrb_Int 6642
+VSUBSDZrrbk_Int 6643
+VSUBSDZrrbkz_Int 6644
+VSUBSDZrrk_Int 6645
+VSUBSDZrrkz_Int 6646
+VSUBSDrm 6647
+VSUBSDrm_Int 6648
+VSUBSDrr 6649
+VSUBSDrr_Int 6650
+VSUBSHZrm 6651
+VSUBSHZrm_Int 6652
+VSUBSHZrmk_Int 6653
+VSUBSHZrmkz_Int 6654
+VSUBSHZrr 6655
+VSUBSHZrr_Int 6656
+VSUBSHZrrb_Int 6657
+VSUBSHZrrbk_Int 6658
+VSUBSHZrrbkz_Int 6659
+VSUBSHZrrk_Int 6660
+VSUBSHZrrkz_Int 6661
+VSUBSSZrm 6662
+VSUBSSZrm_Int 6663
+VSUBSSZrmk_Int 6664
+VSUBSSZrmkz_Int 6665
+VSUBSSZrr 6666
+VSUBSSZrr_Int 6667
+VSUBSSZrrb_Int 6668
+VSUBSSZrrbk_Int 6669
+VSUBSSZrrbkz_Int 6670
+VSUBSSZrrk_Int 6671
+VSUBSSZrrkz_Int 6672
+VSUBSSrm 6673
+VSUBSSrm_Int 6674
+VSUBSSrr 6675
+VSUBSSrr_Int 6676
+VTESTPDYrm 6677
+VTESTPDYrr 6678
+VTESTPDrm 6679
+VTESTPDrr 6680
+VTESTPSYrm 6681
+VTESTPSYrr 6682
+VTESTPSrm 6683
+VTESTPSrr 6684
+VUCOMISDZrm 6685
+VUCOMISDZrm_Int 6686
+VUCOMISDZrr 6687
+VUCOMISDZrr_Int 6688
+VUCOMISDZrrb 6689
+VUCOMISDrm 6690
+VUCOMISDrm_Int 6691
+VUCOMISDrr 6692
+VUCOMISDrr_Int 6693
+VUCOMISHZrm 6694
+VUCOMISHZrm_Int 6695
+VUCOMISHZrr 6696
+VUCOMISHZrr_Int 6697
+VUCOMISHZrrb 6698
+VUCOMISSZrm 6699
+VUCOMISSZrm_Int 6700
+VUCOMISSZrr 6701
+VUCOMISSZrr_Int 6702
+VUCOMISSZrrb 6703
+VUCOMISSrm 6704
+VUCOMISSrm_Int 6705
+VUCOMISSrr 6706
+VUCOMISSrr_Int 6707
+VUCOMXSDZrm 6708
+VUCOMXSDZrm_Int 6709
+VUCOMXSDZrr 6710
+VUCOMXSDZrr_Int 6711
+VUCOMXSDZrrb_Int 6712
+VUCOMXSHZrm 6713
+VUCOMXSHZrm_Int 6714
+VUCOMXSHZrr 6715
+VUCOMXSHZrr_Int 6716
+VUCOMXSHZrrb_Int 6717
+VUCOMXSSZrm 6718
+VUCOMXSSZrm_Int 6719
+VUCOMXSSZrr 6720
+VUCOMXSSZrr_Int 6721
+VUCOMXSSZrrb_Int 6722
+VUNPCKHPDYrm 6723
+VUNPCKHPDYrr 6724
+VUNPCKHPDZ 6725
+VUNPCKHPDZrm 6726
+VUNPCKHPDZrmb 6727
+VUNPCKHPDZrmbk 6728
+VUNPCKHPDZrmbkz 6729
+VUNPCKHPDZrmk 6730
+VUNPCKHPDZrmkz 6731
+VUNPCKHPDZrr 6732
+VUNPCKHPDZrrk 6733
+VUNPCKHPDZrrkz 6734
+VUNPCKHPDrm 6735
+VUNPCKHPDrr 6736
+VUNPCKHPSYrm 6737
+VUNPCKHPSYrr 6738
+VUNPCKHPSZ 6739
+VUNPCKHPSZrm 6740
+VUNPCKHPSZrmb 6741
+VUNPCKHPSZrmbk 6742
+VUNPCKHPSZrmbkz 6743
+VUNPCKHPSZrmk 6744
+VUNPCKHPSZrmkz 6745
+VUNPCKHPSZrr 6746
+VUNPCKHPSZrrk 6747
+VUNPCKHPSZrrkz 6748
+VUNPCKHPSrm 6749
+VUNPCKHPSrr 6750
+VUNPCKLPDYrm 6751
+VUNPCKLPDYrr 6752
+VUNPCKLPDZ 6753
+VUNPCKLPDZrm 6754
+VUNPCKLPDZrmb 6755
+VUNPCKLPDZrmbk 6756
+VUNPCKLPDZrmbkz 6757
+VUNPCKLPDZrmk 6758
+VUNPCKLPDZrmkz 6759
+VUNPCKLPDZrr 6760
+VUNPCKLPDZrrk 6761
+VUNPCKLPDZrrkz 6762
+VUNPCKLPDrm 6763
+VUNPCKLPDrr 6764
+VUNPCKLPSYrm 6765
+VUNPCKLPSYrr 6766
+VUNPCKLPSZ 6767
+VUNPCKLPSZrm 6768
+VUNPCKLPSZrmb 6769
+VUNPCKLPSZrmbk 6770
+VUNPCKLPSZrmbkz 6771
+VUNPCKLPSZrmk 6772
+VUNPCKLPSZrmkz 6773
+VUNPCKLPSZrr 6774
+VUNPCKLPSZrrk 6775
+VUNPCKLPSZrrkz 6776
+VUNPCKLPSrm 6777
+VUNPCKLPSrr 6778
+VXORPDYrm 6779
+VXORPDYrr 6780
+VXORPDZ 6781
+VXORPDZrm 6782
+VXORPDZrmb 6783
+VXORPDZrmbk 6784
+VXORPDZrmbkz 6785
+VXORPDZrmk 6786
+VXORPDZrmkz 6787
+VXORPDZrr 6788
+VXORPDZrrk 6789
+VXORPDZrrkz 6790
+VXORPDrm 6791
+VXORPDrr 6792
+VXORPSYrm 6793
+VXORPSYrr 6794
+VXORPSZ 6795
+VXORPSZrm 6796
+VXORPSZrmb 6797
+VXORPSZrmbk 6798
+VXORPSZrmbkz 6799
+VXORPSZrmk 6800
+VXORPSZrmkz 6801
+VXORPSZrr 6802
+VXORPSZrrk 6803
+VXORPSZrrkz 6804
+VXORPSrm 6805
+VXORPSrr 6806
+VZEROALL 6807
+VZEROUPPER 6808
+V_SET 6809
+V_SETALLONES 6810
+WAIT 6811
+WBINVD 6812
+WBNOINVD 6813
+WRFLAGS 6814
+WRFSBASE 6815
+WRGSBASE 6816
+WRMSR 6817
+WRMSRLIST 6818
+WRMSRNS 6819
+WRMSRNSir 6820
+WRMSRNSir_EVEX 6821
+WRPKRUr 6822
+WRSSD 6823
+WRSSD_EVEX 6824
+WRSSQ 6825
+WRSSQ_EVEX 6826
+WRUSSD 6827
+WRUSSD_EVEX 6828
+WRUSSQ 6829
+WRUSSQ_EVEX 6830
+XABORT 6831
+XABORT_DEF 6832
+XACQUIRE_PREFIX 6833
+XADD 6834
+XAM_F 6835
+XAM_Fp 6836
+XBEGIN 6837
+XCHG 6838
+XCH_F 6839
+XCRYPTCBC 6840
+XCRYPTCFB 6841
+XCRYPTCTR 6842
+XCRYPTECB 6843
+XCRYPTOFB 6844
+XEND 6845
+XGETBV 6846
+XLAT 6847
+XOR 6848
+XORPDrm 6849
+XORPDrr 6850
+XORPSrm 6851
+XORPSrr 6852
+XRELEASE_PREFIX 6853
+XRESLDTRK 6854
+XRSTOR 6855
+XRSTORS 6856
+XSAVE 6857
+XSAVEC 6858
+XSAVEOPT 6859
+XSAVES 6860
+XSETBV 6861
+XSHA 6862
+XSTORE 6863
+XSUSLDTRK 6864
+XTEST 6865
+Immediate 6866
+CImmediate 6867
+FPImmediate 6868
+MBB 6869
+FrameIndex 6870
+ConstantPoolIndex 6871
+TargetIndex 6872
+JumpTableIndex 6873
+ExternalSymbol 6874
+GlobalAddress 6875
+BlockAddress 6876
+RegisterMask 6877
+RegisterLiveOut 6878
+Metadata 6879
+MCSymbol 6880
+CFIIndex 6881
+IntrinsicID 6882
+Predicate 6883
+ShuffleMask 6884
+PhyReg_GR8 6885
+PhyReg_GRH8 6886
+PhyReg_GR8_NOREX2 6887
+PhyReg_GR8_NOREX 6888
+PhyReg_GR8_ABCD_H 6889
+PhyReg_GR8_ABCD_L 6890
+PhyReg_GRH16 6891
+PhyReg_GR16 6892
+PhyReg_GR16_NOREX2 6893
+PhyReg_GR16_NOREX 6894
+PhyReg_VK1 6895
+PhyReg_VK16 6896
+PhyReg_VK2 6897
+PhyReg_VK4 6898
+PhyReg_VK8 6899
+PhyReg_VK16WM 6900
+PhyReg_VK1WM 6901
+PhyReg_VK2WM 6902
+PhyReg_VK4WM 6903
+PhyReg_VK8WM 6904
+PhyReg_SEGMENT_REG 6905
+PhyReg_GR16_ABCD 6906
+PhyReg_FPCCR 6907
+PhyReg_FR16X 6908
+PhyReg_FR16 6909
+PhyReg_VK16PAIR 6910
+PhyReg_VK1PAIR 6911
+PhyReg_VK2PAIR 6912
+PhyReg_VK4PAIR 6913
+PhyReg_VK8PAIR 6914
+PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6915
+PhyReg_LOW32_ADDR_ACCESS_RBP 6916
+PhyReg_LOW32_ADDR_ACCESS 6917
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6918
+PhyReg_FR32X 6919
+PhyReg_GR32 6920
+PhyReg_GR32_NOSP 6921
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6922
+PhyReg_DEBUG_REG 6923
+PhyReg_FR32 6924
+PhyReg_GR32_NOREX2 6925
+PhyReg_GR32_NOREX2_NOSP 6926
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6927
+PhyReg_GR32_NOREX 6928
+PhyReg_VK32 6929
+PhyReg_GR32_NOREX_NOSP 6930
+PhyReg_RFP32 6931
+PhyReg_VK32WM 6932
+PhyReg_GR32_ABCD 6933
+PhyReg_GR32_TC 6934
+PhyReg_GR32_ABCD_and_GR32_TC 6935
+PhyReg_GR32_AD 6936
+PhyReg_GR32_ArgRef 6937
+PhyReg_GR32_BPSP 6938
+PhyReg_GR32_BSI 6939
+PhyReg_GR32_CB 6940
+PhyReg_GR32_DC 6941
+PhyReg_GR32_DIBP 6942
+PhyReg_GR32_SIDI 6943
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6944
+PhyReg_CCR 6945
+PhyReg_DFCCR 6946
+PhyReg_GR32_ABCD_and_GR32_BSI 6947
+PhyReg_GR32_AD_and_GR32_ArgRef 6948
+PhyReg_GR32_ArgRef_and_GR32_CB 6949
+PhyReg_GR32_BPSP_and_GR32_DIBP 6950
+PhyReg_GR32_BPSP_and_GR32_TC 6951
+PhyReg_GR32_BSI_and_GR32_SIDI 6952
+PhyReg_GR32_DIBP_and_GR32_SIDI 6953
+PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6954
+PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6955
+PhyReg_RFP64 6956
+PhyReg_GR64 6957
+PhyReg_FR64X 6958
+PhyReg_GR64_with_sub_8bit 6959
+PhyReg_GR64_NOSP 6960
+PhyReg_GR64_NOREX2 6961
+PhyReg_CONTROL_REG 6962
+PhyReg_FR64 6963
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6964
+PhyReg_GR64_NOREX2_NOSP 6965
+PhyReg_GR64PLTSafe 6966
+PhyReg_GR64_TC 6967
+PhyReg_GR64_NOREX 6968
+PhyReg_GR64_TCW64 6969
+PhyReg_GR64_TC_with_sub_8bit 6970
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6971
+PhyReg_GR64_TCW64_with_sub_8bit 6972
+PhyReg_GR64_TC_and_GR64_TCW64 6973
+PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6974
+PhyReg_VK64 6975
+PhyReg_VR64 6976
+PhyReg_GR64PLTSafe_and_GR64_TC 6977
+PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6978
+PhyReg_GR64_NOREX_NOSP 6979
+PhyReg_GR64_NOREX_and_GR64_TC 6980
+PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6981
+PhyReg_VK64WM 6982
+PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6983
+PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 6984
+PhyReg_GR64PLTSafe_and_GR64_TCW64 6985
+PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 6986
+PhyReg_GR64_NOREX_and_GR64_TCW64 6987
+PhyReg_GR64_ABCD 6988
+PhyReg_GR64_with_sub_32bit_in_GR32_TC 6989
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 6990
+PhyReg_GR64_AD 6991
+PhyReg_GR64_ArgRef 6992
+PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 6993
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 6994
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 6995
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI 6996
+PhyReg_GR64_with_sub_32bit_in_GR32_CB 6997
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 6998
+PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 6999
+PhyReg_GR64_A 7000
+PhyReg_GR64_ArgRef_and_GR64_TC 7001
+PhyReg_GR64_and_LOW32_ADDR_ACCESS 7002
+PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7003
+PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7004
+PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7005
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7006
+PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7007
+PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7008
+PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7009
+PhyReg_RST 7010
+PhyReg_RFP80 7011
+PhyReg_RFP80_7 7012
+PhyReg_VR128X 7013
+PhyReg_VR128 7014
+PhyReg_VR256X 7015
+PhyReg_VR256 7016
+PhyReg_VR512 7017
+PhyReg_VR512_0_15 7018
+PhyReg_TILE 7019
+VirtReg_GR8 7020
+VirtReg_GRH8 7021
+VirtReg_GR8_NOREX2 7022
+VirtReg_GR8_NOREX 7023
+VirtReg_GR8_ABCD_H 7024
+VirtReg_GR8_ABCD_L 7025
+VirtReg_GRH16 7026
+VirtReg_GR16 7027
+VirtReg_GR16_NOREX2 7028
+VirtReg_GR16_NOREX 7029
+VirtReg_VK1 7030
+VirtReg_VK16 7031
+VirtReg_VK2 7032
+VirtReg_VK4 7033
+VirtReg_VK8 7034
+VirtReg_VK16WM 7035
+VirtReg_VK1WM 7036
+VirtReg_VK2WM 7037
+VirtReg_VK4WM 7038
+VirtReg_VK8WM 7039
+VirtReg_SEGMENT_REG 7040
+VirtReg_GR16_ABCD 7041
+VirtReg_FPCCR 7042
+VirtReg_FR16X 7043
+VirtReg_FR16 7044
+VirtReg_VK16PAIR 7045
+VirtReg_VK1PAIR 7046
+VirtReg_VK2PAIR 7047
+VirtReg_VK4PAIR 7048
+VirtReg_VK8PAIR 7049
+VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7050
+VirtReg_LOW32_ADDR_ACCESS_RBP 7051
+VirtReg_LOW32_ADDR_ACCESS 7052
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7053
+VirtReg_FR32X 7054
+VirtReg_GR32 7055
+VirtReg_GR32_NOSP 7056
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7057
+VirtReg_DEBUG_REG 7058
+VirtReg_FR32 7059
+VirtReg_GR32_NOREX2 7060
+VirtReg_GR32_NOREX2_NOSP 7061
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7062
+VirtReg_GR32_NOREX 7063
+VirtReg_VK32 7064
+VirtReg_GR32_NOREX_NOSP 7065
+VirtReg_RFP32 7066
+VirtReg_VK32WM 7067
+VirtReg_GR32_ABCD 7068
+VirtReg_GR32_TC 7069
+VirtReg_GR32_ABCD_and_GR32_TC 7070
+VirtReg_GR32_AD 7071
+VirtReg_GR32_ArgRef 7072
+VirtReg_GR32_BPSP 7073
+VirtReg_GR32_BSI 7074
+VirtReg_GR32_CB 7075
+VirtReg_GR32_DC 7076
+VirtReg_GR32_DIBP 7077
+VirtReg_GR32_SIDI 7078
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7079
+VirtReg_CCR 7080
+VirtReg_DFCCR 7081
+VirtReg_GR32_ABCD_and_GR32_BSI 7082
+VirtReg_GR32_AD_and_GR32_ArgRef 7083
+VirtReg_GR32_ArgRef_and_GR32_CB 7084
+VirtReg_GR32_BPSP_and_GR32_DIBP 7085
+VirtReg_GR32_BPSP_and_GR32_TC 7086
+VirtReg_GR32_BSI_and_GR32_SIDI 7087
+VirtReg_GR32_DIBP_and_GR32_SIDI 7088
+VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7089
+VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7090
+VirtReg_RFP64 7091
+VirtReg_GR64 7092
+VirtReg_FR64X 7093
+VirtReg_GR64_with_sub_8bit 7094
+VirtReg_GR64_NOSP 7095
+VirtReg_GR64_NOREX2 7096
+VirtReg_CONTROL_REG 7097
+VirtReg_FR64 7098
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7099
+VirtReg_GR64_NOREX2_NOSP 7100
+VirtReg_GR64PLTSafe 7101
+VirtReg_GR64_TC 7102
+VirtReg_GR64_NOREX 7103
+VirtReg_GR64_TCW64 7104
+VirtReg_GR64_TC_with_sub_8bit 7105
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7106
+VirtReg_GR64_TCW64_with_sub_8bit 7107
+VirtReg_GR64_TC_and_GR64_TCW64 7108
+VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7109
+VirtReg_VK64 7110
+VirtReg_VR64 7111
+VirtReg_GR64PLTSafe_and_GR64_TC 7112
+VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7113
+VirtReg_GR64_NOREX_NOSP 7114
+VirtReg_GR64_NOREX_and_GR64_TC 7115
+VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7116
+VirtReg_VK64WM 7117
+VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7118
+VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7119
+VirtReg_GR64PLTSafe_and_GR64_TCW64 7120
+VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7121
+VirtReg_GR64_NOREX_and_GR64_TCW64 7122
+VirtReg_GR64_ABCD 7123
+VirtReg_GR64_with_sub_32bit_in_GR32_TC 7124
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7125
+VirtReg_GR64_AD 7126
+VirtReg_GR64_ArgRef 7127
+VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7128
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7129
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7130
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7131
+VirtReg_GR64_with_sub_32bit_in_GR32_CB 7132
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7133
+VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7134
+VirtReg_GR64_A 7135
+VirtReg_GR64_ArgRef_and_GR64_TC 7136
+VirtReg_GR64_and_LOW32_ADDR_ACCESS 7137
+VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7138
+VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7139
+VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7140
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7141
+VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7142
+VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7143
+VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7144
+VirtReg_RST 7145
+VirtReg_RFP80 7146
+VirtReg_RFP80_7 7147
+VirtReg_VR128X 7148
+VirtReg_VR128 7149
+VirtReg_VR256X 7150
+VirtReg_VR256 7151
+VirtReg_VR512 7152
+VirtReg_VR512_0_15 7153
+VirtReg_TILE 7154
>From d5c45dad9d2f0a2623c73e58eceb0fd6292c3b95 Mon Sep 17 00:00:00 2001
From: Josh Rodriguez <Josh.Rodriguez at arm.com>
Date: Tue, 18 Nov 2025 13:52:27 +0000
Subject: [PATCH 18/18] [X86][GlobalISel] Patched triplets.mir test
Third of 3 tests that need changing due to implementation of new generic intrinsics
---
.../llvm-ir2vec/output/reference_triplets.txt | 56 +++++++++----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
index 141a56ad10903..f4ec3f096386f 100644
--- a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
+++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt
@@ -1,33 +1,33 @@
MAX_RELATION=4
-187 7051 1
-187 6948 2
+187 7055 1
+187 6952 2
187 187 0
-187 7051 1
-187 6949 2
+187 7055 1
+187 6953 2
187 10 0
-10 7051 1
-10 7051 2
-10 7051 3
-10 6941 4
+10 7055 1
+10 7055 2
+10 7055 3
+10 6945 4
10 187 0
-187 6932 1
-187 7051 2
-187 1543 0
-1543 6862 1
-1543 6932 2
-187 7051 1
-187 6948 2
+187 6936 1
+187 7055 2
+187 1547 0
+1547 6866 1
+1547 6936 2
+187 7055 1
+187 6952 2
187 187 0
-187 7051 1
-187 6949 2
-187 601 0
-601 7051 1
-601 7051 2
-601 7051 3
-601 6941 4
-601 187 0
-187 6932 1
-187 7051 2
-187 1543 0
-1543 6862 1
-1543 6932 2
+187 7055 1
+187 6953 2
+187 605 0
+605 7055 1
+605 7055 2
+605 7055 3
+605 6945 4
+605 187 0
+187 6936 1
+187 7055 2
+187 1547 0
+1547 6866 1
+1547 6936 2
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