[llvm] [RISCV] tt-ascalon-d8 vector scheduling (PR #167066)

[Petr Penzin via llvm-commits]

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@@ -316,10 +409,634 @@ def : ReadAdvance<ReadSHXADD32, 0>;
 def : ReadAdvance<ReadSingleBit, 0>;
 def : ReadAdvance<ReadSingleBitImm, 0>;
 
+//===----------------------------------------------------------------------===//
+// Vector
+def : WriteRes<WriteRdVLENB, [AscalonFXA]>;
+
+// Configuration-Setting Instructions
+let Latency = 1 in {
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ppenzin wrote:

Addressed

https://github.com/llvm/llvm-project/pull/167066