[llvm] [AArch64][SVE] Add basic support for `@llvm.masked.compressstore` (PR #168350)

[Paul Walker via llvm-commits]

================
@@ -30180,6 +30185,36 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorStoreToSVE(
                             Store->isTruncatingStore());
 }
 
+SDValue AArch64TargetLowering::LowerMSTORE(SDValue Op,
+                                           SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  auto *Store = cast<MaskedStoreSDNode>(Op);
+  EVT VT = Store->getValue().getValueType();
+  if (VT.isFixedLengthVector())
+    return LowerFixedLengthVectorMStoreToSVE(Op, DAG);
+
+  if (!Store->isCompressingStore())
+    return SDValue();
+
+  EVT MaskVT = Store->getMask().getValueType();
+
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
+  SDValue CntActive =
+      DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i64, Store->getMask());
----------------
paulwalker-arm wrote:

While `ISD::VECREDUCE_ADD` supports a larger result type than its operand's element type, the extra bits are undefined. In this case that means only the bottom but of the result can be relied upon with the operation likely converted to a `ISD::VECREDUCE_XOR`.

Fixing the above might make this request impossible but can this be done as target agnostic expansion? 

https://github.com/llvm/llvm-project/pull/168350