[llvm] [X86][GISel] Fix crash on bitcasting i16 <-> half with gisel enabled. (PR #168456)

[Craig Topper via llvm-commits]

================
@@ -4366,6 +4367,30 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
     Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
                              : (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
+
+  else if (X86::GR16RegClass.contains(DestReg) &&
----------------
topperc wrote:

> GlobalIsel shouldn't really encounter new types of MIR to deal with later, and it's more likely globalisel is producing something malformed. What is the MIR coming out of the selector?

```
bb.1.entry:
  liveins: $edi
  %1:gr32 = COPY $edi
  %0:gr16 = COPY %1.sub_16bit:gr32
  $xmm0 = COPY %0:gr16
  RET 0, implicit $xmm0
```

SelectionDAG uses these patterns.
```
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (PINSRWrri (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (VPINSRWrri (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
```

https://github.com/llvm/llvm-project/pull/168456