[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)

[Simon Wallis via llvm-commits]

================
@@ -1564,10 +1590,11 @@ def : InstRW<[N3Write_2c_1M], (instregex "^REV_PP_[BHSD]")>;
 def : InstRW<[N3Write_1c_1M], (instrs SEL_PPPP)>;
 
 // Predicate set
-def : InstRW<[N3Write_2c_1M], (instregex "^PFALSE", "^PTRUE_[BHSD]")>;
+def : InstRW<[N3Write_0c], (instregex "^PFALSE")>;
----------------
simonwallis2 wrote:

Unnecessary regexes now removed here too.

https://github.com/llvm/llvm-project/pull/165690