[llvm] [X86] Enable zmms generation on NVL and DMR by default (PR #168413)

[Mikołaj Piróg via llvm-commits]

https://github.com/mikolaj-pirog created https://github.com/llvm/llvm-project/pull/168413

As in title.

>From 2fdda2580acde4abe3635a70c8c8574754055b40 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 17 Nov 2025 18:53:02 +0100
Subject: [PATCH] Enable zmms on NVL and DMR by default

---
 llvm/lib/Target/X86/X86.td | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 27ec052cfda40..ee1953ece87ba 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1177,6 +1177,7 @@ def ProcessorFeatures {
                                                   FeatureAMXTF32];
   list<SubtargetFeature> DMRFeatures =
     !listconcat(GNRDFeatures, DMRAdditionalFeatures);
+  list<SubtargetFeature> DMRTuning = !listremove(GNRTuning, [TuningPrefer256Bit]);
 
   // Atom
   list<SubtargetFeature> AtomFeatures = [FeatureX87,
@@ -1346,6 +1347,7 @@ def ProcessorFeatures {
                                                   FeaturePREFETCHI];
   list<SubtargetFeature> NVLFeatures =
       !listconcat(PTLFeatures, NVLAdditionalFeatures);
+  list<SubtargetFeature> NVLTuning = !listremove(ADLTuning, [TuningPrefer256Bit]);
 
   // Clearwaterforest
   list<SubtargetFeature> CWFAdditionalFeatures = [FeaturePREFETCHI,
@@ -1893,7 +1895,7 @@ def : ProcModel<P, AlderlakePModel,
                 ProcessorFeatures.PTLFeatures, ProcessorFeatures.ADLTuning>;
 }
 def : ProcModel<"novalake", AlderlakePModel, ProcessorFeatures.NVLFeatures,
-                ProcessorFeatures.ADLTuning>;
+                ProcessorFeatures.NVLTuning>;
 
 def : ProcModel<"clearwaterforest", AlderlakePModel,
                 ProcessorFeatures.CWFFeatures, ProcessorFeatures.ADLTuning>;
@@ -1906,7 +1908,7 @@ def : ProcModel<P, SapphireRapidsModel,
                 ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
 }
 def : ProcModel<"diamondrapids", SapphireRapidsModel,
-                ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;
+                ProcessorFeatures.DMRFeatures, ProcessorFeatures.DMRTuning>;
 
 // AMD CPUs.