[llvm] [AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (PR #159818)

[Anshil Gandhi via llvm-commits]

https://github.com/gandhi56 updated https://github.com/llvm/llvm-project/pull/159818

>From 534241c14c5332abf036cc86735021814ce2b4b3 Mon Sep 17 00:00:00 2001
From: Anshil Gandhi <Anshil.Gandhi at amd.com>
Date: Fri, 19 Sep 2025 12:06:18 -0500
Subject: [PATCH] [AMDGPU] Add regbankselect rules for G_FSHR

---
 .../AMDGPU/AMDGPURegBankLegalizeRules.cpp     |  4 ++
 .../GlobalISel/fshr-new-regbank-select.ll     | 37 +++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 103cdec8233a0..192fc05ad05de 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -526,6 +526,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
       .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}});
 
+  addRulesForGOpcs({G_FSHR}, Standard)
+      .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}})
+      .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}});
+
   addRulesForGOpcs({G_FRAME_INDEX}).Any({{UniP5, _}, {{SgprP5}, {None}}});
 
   addRulesForGOpcs({G_UBFX, G_SBFX}, Standard)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
new file mode 100644
index 0000000000000..aa444c6e3a210
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck %s
+
+define amdgpu_ps i32 @uniform_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
+; CHECK-LABEL: uniform_fshr_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v2
+; CHECK-NEXT:    v_readfirstlane_b32 s1, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s2, v1
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s0
+; CHECK-NEXT:    v_alignbit_b32 v0, s1, s2, v0
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    s_wait_alu 0xf1ff
+; CHECK-NEXT:    ; return to shader part epilog
+  %ulhs = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %lhs)
+  %urhs = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %rhs)
+  %uamt = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %amt)
+  %vres = call i32 @llvm.fshr.i32(i32 %ulhs, i32 %urhs, i32 %uamt)
+  ret i32 %vres
+}
+
+declare i32 @llvm.amdgcn.readfirstlane.i32(i32)
+
+define amdgpu_ps i32 @divergent_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
+; CHECK-LABEL: divergent_fshr_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_alignbit_b32 v0, v0, v1, v2
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    ; return to shader part epilog
+  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
+  ret i32 %result
+}
+
+declare i32 @llvm.fshr.i32(i32, i32, i32)