[llvm] [AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (PR #159818)

[Petar Avramovic via llvm-commits]

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@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck %s
+
+define amdgpu_ps i32 @uniform_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt) {
+; CHECK-LABEL: uniform_fshr_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_mov_b32_e32 v0, s2
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; CHECK-NEXT:    v_alignbit_b32 v0, s0, s1, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    s_wait_alu 0xf1ff
+; CHECK-NEXT:    ; return to shader part epilog
+  %vres = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
+  ret i32 %vres
+}
+
+declare i32 @llvm.amdgcn.readfirstlane.i32(i32)
+
+define amdgpu_ps i32 @divergent_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt) {
+; CHECK-LABEL: divergent_fshr_i32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_alignbit_b32 v0, v0, v1, v2
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    ; return to shader part epilog
+  %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)
+  ret i32 %result
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petar-avramovic wrote:

Can you change test to store instead of return to avoid having v_readfirstlane_b32 that is not because of regbanklegalize.

https://github.com/llvm/llvm-project/pull/159818