[llvm] [X86] TableGen-erate SDNode descriptions (PR #168421)

[Sergei Barannikov via llvm-commits]

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@@ -5265,6 +5265,8 @@ multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
 let Predicates = [HasAVX, NoBWI] in
   defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX, WIG;
 
+// Extract an 8-bit value from a vector and zero extend it to
+// i32, corresponds to X86::PEXTRB.
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s-barannikov wrote:

Thanks, moved

https://github.com/llvm/llvm-project/pull/168421