[llvm] 97a60aa - [CodeGen] Turn MCRegUnit into an enum class (NFC) (#167943)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 16 09:46:48 PST 2025
Author: Sergei Barannikov
Date: 2025-11-16T20:46:44+03:00
New Revision: 97a60aa37a048155fec0c560fc51ed52dbd84e44
URL: https://github.com/llvm/llvm-project/commit/97a60aa37a048155fec0c560fc51ed52dbd84e44
DIFF: https://github.com/llvm/llvm-project/commit/97a60aa37a048155fec0c560fc51ed52dbd84e44.diff
LOG: [CodeGen] Turn MCRegUnit into an enum class (NFC) (#167943)
This changes `MCRegUnit` type from `unsigned` to `enum class : unsigned`
and inserts necessary casts.
The added `MCRegUnitToIndex` functor is used with `SparseSet`,
`SparseMultiSet` and `IndexedMap` in a few places.
`MCRegUnit` is opaque to users, so it didn't seem worth making it a
full-fledged class like `Register`.
Static type checking has detected one issue in
`PrologueEpilogueInserter.cpp`, where `BitVector` created for
`MCRegister` is indexed by both `MCRegister` and `MCRegUnit`.
The number of casts could be reduced by using `IndexedMap` in more
places and/or adding a `BitVector` adaptor, but the number of casts *per
file* is still small and `IndexedMap` has limitations, so it didn't seem
worth the effort.
Pull Request: https://github.com/llvm/llvm-project/pull/167943
Added:
Modified:
llvm/include/llvm/CodeGen/LiveIntervalUnion.h
llvm/include/llvm/CodeGen/LiveIntervals.h
llvm/include/llvm/CodeGen/LiveRegMatrix.h
llvm/include/llvm/CodeGen/LiveRegUnits.h
llvm/include/llvm/CodeGen/MachineTraceMetrics.h
llvm/include/llvm/CodeGen/RDFRegisters.h
llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
llvm/include/llvm/CodeGen/Register.h
llvm/include/llvm/CodeGen/RegisterClassInfo.h
llvm/include/llvm/CodeGen/RegisterPressure.h
llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/include/llvm/MC/MCRegister.h
llvm/include/llvm/MC/MCRegisterInfo.h
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/InterferenceCache.cpp
llvm/lib/CodeGen/LiveIntervals.cpp
llvm/lib/CodeGen/LiveRegMatrix.cpp
llvm/lib/CodeGen/LiveRegUnits.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachineInstrBundle.cpp
llvm/lib/CodeGen/MachineLICM.cpp
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/RDFRegisters.cpp
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegisterClassInfo.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/X86/X86FixupBWInsts.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
index cc0f2a45bb182..240fa114cf179 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervalUnion.h
@@ -191,14 +191,14 @@ class LiveIntervalUnion {
void clear();
- LiveIntervalUnion& operator[](unsigned idx) {
- assert(idx < Size && "idx out of bounds");
- return LIUs[idx];
+ LiveIntervalUnion &operator[](MCRegUnit Unit) {
+ assert(static_cast<unsigned>(Unit) < Size && "Unit out of bounds");
+ return LIUs[static_cast<unsigned>(Unit)];
}
- const LiveIntervalUnion& operator[](unsigned Idx) const {
- assert(Idx < Size && "Idx out of bounds");
- return LIUs[Idx];
+ const LiveIntervalUnion &operator[](MCRegUnit Unit) const {
+ assert(static_cast<unsigned>(Unit) < Size && "Unit out of bounds");
+ return LIUs[static_cast<unsigned>(Unit)];
}
};
};
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index 32027766e7093..b618e0b778ae8 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -413,11 +413,12 @@ class LiveIntervals {
/// Return the live range for register unit \p Unit. It will be computed if
/// it doesn't exist.
LiveRange &getRegUnit(MCRegUnit Unit) {
- LiveRange *LR = RegUnitRanges[Unit];
+ LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];
if (!LR) {
// Compute missing ranges on demand.
// Use segment set to speed-up initial computation of the live range.
- RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
+ RegUnitRanges[static_cast<unsigned>(Unit)] = LR =
+ new LiveRange(UseSegmentSetForPhysRegs);
computeRegUnitRange(*LR, Unit);
}
return *LR;
@@ -425,17 +426,19 @@ class LiveIntervals {
/// Return the live range for register unit \p Unit if it has already been
/// computed, or nullptr if it hasn't been computed yet.
- LiveRange *getCachedRegUnit(MCRegUnit Unit) { return RegUnitRanges[Unit]; }
+ LiveRange *getCachedRegUnit(MCRegUnit Unit) {
+ return RegUnitRanges[static_cast<unsigned>(Unit)];
+ }
const LiveRange *getCachedRegUnit(MCRegUnit Unit) const {
- return RegUnitRanges[Unit];
+ return RegUnitRanges[static_cast<unsigned>(Unit)];
}
/// Remove computed live range for register unit \p Unit. Subsequent uses
/// should rely on on-demand recomputation.
void removeRegUnit(MCRegUnit Unit) {
- delete RegUnitRanges[Unit];
- RegUnitRanges[Unit] = nullptr;
+ delete RegUnitRanges[static_cast<unsigned>(Unit)];
+ RegUnitRanges[static_cast<unsigned>(Unit)] = nullptr;
}
/// Remove associated live ranges for the register units associated with \p
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 0bc243271bb73..35add577d071a 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -165,7 +165,9 @@ class LiveRegMatrix {
/// Directly access the live interval unions per regunit.
/// This returns an array indexed by the regunit number.
- LiveIntervalUnion *getLiveUnions() { return &Matrix[0]; }
+ LiveIntervalUnion *getLiveUnions() {
+ return &Matrix[static_cast<MCRegUnit>(0)];
+ }
Register getOneVReg(unsigned PhysReg) const;
};
diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h
index 37c31cc6f4ac5..0ff5273929671 100644
--- a/llvm/include/llvm/CodeGen/LiveRegUnits.h
+++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h
@@ -86,23 +86,23 @@ class LiveRegUnits {
/// Adds register units covered by physical register \p Reg.
void addReg(MCRegister Reg) {
for (MCRegUnit Unit : TRI->regunits(Reg))
- Units.set(Unit);
+ Units.set(static_cast<unsigned>(Unit));
}
/// Adds register units covered by physical register \p Reg that are
/// part of the lanemask \p Mask.
void addRegMasked(MCRegister Reg, LaneBitmask Mask) {
- for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
- LaneBitmask UnitMask = (*Unit).second;
+ for (MCRegUnitMaskIterator I(Reg, TRI); I.isValid(); ++I) {
+ auto [Unit, UnitMask] = *I;
if ((UnitMask & Mask).any())
- Units.set((*Unit).first);
+ Units.set(static_cast<unsigned>(Unit));
}
}
/// Removes all register units covered by physical register \p Reg.
void removeReg(MCRegister Reg) {
for (MCRegUnit Unit : TRI->regunits(Reg))
- Units.reset(Unit);
+ Units.reset(static_cast<unsigned>(Unit));
}
/// Removes register units not preserved by the regmask \p RegMask.
@@ -116,7 +116,7 @@ class LiveRegUnits {
/// Returns true if no part of physical register \p Reg is live.
bool available(MCRegister Reg) const {
for (MCRegUnit Unit : TRI->regunits(Reg)) {
- if (Units.test(Unit))
+ if (Units.test(static_cast<unsigned>(Unit)))
return false;
}
return true;
diff --git a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
index d1be0ee3dfff9..b29984cd95a4b 100644
--- a/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
+++ b/llvm/include/llvm/CodeGen/MachineTraceMetrics.h
@@ -78,12 +78,12 @@ struct LiveRegUnit {
const MachineInstr *MI = nullptr;
unsigned Op = 0;
- unsigned getSparseSetIndex() const { return RegUnit; }
+ unsigned getSparseSetIndex() const { return static_cast<unsigned>(RegUnit); }
explicit LiveRegUnit(MCRegUnit RU) : RegUnit(RU) {}
};
-using LiveRegUnitSet = SparseSet<LiveRegUnit>;
+using LiveRegUnitSet = SparseSet<LiveRegUnit, MCRegUnit, MCRegUnitToIndex>;
/// Strategies for selecting traces.
enum class MachineTraceStrategy {
diff --git a/llvm/include/llvm/CodeGen/RDFRegisters.h b/llvm/include/llvm/CodeGen/RDFRegisters.h
index 6583efc00cf96..48e1e3487f11f 100644
--- a/llvm/include/llvm/CodeGen/RDFRegisters.h
+++ b/llvm/include/llvm/CodeGen/RDFRegisters.h
@@ -10,6 +10,7 @@
#define LLVM_CODEGEN_RDFREGISTERS_H
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -111,7 +112,7 @@ struct RegisterRef {
constexpr MCRegUnit asMCRegUnit() const {
assert(isUnit());
- return Id & ~UnitFlag;
+ return static_cast<MCRegUnit>(Id & ~UnitFlag);
}
constexpr unsigned asMaskIdx() const {
@@ -160,7 +161,7 @@ struct PhysicalRegisterInfo {
// Returns the set of aliased physical registers.
std::set<RegisterId> getAliasSet(RegisterRef RR) const;
- RegisterRef getRefForUnit(uint32_t U) const {
+ RegisterRef getRefForUnit(MCRegUnit U) const {
return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
}
@@ -170,7 +171,7 @@ struct PhysicalRegisterInfo {
std::set<RegisterId> getUnits(RegisterRef RR) const;
- const BitVector &getUnitAliases(uint32_t U) const {
+ const BitVector &getUnitAliases(MCRegUnit U) const {
return AliasInfos[U].Regs;
}
@@ -201,9 +202,9 @@ struct PhysicalRegisterInfo {
const TargetRegisterInfo &TRI;
IndexedSet<const uint32_t *> RegMasks;
std::vector<RegInfo> RegInfos;
- std::vector<UnitInfo> UnitInfos;
+ IndexedMap<UnitInfo, MCRegUnitToIndex> UnitInfos;
std::vector<MaskInfo> MaskInfos;
- std::vector<AliasInfo> AliasInfos;
+ IndexedMap<AliasInfo, MCRegUnitToIndex> AliasInfos;
};
struct RegisterRefEqualTo {
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index 2893e5ce6647e..863c3b39229b9 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -78,17 +78,17 @@ class MBBReachingDefsInfo {
}
void append(unsigned MBBNumber, MCRegUnit Unit, int Def) {
- AllReachingDefs[MBBNumber][Unit].push_back(Def);
+ AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].push_back(Def);
}
void prepend(unsigned MBBNumber, MCRegUnit Unit, int Def) {
- auto &Defs = AllReachingDefs[MBBNumber][Unit];
+ auto &Defs = AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)];
Defs.insert(Defs.begin(), Def);
}
void replaceFront(unsigned MBBNumber, MCRegUnit Unit, int Def) {
- assert(!AllReachingDefs[MBBNumber][Unit].empty());
- *AllReachingDefs[MBBNumber][Unit].begin() = Def;
+ assert(!AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].empty());
+ *AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].begin() = Def;
}
void clear() { AllReachingDefs.clear(); }
@@ -97,7 +97,7 @@ class MBBReachingDefsInfo {
if (AllReachingDefs[MBBNumber].empty())
// Block IDs are not necessarily dense.
return ArrayRef<ReachingDef>();
- return AllReachingDefs[MBBNumber][Unit];
+ return AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)];
}
private:
diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h
index 5e1e12942a019..f375af5808d1c 100644
--- a/llvm/include/llvm/CodeGen/Register.h
+++ b/llvm/include/llvm/CodeGen/Register.h
@@ -182,20 +182,25 @@ class VirtRegOrUnit {
unsigned VRegOrUnit;
public:
- constexpr explicit VirtRegOrUnit(MCRegUnit Unit) : VRegOrUnit(Unit) {
+ constexpr explicit VirtRegOrUnit(MCRegUnit Unit)
+ : VRegOrUnit(static_cast<unsigned>(Unit)) {
assert(!Register::isVirtualRegister(VRegOrUnit));
}
+
constexpr explicit VirtRegOrUnit(Register Reg) : VRegOrUnit(Reg.id()) {
assert(Reg.isVirtual());
}
+ // Catches implicit conversions to Register.
+ template <typename T> explicit VirtRegOrUnit(T) = delete;
+
constexpr bool isVirtualReg() const {
return Register::isVirtualRegister(VRegOrUnit);
}
constexpr MCRegUnit asMCRegUnit() const {
assert(!isVirtualReg() && "Not a register unit");
- return VRegOrUnit;
+ return static_cast<MCRegUnit>(VRegOrUnit);
}
constexpr Register asVirtualReg() const {
diff --git a/llvm/include/llvm/CodeGen/RegisterClassInfo.h b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
index 078ae80915fed..124c7aff8c76d 100644
--- a/llvm/include/llvm/CodeGen/RegisterClassInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
@@ -123,7 +123,7 @@ class RegisterClassInfo {
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
MCRegister CSR;
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
- CSR = CalleeSavedAliases[Unit];
+ CSR = CalleeSavedAliases[static_cast<unsigned>(Unit)];
if (CSR)
break;
}
diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h
index 20a7e4fa2e9de..7485be6dcb351 100644
--- a/llvm/include/llvm/CodeGen/RegisterPressure.h
+++ b/llvm/include/llvm/CodeGen/RegisterPressure.h
@@ -282,14 +282,14 @@ class LiveRegSet {
unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
if (VRegOrUnit.isVirtualReg())
return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
- assert(VRegOrUnit.asMCRegUnit() < NumRegUnits);
- return VRegOrUnit.asMCRegUnit();
+ assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
+ return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
}
VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
if (SparseIndex >= NumRegUnits)
return VirtRegOrUnit(Register::index2VirtReg(SparseIndex - NumRegUnits));
- return VirtRegOrUnit(SparseIndex);
+ return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
}
public:
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index 059a3444c609c..8b3907629c00b 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -82,14 +82,16 @@ namespace llvm {
PhysRegSUOper(SUnit *su, int op, MCRegUnit R)
: SU(su), OpIdx(op), RegUnit(R) {}
- unsigned getSparseSetIndex() const { return RegUnit; }
+ unsigned getSparseSetIndex() const {
+ return static_cast<unsigned>(RegUnit);
+ }
};
/// Use a SparseMultiSet to track physical registers. Storage is only
/// allocated once for the pass. It can be cleared in constant time and reused
/// without any frees.
using RegUnit2SUnitsMap =
- SparseMultiSet<PhysRegSUOper, unsigned, identity, uint16_t>;
+ SparseMultiSet<PhysRegSUOper, MCRegUnit, MCRegUnitToIndex, uint16_t>;
/// Track local uses of virtual registers. These uses are gathered by the DAG
/// builder and may be consulted by the scheduler to avoid iterating an entire
diff --git a/llvm/include/llvm/MC/MCRegister.h b/llvm/include/llvm/MC/MCRegister.h
index 388cb5958f32e..c6cde36478c1d 100644
--- a/llvm/include/llvm/MC/MCRegister.h
+++ b/llvm/include/llvm/MC/MCRegister.h
@@ -27,7 +27,15 @@ using MCPhysReg = uint16_t;
/// A target with a complicated sub-register structure will typically have many
/// fewer register units than actual registers. MCRI::getNumRegUnits() returns
/// the number of register units in the target.
-using MCRegUnit = unsigned;
+enum class MCRegUnit : unsigned;
+
+struct MCRegUnitToIndex {
+ using argument_type = MCRegUnit;
+
+ unsigned operator()(MCRegUnit Unit) const {
+ return static_cast<unsigned>(Unit);
+ }
+};
/// Wrapper class representing physical registers. Should be passed by value.
class MCRegister {
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index f1caa077a6d7b..6e36e580358e7 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -724,9 +724,10 @@ class MCRegUnitRootIterator {
MCRegUnitRootIterator() = default;
MCRegUnitRootIterator(MCRegUnit RegUnit, const MCRegisterInfo *MCRI) {
- assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
- Reg0 = MCRI->RegUnitRoots[RegUnit][0];
- Reg1 = MCRI->RegUnitRoots[RegUnit][1];
+ assert(static_cast<unsigned>(RegUnit) < MCRI->getNumRegUnits() &&
+ "Invalid register unit");
+ Reg0 = MCRI->RegUnitRoots[static_cast<unsigned>(RegUnit)][0];
+ Reg1 = MCRI->RegUnitRoots[static_cast<unsigned>(RegUnit)][1];
}
/// Dereference to get the current root register.
@@ -803,7 +804,9 @@ MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
}
inline iota_range<MCRegUnit> MCRegisterInfo::regunits() const {
- return seq(getNumRegUnits());
+ return enum_seq(static_cast<MCRegUnit>(0),
+ static_cast<MCRegUnit>(getNumRegUnits()),
+ force_iteration_on_noniterable_enum);
}
inline iterator_range<MCRegUnitIterator>
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 55caa6e8a8f95..28993c47c094d 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -134,7 +134,7 @@ class SSAIfConv {
BitVector ClobberedRegUnits;
// Scratch pad for findInsertionPoint.
- SparseSet<MCRegUnit> LiveRegUnits;
+ SparseSet<MCRegUnit, MCRegUnit, MCRegUnitToIndex> LiveRegUnits;
/// Insertion point in Head for speculatively executed instructions form TBB
/// and FBB.
@@ -271,7 +271,7 @@ bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) {
// Remember clobbered regunits.
if (MO.isDef() && Reg.isPhysical())
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
- ClobberedRegUnits.set(Unit);
+ ClobberedRegUnits.set(static_cast<unsigned>(Unit));
if (!MO.readsReg() || !Reg.isVirtual())
continue;
@@ -409,7 +409,7 @@ bool SSAIfConv::findInsertionPoint() {
// Anything read by I is live before I.
while (!Reads.empty())
for (MCRegUnit Unit : TRI->regunits(Reads.pop_back_val()))
- if (ClobberedRegUnits.test(Unit))
+ if (ClobberedRegUnits.test(static_cast<unsigned>(Unit)))
LiveRegUnits.insert(Unit);
// We can't insert before a terminator.
diff --git a/llvm/lib/CodeGen/InterferenceCache.cpp b/llvm/lib/CodeGen/InterferenceCache.cpp
index ebdf0506bb22f..466070b312b2d 100644
--- a/llvm/lib/CodeGen/InterferenceCache.cpp
+++ b/llvm/lib/CodeGen/InterferenceCache.cpp
@@ -93,7 +93,7 @@ void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
PrevPos = SlotIndex();
unsigned i = 0;
for (MCRegUnit Unit : TRI->regunits(PhysReg))
- RegUnits[i++].VirtTag = LIUArray[Unit].getTag();
+ RegUnits[i++].VirtTag = LIUArray[static_cast<unsigned>(Unit)].getTag();
}
void InterferenceCache::Entry::reset(MCRegister physReg,
@@ -110,7 +110,7 @@ void InterferenceCache::Entry::reset(MCRegister physReg,
PrevPos = SlotIndex();
RegUnits.clear();
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
- RegUnits.push_back(LIUArray[Unit]);
+ RegUnits.push_back(LIUArray[static_cast<unsigned>(Unit)]);
RegUnits.back().Fixed = &LIS->getRegUnit(Unit);
}
}
@@ -121,7 +121,7 @@ bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
if (i == e)
return false;
- if (LIUArray[Unit].changedSince(RegUnits[i].VirtTag))
+ if (LIUArray[static_cast<unsigned>(Unit)].changedSince(RegUnits[i].VirtTag))
return false;
++i;
}
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index b600e0411bc48..2e8756565c8f7 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -184,7 +184,8 @@ void LiveIntervals::print(raw_ostream &OS) const {
// Dump the regunits.
for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)
if (LiveRange *LR = RegUnitRanges[Unit])
- OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n';
+ OS << printRegUnit(static_cast<MCRegUnit>(Unit), TRI) << ' ' << *LR
+ << '\n';
// Dump the virtregs.
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
@@ -367,10 +368,11 @@ void LiveIntervals::computeLiveInRegUnits() {
LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
for (const auto &LI : MBB.liveins()) {
for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
- LiveRange *LR = RegUnitRanges[Unit];
+ LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];
if (!LR) {
// Use segment set to speed-up initial computation of the live range.
- LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
+ LR = RegUnitRanges[static_cast<unsigned>(Unit)] =
+ new LiveRange(UseSegmentSetForPhysRegs);
NewRanges.push_back(Unit);
}
VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
@@ -384,7 +386,7 @@ void LiveIntervals::computeLiveInRegUnits() {
// Compute the 'normal' part of the ranges.
for (MCRegUnit Unit : NewRanges)
- computeRegUnitRange(*RegUnitRanges[Unit], Unit);
+ computeRegUnitRange(*RegUnitRanges[static_cast<unsigned>(Unit)], Unit);
}
static void createSegmentsForValues(LiveRange &LR,
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index e3ee8dc325933..e7238008d2c69 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -76,7 +76,7 @@ void LiveRegMatrixWrapperLegacy::releaseMemory() { LRM.releaseMemory(); }
void LiveRegMatrix::releaseMemory() {
for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {
- Matrix[i].clear();
+ Matrix[static_cast<MCRegUnit>(i)].clear();
// No need to clear Queries here, since LiveIntervalUnion::Query doesn't
// have anything important to clear and LiveRegMatrix's runOnFunction()
// does a std::unique_ptr::reset anyways.
@@ -185,7 +185,7 @@ bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg,
LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR,
MCRegUnit RegUnit) {
- LiveIntervalUnion::Query &Q = Queries[RegUnit];
+ LiveIntervalUnion::Query &Q = Queries[static_cast<unsigned>(RegUnit)];
Q.init(UserTag, LR, Matrix[RegUnit]);
return Q;
}
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index 3e7052a9b6245..348ccd85f4c45 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -23,7 +23,7 @@ void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
for (MCRegUnit U : TRI->regunits()) {
for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) {
- Units.reset(U);
+ Units.reset(static_cast<unsigned>(U));
break;
}
}
@@ -34,7 +34,7 @@ void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
for (MCRegUnit U : TRI->regunits()) {
for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) {
- Units.set(U);
+ Units.set(static_cast<unsigned>(U));
break;
}
}
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 5ec7c48d7ee64..2a344b40c30c1 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -138,7 +138,7 @@ class CopyTracker {
for (unsigned SafeReg = 0, E = TRI.getNumRegs(); SafeReg < E; ++SafeReg)
if (!RegMaskOp.clobbersPhysReg(SafeReg))
for (MCRegUnit SafeUnit : TRI.regunits(SafeReg))
- PreservedRegUnits.set(SafeUnit);
+ PreservedRegUnits.set(static_cast<unsigned>(SafeUnit));
return PreservedRegUnits;
}
@@ -996,7 +996,7 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
// this register mask.
bool MIRefedinCopyInfo = false;
for (MCRegUnit RegUnit : TRI->regunits(Reg)) {
- if (!PreservedRegUnits.test(RegUnit))
+ if (!PreservedRegUnits.test(static_cast<unsigned>(RegUnit)))
Tracker.clobberRegUnit(RegUnit, *TRI, *TII, UseCopyInstr);
else {
if (MaybeDead == Tracker.findCopyForUnit(RegUnit, *TRI)) {
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp
index fa654f266c89a..3a212206ac4e6 100644
--- a/llvm/lib/CodeGen/MachineInstrBundle.cpp
+++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp
@@ -108,7 +108,7 @@ static bool containsReg(SmallSetVector<Register, 32> LocalDefsV,
const TargetRegisterInfo *TRI) {
if (Reg.isPhysical()) {
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
- if (!LocalDefsP[Unit])
+ if (!LocalDefsP[static_cast<unsigned>(Unit)])
return false;
return true;
@@ -189,7 +189,7 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
if (LocalDefs.insert(Reg)) {
if (!MO.isDead() && Reg.isPhysical()) {
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
- LocalDefsP.set(Unit);
+ LocalDefsP.set(static_cast<unsigned>(Unit));
}
} else {
if (!MO.isDead()) {
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index c169467384f8b..0a4b04d60aedc 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -492,7 +492,7 @@ static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
if (PhysReg && !((Word >> Bit) & 1)) {
for (MCRegUnit Unit : TRI.regunits(PhysReg))
- RUsFromRegsNotInMask.set(Unit);
+ RUsFromRegsNotInMask.set(static_cast<unsigned>(Unit));
}
}
}
@@ -541,7 +541,8 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
for (MCRegUnit Unit : TRI->regunits(Reg)) {
// If it's using a non-loop-invariant register, then it's obviously
// not safe to hoist.
- if (RUDefs.test(Unit) || RUClobbers.test(Unit)) {
+ if (RUDefs.test(static_cast<unsigned>(Unit)) ||
+ RUClobbers.test(static_cast<unsigned>(Unit))) {
HasNonInvariantUse = true;
break;
}
@@ -562,16 +563,16 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
// register, then this is not safe. Two defs is indicated by setting a
// PhysRegClobbers bit.
for (MCRegUnit Unit : TRI->regunits(Reg)) {
- if (RUDefs.test(Unit)) {
- RUClobbers.set(Unit);
+ if (RUDefs.test(static_cast<unsigned>(Unit))) {
+ RUClobbers.set(static_cast<unsigned>(Unit));
RuledOut = true;
- } else if (RUClobbers.test(Unit)) {
+ } else if (RUClobbers.test(static_cast<unsigned>(Unit))) {
// MI defined register is seen defined by another instruction in
// the loop, it cannot be a LICM candidate.
RuledOut = true;
}
- RUDefs.set(Unit);
+ RUDefs.set(static_cast<unsigned>(Unit));
}
}
@@ -612,7 +613,7 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
// be LICM'ed.
for (const auto &LI : BB->liveins()) {
for (MCRegUnit Unit : TRI->regunits(LI.PhysReg))
- RUDefs.set(Unit);
+ RUDefs.set(static_cast<unsigned>(Unit));
}
// Funclet entry blocks will clobber all registers
@@ -626,10 +627,10 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
if (MCRegister Reg = TLI.getExceptionPointerRegister(PersonalityFn))
for (MCRegUnit Unit : TRI->regunits(Reg))
- RUClobbers.set(Unit);
+ RUClobbers.set(static_cast<unsigned>(Unit));
if (MCRegister Reg = TLI.getExceptionSelectorRegister(PersonalityFn))
for (MCRegUnit Unit : TRI->regunits(Reg))
- RUClobbers.set(Unit);
+ RUClobbers.set(static_cast<unsigned>(Unit));
}
SpeculationState = SpeculateUnknown;
@@ -648,7 +649,7 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
if (!Reg)
continue;
for (MCRegUnit Unit : TRI->regunits(Reg))
- TermRUs.set(Unit);
+ TermRUs.set(static_cast<unsigned>(Unit));
}
}
@@ -668,7 +669,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
Register Def = Candidate.Def;
bool Safe = true;
for (MCRegUnit Unit : TRI->regunits(Def)) {
- if (RUClobbers.test(Unit) || TermRUs.test(Unit)) {
+ if (RUClobbers.test(static_cast<unsigned>(Unit)) ||
+ TermRUs.test(static_cast<unsigned>(Unit))) {
Safe = false;
break;
}
@@ -682,7 +684,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
if (!MO.getReg())
continue;
for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
- if (RUDefs.test(Unit) || RUClobbers.test(Unit)) {
+ if (RUDefs.test(static_cast<unsigned>(Unit)) ||
+ RUClobbers.test(static_cast<unsigned>(Unit))) {
// If it's using a non-loop-invariant register, then it's obviously
// not safe to hoist.
Safe = false;
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 0be75e073dedd..41efe622417c8 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1320,8 +1320,9 @@ void PEIImpl::insertZeroCallUsedRegs(MachineFunction &MF) {
continue;
// This picks up sibling registers (e.q. %al -> %ah).
+ // FIXME: Mixing physical registers and register units is likely a bug.
for (MCRegUnit Unit : TRI.regunits(Reg))
- RegsToZero.reset(Unit);
+ RegsToZero.reset(static_cast<unsigned>(Unit));
for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg))
RegsToZero.reset(SReg);
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index 07729ebec6e51..80fad722f592a 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -82,7 +82,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
if (!(MB[I / 32] & (1u << (I % 32))))
continue;
for (MCRegUnit Unit : TRI.regunits(MCRegister::from(I)))
- PU.set(Unit);
+ PU.set(static_cast<unsigned>(Unit));
}
MaskInfos[M].Units = PU.flip();
}
@@ -132,7 +132,7 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
for (MCRegUnitMaskIterator UM(RR.asMCReg(), &TRI); UM.isValid(); ++UM) {
auto [U, M] = *UM;
if ((M & RR.Mask).any())
- Units.insert(U);
+ Units.insert(static_cast<unsigned>(U));
}
return Units;
}
@@ -152,7 +152,7 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
unsigned T = llvm::countr_zero(C);
unsigned CR = 32 * I + T; // Clobbered reg
for (MCRegUnit U : TRI.regunits(CR))
- Units.insert(U);
+ Units.insert(static_cast<unsigned>(U));
C &= ~(1u << T);
}
}
@@ -269,7 +269,7 @@ void PhysicalRegisterInfo::print(raw_ostream &OS, RegisterRef A) const {
void PhysicalRegisterInfo::print(raw_ostream &OS, const RegisterAggr &A) const {
OS << '{';
for (unsigned U : A.units())
- OS << ' ' << printRegUnit(U, &TRI);
+ OS << ' ' << printRegUnit(static_cast<MCRegUnit>(U), &TRI);
OS << " }";
}
@@ -280,7 +280,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
auto [Unit, LaneMask] = *U;
if ((LaneMask & RR.Mask).any())
- if (Units.test(Unit))
+ if (Units.test(static_cast<unsigned>(Unit)))
return true;
}
return false;
@@ -295,7 +295,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
auto [Unit, LaneMask] = *U;
if ((LaneMask & RR.Mask).any())
- if (!Units.test(Unit))
+ if (!Units.test(static_cast<unsigned>(Unit)))
return false;
}
return true;
@@ -310,7 +310,7 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
auto [Unit, LaneMask] = *U;
if ((LaneMask & RR.Mask).any())
- Units.set(Unit);
+ Units.set(static_cast<unsigned>(Unit));
}
return *this;
}
@@ -361,13 +361,13 @@ RegisterRef RegisterAggr::makeRegRef() const {
// in this aggregate.
// Get all the registers aliased to the first unit in the bit vector.
- BitVector Regs = PRI.getUnitAliases(U);
+ BitVector Regs = PRI.getUnitAliases(static_cast<MCRegUnit>(U));
U = Units.find_next(U);
// For each other unit, intersect it with the set of all registers
// aliased that unit.
while (U >= 0) {
- Regs &= PRI.getUnitAliases(U);
+ Regs &= PRI.getUnitAliases(static_cast<MCRegUnit>(U));
U = Units.find_next(U);
}
@@ -382,7 +382,7 @@ RegisterRef RegisterAggr::makeRegRef() const {
LaneBitmask M;
for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
auto [Unit, LaneMask] = *I;
- if (Units.test(Unit))
+ if (Units.test(static_cast<unsigned>(Unit)))
M |= LaneMask;
}
return RegisterRef(F, M);
@@ -391,7 +391,7 @@ RegisterRef RegisterAggr::makeRegRef() const {
RegisterAggr::ref_iterator::ref_iterator(const RegisterAggr &RG, bool End)
: Owner(&RG) {
for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
- RegisterRef R = RG.PRI.getRefForUnit(U);
+ RegisterRef R = RG.PRI.getRefForUnit(static_cast<MCRegUnit>(U));
Masks[R.Id] |= R.Mask;
}
Pos = End ? Masks.end() : Masks.begin();
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index 61706e13b8e91..b12a5bc64ca0b 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -134,8 +134,8 @@ void ReachingDefInfo::enterBasicBlock(MachineBasicBlock *MBB) {
// Treat function live-ins as if they were defined just before the first
// instruction. Usually, function arguments are set up immediately
// before the call.
- if (LiveRegs[Unit] != -1) {
- LiveRegs[Unit] = -1;
+ if (LiveRegs[static_cast<unsigned>(Unit)] != -1) {
+ LiveRegs[static_cast<unsigned>(Unit)] = -1;
MBBReachingDefs.append(MBBNumber, Unit, -1);
}
}
@@ -162,7 +162,8 @@ void ReachingDefInfo::enterBasicBlock(MachineBasicBlock *MBB) {
// Insert the most recent reaching definition we found.
for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)
if (LiveRegs[Unit] != ReachingDefDefaultVal)
- MBBReachingDefs.append(MBBNumber, Unit, LiveRegs[Unit]);
+ MBBReachingDefs.append(MBBNumber, static_cast<MCRegUnit>(Unit),
+ LiveRegs[Unit]);
}
void ReachingDefInfo::leaveBasicBlock(MachineBasicBlock *MBB) {
@@ -205,8 +206,8 @@ void ReachingDefInfo::processDefs(MachineInstr *MI) {
<< *MI);
// How many instructions since this reg unit was last written?
- if (LiveRegs[Unit] != CurInstr) {
- LiveRegs[Unit] = CurInstr;
+ if (LiveRegs[static_cast<unsigned>(Unit)] != CurInstr) {
+ LiveRegs[static_cast<unsigned>(Unit)] = CurInstr;
MBBReachingDefs.append(MBBNumber, Unit, CurInstr);
}
}
@@ -240,16 +241,17 @@ void ReachingDefInfo::reprocessBasicBlock(MachineBasicBlock *MBB) {
if (Def == ReachingDefDefaultVal)
continue;
- auto Defs = MBBReachingDefs.defs(MBBNumber, Unit);
+ auto Defs = MBBReachingDefs.defs(MBBNumber, static_cast<MCRegUnit>(Unit));
if (!Defs.empty() && Defs.front() < 0) {
if (Defs.front() >= Def)
continue;
// Update existing reaching def from predecessor to a more recent one.
- MBBReachingDefs.replaceFront(MBBNumber, Unit, Def);
+ MBBReachingDefs.replaceFront(MBBNumber, static_cast<MCRegUnit>(Unit),
+ Def);
} else {
// Insert new reaching def from predecessor.
- MBBReachingDefs.prepend(MBBNumber, Unit, Def);
+ MBBReachingDefs.prepend(MBBNumber, static_cast<MCRegUnit>(Unit), Def);
}
// Update reaching def at end of BB. Keep in mind that these are
@@ -370,7 +372,8 @@ void ReachingDefInfo::traverse() {
MBBNumber != NumBlockIDs; ++MBBNumber) {
for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
int LastDef = ReachingDefDefaultVal;
- for (int Def : MBBReachingDefs.defs(MBBNumber, Unit)) {
+ for (int Def :
+ MBBReachingDefs.defs(MBBNumber, static_cast<MCRegUnit>(Unit))) {
assert(Def > LastDef && "Defs must be sorted and unique");
LastDef = Def;
}
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index d01f0d1f9de33..33e1d916a7d7a 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -284,7 +284,7 @@ class RegAllocFastImpl {
/// Mark a physreg as used in this instruction.
void markRegUsedInInstr(MCPhysReg PhysReg) {
for (MCRegUnit Unit : TRI->regunits(PhysReg))
- UsedInInstr[Unit] = InstrGen | 1;
+ UsedInInstr[static_cast<unsigned>(Unit)] = InstrGen | 1;
}
// Check if physreg is clobbered by instruction's regmask(s).
@@ -299,7 +299,8 @@ class RegAllocFastImpl {
if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
return true;
for (MCRegUnit Unit : TRI->regunits(PhysReg))
- if (UsedInInstr[Unit] >= (InstrGen | !LookAtPhysRegUses))
+ if (UsedInInstr[static_cast<unsigned>(Unit)] >=
+ (InstrGen | !LookAtPhysRegUses))
return true;
return false;
}
@@ -308,15 +309,16 @@ class RegAllocFastImpl {
/// This is only used by the special livethrough handling code.
void markPhysRegUsedInInstr(MCRegister PhysReg) {
for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
- assert(UsedInInstr[Unit] <= InstrGen && "non-phys use before phys use?");
- UsedInInstr[Unit] = InstrGen;
+ assert(UsedInInstr[static_cast<unsigned>(Unit)] <= InstrGen &&
+ "non-phys use before phys use?");
+ UsedInInstr[static_cast<unsigned>(Unit)] = InstrGen;
}
}
/// Remove mark of physical register being used in the instruction.
void unmarkRegUsedInInstr(MCRegister PhysReg) {
for (MCRegUnit Unit : TRI->regunits(PhysReg))
- UsedInInstr[Unit] = 0;
+ UsedInInstr[static_cast<unsigned>(Unit)] = 0;
}
enum : unsigned {
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 1bc7607890328..a059cb55371a3 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -590,7 +590,8 @@ bool RegAllocEvictionAdvisor::canReassign(const LiveInterval &VirtReg,
MCRegister FromReg) const {
auto HasRegUnitInterference = [&](MCRegUnit Unit) {
// Instantiate a "subquery", not to be confused with the Queries array.
- LiveIntervalUnion::Query SubQ(VirtReg, Matrix->getLiveUnions()[Unit]);
+ LiveIntervalUnion::Query SubQ(
+ VirtReg, Matrix->getLiveUnions()[static_cast<unsigned>(Unit)]);
return SubQ.checkInterference();
};
@@ -1681,7 +1682,7 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
// StartIdx and after StopIdx.
//
LiveIntervalUnion::SegmentIter IntI =
- Matrix->getLiveUnions()[Unit].find(StartIdx);
+ Matrix->getLiveUnions()[static_cast<unsigned>(Unit)].find(StartIdx);
for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
// Skip the gaps before IntI.
while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 8ead83302c337..bbeb7adae825c 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -85,7 +85,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf,
CalleeSavedAliases.assign(TRI->getNumRegUnits(), 0);
for (const MCPhysReg *I = CSR; *I; ++I) {
for (MCRegUnit U : TRI->regunits(*I))
- CalleeSavedAliases[U] = *I;
+ CalleeSavedAliases[static_cast<unsigned>(U)] = *I;
LastCalleeSavedRegs.push_back(*I);
}
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 975895809b9de..cffb3ed1b8779 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -137,13 +137,13 @@ Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
// Generic printout when TRI is missing.
if (!TRI) {
- OS << "Unit~" << Unit;
+ OS << "Unit~" << static_cast<unsigned>(Unit);
return;
}
// Check for invalid register units.
- if (Unit >= TRI->getNumRegUnits()) {
- OS << "BadUnit~" << Unit;
+ if (static_cast<unsigned>(Unit) >= TRI->getNumRegUnits()) {
+ OS << "BadUnit~" << static_cast<unsigned>(Unit);
return;
}
diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
index 6274cb4462192..6e0a0f6f1de93 100644
--- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp
+++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp
@@ -202,7 +202,8 @@ Register FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI) const {
MCRegUnitIterator I = Range.begin(), E = Range.end();
for (MCRegUnit S : TRI->regunits(SuperDestReg)) {
I = std::lower_bound(I, E, S);
- if ((I == E || *I > S) && LiveUnits.getBitVector().test(S)) {
+ if ((I == E || *I > S) &&
+ LiveUnits.getBitVector().test(static_cast<unsigned>(S))) {
SuperIsLive = true;
break;
}
More information about the llvm-commits
mailing list