[llvm] [ARM] TableGen-erate node descriptions (PR #168212)

[Sergei Barannikov via llvm-commits]

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@@ -6006,13 +6055,49 @@ foreach wb = [MVE_vldst24_writeback<
                      "vst" # n.nvecs # stage # "." # s.lanesize>;
 }
 
-def SDTARMVST2    : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
-                                         SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
-def SDTARMVST4    : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
-                                         SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
-                                         SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>;
-def MVEVST2UPD       : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain, SDNPMemOperand]>;
-def MVEVST4UPD       : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain, SDNPMemOperand]>;
+// Vector load N-element structure to all lanes
----------------
s-barannikov wrote:

It seems some of these nodes are sometimes created with and sometimes without the last operand.
I've reverted my attempt to add node descriptions for them and will let someone else try to do this

https://github.com/llvm/llvm-project/pull/168212