[clang] [llvm] [Hexagon] Enable soft bf16 in hexagon (PR #167922)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- clang/lib/Basic/Targets/Hexagon.cpp clang/lib/Basic/Targets/Hexagon.h llvm/lib/Target/Hexagon/HexagonISelLowering.cpp llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp llvm/lib/Target/Hexagon/HexagonSubtarget.h --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index bcc705c3f..63b7683d5 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -2365,16 +2365,21 @@ SDValue HexagonTargetLowering::LowerHvxFpExtend(SDValue Op,
   const SDLoc &dl(Op);
 
   if (ArgTy == MVT::v64bf16) {
-     MVT HalfTy = typeSplit(VecTy).first;
-     SDValue BF16Vec = Op.getOperand(0);
-     SDValue Zeroes = getInstr(Hexagon::V6_vxor, dl, HalfTy, {BF16Vec, BF16Vec}, DAG);
-     // Interleave zero vector with the bf16 vector, with zeroes in the lower half
-     // of each 32 bit lane, effectively extending the bf16 values to fp32 values.
-     SDValue ShuffVec = getInstr(Hexagon::V6_vshufoeh, dl, VecTy, {BF16Vec, Zeroes}, DAG);
-     VectorPair VecPair = opSplit(ShuffVec, dl, DAG);
-     SDValue Result = getInstr(Hexagon::V6_vshuffvdd, dl, VecTy,
-                  {VecPair.second, VecPair.first, DAG.getSignedConstant(-4, dl, MVT::i32)}, DAG);
-     return Result;
+    MVT HalfTy = typeSplit(VecTy).first;
+    SDValue BF16Vec = Op.getOperand(0);
+    SDValue Zeroes =
+        getInstr(Hexagon::V6_vxor, dl, HalfTy, {BF16Vec, BF16Vec}, DAG);
+    // Interleave zero vector with the bf16 vector, with zeroes in the lower
+    // half of each 32 bit lane, effectively extending the bf16 values to fp32
+    // values.
+    SDValue ShuffVec =
+        getInstr(Hexagon::V6_vshufoeh, dl, VecTy, {BF16Vec, Zeroes}, DAG);
+    VectorPair VecPair = opSplit(ShuffVec, dl, DAG);
+    SDValue Result = getInstr(Hexagon::V6_vshuffvdd, dl, VecTy,
+                              {VecPair.second, VecPair.first,
+                               DAG.getSignedConstant(-4, dl, MVT::i32)},
+                              DAG);
+    return Result;
   }
 
   assert(VecTy == MVT::v64f32 && ArgTy == MVT::v64f16);
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index 5cf0995c6..b2fc07ee1 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -343,7 +343,8 @@ public:
 
   ArrayRef<MVT> getHVXElementTypes() const {
     static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};
-    static MVT TypesV81[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::bf16, MVT::f32};
+    static MVT TypesV81[] = {MVT::i8,  MVT::i16,  MVT::i32,
+                             MVT::f16, MVT::bf16, MVT::f32};
 
     if (useHVXV81Ops() && useHVXFloatingPoint())
       return ArrayRef(TypesV81);

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https://github.com/llvm/llvm-project/pull/167922