[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)

[Ricardo Jesus via llvm-commits]

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@@ -962,6 +985,8 @@ def : InstRW<[WriteAdr, N3Write_2c_1L01_1V_1I], (instregex "^STP[SDQ](post|pre)$
 // ASIMD compare
 // ASIMD logical
 // ASIMD max/min, basic and pair-wise
+def : InstRW<[N3Write_0or2c_1V], (instregex "^ORRv16i8", "^ORRv8i8")>;
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rj-jesus wrote:

You could list the opcodes here without regex if you want.

https://github.com/llvm/llvm-project/pull/165690