[llvm] [RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (PR #168026)

[Kai Lin via llvm-commits]

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@@ -595,11 +383,12 @@ define <vscale x 4 x i32> @mismatched_extend_sub_add_commuted(<vscale x 4 x i16>
 ; FOLDING:       # %bb.0:
 ; FOLDING-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
 ; FOLDING-NEXT:    vzext.vf2 v10, v8
+; FOLDING-NEXT:    vsext.vf2 v12, v9
 ; FOLDING-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
-; FOLDING-NEXT:    vwsub.wv v12, v10, v9
-; FOLDING-NEXT:    vwadd.wv v10, v10, v9
+; FOLDING-NEXT:    vwsub.wv v10, v10, v9
+; FOLDING-NEXT:    vwaddu.wv v12, v12, v8
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OMG-link wrote:

The worklist inside `combineOp_VLToVWOp_VL` and the one in `DAGCombiner` are supposed to serve the same purpose. I need some time to understand why removing the worklist in `combineOp_VLToVWOp_VL` would cause your change to stop working. This should not happen.

https://github.com/llvm/llvm-project/pull/168026