[llvm] [AArch64] Consider COPY between disjoint register classes as expensive (PR #167661)

[Florian Hahn via llvm-commits]

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@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=early-machinelicm -o - %s | FileCheck %s
+
+# This test verifies that cross-register-class copies (e.g., between GPR and FPR)
+# are hoisted out of loops by MachineLICM, as they translate to expensive
+# instructions like FMOV (2-6 cycles) on AArch64.
+
+--- |
+  define void @cross_regclass_copy_hoisted() {
+    ret void
+  }
+...
+---
+name: cross_regclass_copy_hoisted
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: cross_regclass_copy_hoisted
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
+  ; CHECK-NEXT:   [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   FCMPSrr [[COPY]], [[FMOVS0_]], implicit-def $nzcv, implicit $fpcr
+  ; CHECK-NEXT:   Bcc 11, %bb.1, implicit $nzcv
+  ; CHECK-NEXT:   B %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   RET_ReallyLR
+  bb.0:
+    B %bb.1
+
+  bb.1:
+    ; High latency copy.
+    %0:gpr32 = MOVi32imm 2143289344
+    %1:fpr32 = COPY %0:gpr32
+    %2:fpr32 = FMOVS0
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fhahn wrote:

Could you also add a test for a physical register?

https://github.com/llvm/llvm-project/pull/167661