[llvm] [VE] Use MCRegister instead of unsigned. NFC (PR #167460)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 10 22:00:20 PST 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/167460
None
>From 33b4f711b024c9175f85e520adb6c4d0b8b330e5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 10 Nov 2025 21:35:43 -0800
Subject: [PATCH] [VE] Use MCRegister instead of unsigned. NFC
---
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp | 58 ++++++++++----------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 20f561a8dac34..46502716c6f20 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -54,7 +54,7 @@ class VEAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
- int parseRegisterName(MCRegister (*matchFn)(StringRef));
+ MCRegister parseRegisterName(MCRegister (*matchFn)(StringRef));
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -169,7 +169,7 @@ class VEOperand : public MCParsedAsmOperand {
};
struct RegOp {
- unsigned RegNum;
+ MCRegister RegNum;
};
struct ImmOp {
@@ -177,7 +177,7 @@ class VEOperand : public MCParsedAsmOperand {
};
struct MemOp {
- unsigned Base;
+ MCRegister Base;
unsigned IndexReg;
const MCExpr *Index;
const MCExpr *Offset;
@@ -350,14 +350,14 @@ class VEOperand : public MCParsedAsmOperand {
return Imm.Val;
}
- unsigned getMemBase() const {
+ MCRegister getMemBase() const {
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
Kind == k_MemoryRegImm) &&
"Invalid access!");
return Mem.Base;
}
- unsigned getMemIndexReg() const {
+ MCRegister getMemIndexReg() const {
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&
"Invalid access!");
return Mem.IndexReg;
@@ -415,20 +415,20 @@ class VEOperand : public MCParsedAsmOperand {
OS << "Token: " << getToken() << "\n";
break;
case k_Register:
- OS << "Reg: #" << getReg() << "\n";
+ OS << "Reg: #" << getReg().id() << "\n";
break;
case k_Immediate:
OS << "Imm: " << getImm() << "\n";
break;
case k_MemoryRegRegImm:
assert(getMemOffset() != nullptr);
- OS << "Mem: #" << getMemBase() << "+#" << getMemIndexReg() << "+";
+ OS << "Mem: #" << getMemBase().id() << "+#" << getMemIndexReg().id() << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
case k_MemoryRegImmImm:
assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
- OS << "Mem: #" << getMemBase() << "+";
+ OS << "Mem: #" << getMemBase().id() << "+";
MAI.printExpr(OS, *getMemIndex());
OS << "+";
MAI.printExpr(OS, *getMemOffset());
@@ -436,7 +436,7 @@ class VEOperand : public MCParsedAsmOperand {
break;
case k_MemoryZeroRegImm:
assert(getMemOffset() != nullptr);
- OS << "Mem: 0+#" << getMemIndexReg() << "+";
+ OS << "Mem: 0+#" << getMemIndexReg().id() << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
@@ -450,7 +450,7 @@ class VEOperand : public MCParsedAsmOperand {
break;
case k_MemoryRegImm:
assert(getMemOffset() != nullptr);
- OS << "Mem: #" << getMemBase() << "+";
+ OS << "Mem: #" << getMemBase().id() << "+";
MAI.printExpr(OS, *getMemOffset());
OS << "\n";
break;
@@ -606,7 +606,7 @@ class VEOperand : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S,
+ static std::unique_ptr<VEOperand> CreateReg(MCRegister RegNum, SMLoc S,
SMLoc E) {
auto Op = std::make_unique<VEOperand>(k_Register);
Op->Reg.RegNum = RegNum;
@@ -653,7 +653,7 @@ class VEOperand : public MCParsedAsmOperand {
}
static bool MorphToI32Reg(VEOperand &Op) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx > 63)
return false;
@@ -662,7 +662,7 @@ class VEOperand : public MCParsedAsmOperand {
}
static bool MorphToF32Reg(VEOperand &Op) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx > 63)
return false;
@@ -671,7 +671,7 @@ class VEOperand : public MCParsedAsmOperand {
}
static bool MorphToF128Reg(VEOperand &Op) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::SX0;
if (regIdx % 2 || regIdx > 63)
return false;
@@ -680,7 +680,7 @@ class VEOperand : public MCParsedAsmOperand {
}
static bool MorphToVM512Reg(VEOperand &Op) {
- unsigned Reg = Op.getReg();
+ MCRegister Reg = Op.getReg();
unsigned regIdx = Reg - VE::VM0;
if (regIdx % 2 || regIdx > 15)
return false;
@@ -701,11 +701,11 @@ class VEOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<VEOperand>
- MorphToMEMri(unsigned Base, std::unique_ptr<VEOperand> Op) {
+ MorphToMEMri(MCRegister Base, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegImm;
Op->Mem.Base = Base;
- Op->Mem.IndexReg = 0;
+ Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
return Op;
@@ -715,15 +715,15 @@ class VEOperand : public MCParsedAsmOperand {
MorphToMEMzi(std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroImm;
- Op->Mem.Base = 0;
- Op->Mem.IndexReg = 0;
+ Op->Mem.Base = MCRegister();
+ Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
return Op;
}
static std::unique_ptr<VEOperand>
- MorphToMEMrri(unsigned Base, unsigned Index, std::unique_ptr<VEOperand> Op) {
+ MorphToMEMrri(MCRegister Base, MCRegister Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegRegImm;
Op->Mem.Base = Base;
@@ -734,22 +734,22 @@ class VEOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<VEOperand>
- MorphToMEMrii(unsigned Base, const MCExpr *Index,
+ MorphToMEMrii(MCRegister Base, const MCExpr *Index,
std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryRegImmImm;
Op->Mem.Base = Base;
- Op->Mem.IndexReg = 0;
+ Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = Index;
Op->Mem.Offset = Imm;
return Op;
}
static std::unique_ptr<VEOperand>
- MorphToMEMzri(unsigned Index, std::unique_ptr<VEOperand> Op) {
+ MorphToMEMzri(MCRegister Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroRegImm;
- Op->Mem.Base = 0;
+ Op->Mem.Base = MCRegister();
Op->Mem.IndexReg = Index;
Op->Mem.Index = nullptr;
Op->Mem.Offset = Imm;
@@ -760,8 +760,8 @@ class VEOperand : public MCParsedAsmOperand {
MorphToMEMzii(const MCExpr *Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
Op->Kind = k_MemoryZeroImmImm;
- Op->Mem.Base = 0;
- Op->Mem.IndexReg = 0;
+ Op->Mem.Base = MCRegister();
+ Op->Mem.IndexReg = MCRegister();
Op->Mem.Index = Index;
Op->Mem.Offset = Imm;
return Op;
@@ -815,14 +815,14 @@ bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
/// Parses a register name using a given matching function.
/// Checks for lowercase or uppercase if necessary.
-int VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
+MCRegister VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
StringRef Name = Parser.getTok().getString();
- int RegNum = matchFn(Name);
+ MCRegister RegNum = matchFn(Name);
// GCC supports case insensitive register names. All of the VE registers
// are all lower case.
- if (RegNum == VE::NoRegister) {
+ if (!RegNum) {
RegNum = matchFn(Name.lower());
}
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