[llvm] [X86] Don't rely on global contraction flag (PR #167252)
Mikołaj Piróg via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 12 06:20:28 PST 2025
https://github.com/mikolaj-pirog updated https://github.com/llvm/llvm-project/pull/167252
>From b8dcc4469af1087c9630f8f07edbdc2b7826706d Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Sun, 9 Nov 2025 22:16:36 +0100
Subject: [PATCH 1/7] Make X86 backend not rely on global contract flag
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a854a0bf3fa..68dca58287c59 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8434,7 +8434,6 @@ static bool isFMAddSubOrFMSubAdd(const X86Subtarget &Subtarget,
// or MUL + ADDSUB to FMADDSUB.
const TargetOptions &Options = DAG.getTarget().Options;
bool AllowFusion =
- Options.AllowFPOpFusion == FPOpFusion::Fast ||
(AllowSubAddOrAddSubContract && Opnd0->getFlags().hasAllowContract());
if (!AllowFusion)
return false;
@@ -54160,11 +54159,7 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
// FADD(A, FMA(B, C, 0)) and FADD(A, FMUL(B, C)) to FMA(B, C, A)
static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
- auto AllowContract = [&DAG](const SDNodeFlags &Flags) {
- return DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
- Flags.hasAllowContract();
- };
-
+ bool AllowContract = N->getFlags().hasAllowContract();
auto HasNoSignedZero = [&DAG](const SDNodeFlags &Flags) {
return DAG.getTarget().Options.NoSignedZerosFPMath ||
Flags.hasNoSignedZeros();
@@ -54177,7 +54172,7 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
};
if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() ||
- !AllowContract(N->getFlags()))
+ !AllowContract)
return SDValue();
EVT VT = N->getValueType(0);
@@ -54188,14 +54183,14 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
SDValue RHS = N->getOperand(1);
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, &AllowContract,
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, AllowContract,
&IsVectorAllNegativeZero,
&HasNoSignedZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
SDValue Op0 = N.getOperand(0);
unsigned Opcode = Op0.getOpcode();
- if (Op0.hasOneUse() && AllowContract(Op0->getFlags())) {
+ if (Op0.hasOneUse() && AllowContract) {
if ((Opcode == X86ISD::VFMULC || Opcode == X86ISD::VFCMULC)) {
MulOp0 = Op0.getOperand(0);
MulOp1 = Op0.getOperand(1);
>From 591d77e829489fb2d7b812b2d9220219acace3d8 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Sun, 9 Nov 2025 22:37:49 +0100
Subject: [PATCH 2/7] Formatting
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 68dca58287c59..bb86efca73deb 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54171,8 +54171,7 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
Bits.getConstant() == AI;
};
- if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() ||
- !AllowContract)
+ if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() || !AllowContract)
return SDValue();
EVT VT = N->getValueType(0);
>From 22798038a35a1f73d5c21733c861d662ced4f532 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Sun, 9 Nov 2025 23:04:42 +0100
Subject: [PATCH 3/7] remove unused
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bb86efca73deb..95bb1df164fef 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8432,7 +8432,6 @@ static bool isFMAddSubOrFMSubAdd(const X86Subtarget &Subtarget,
// DAGCombiner::visitFADDForFMACombine. It would be good to have one
// function that would answer if it is Ok to fuse MUL + ADD to FMADD
// or MUL + ADDSUB to FMADDSUB.
- const TargetOptions &Options = DAG.getTarget().Options;
bool AllowFusion =
(AllowSubAddOrAddSubContract && Opnd0->getFlags().hasAllowContract());
if (!AllowFusion)
>From 22ff3fd5d15886344424939142e1310c451346b3 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 10 Nov 2025 13:01:30 +0100
Subject: [PATCH 4/7] Reviewer suggestions
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 95bb1df164fef..f2a77b7cbc8fd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54158,7 +54158,6 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
// FADD(A, FMA(B, C, 0)) and FADD(A, FMUL(B, C)) to FMA(B, C, A)
static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
- bool AllowContract = N->getFlags().hasAllowContract();
auto HasNoSignedZero = [&DAG](const SDNodeFlags &Flags) {
return DAG.getTarget().Options.NoSignedZerosFPMath ||
Flags.hasNoSignedZeros();
@@ -54170,7 +54169,7 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
Bits.getConstant() == AI;
};
- if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() || !AllowContract)
+ if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() || !N->getFlags().hasAllowContract())
return SDValue();
EVT VT = N->getValueType(0);
@@ -54181,14 +54180,14 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
SDValue RHS = N->getOperand(1);
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, AllowContract,
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj,
&IsVectorAllNegativeZero,
&HasNoSignedZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
SDValue Op0 = N.getOperand(0);
unsigned Opcode = Op0.getOpcode();
- if (Op0.hasOneUse() && AllowContract) {
+ if (Op0.hasOneUse() && Op0->getFlags().hasAllowContract()) {
if ((Opcode == X86ISD::VFMULC || Opcode == X86ISD::VFCMULC)) {
MulOp0 = Op0.getOperand(0);
MulOp1 = Op0.getOperand(1);
>From c8ce070109c94fbca94104709ccf82f7df44938a Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 10 Nov 2025 13:08:45 +0100
Subject: [PATCH 5/7] Formatting
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f2a77b7cbc8fd..2ecb0e951e0dd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54169,7 +54169,8 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
Bits.getConstant() == AI;
};
- if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() || !N->getFlags().hasAllowContract())
+ if (N->getOpcode() != ISD::FADD || !Subtarget.hasFP16() ||
+ !N->getFlags().hasAllowContract())
return SDValue();
EVT VT = N->getValueType(0);
@@ -54180,8 +54181,7 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG,
SDValue RHS = N->getOperand(1);
bool IsConj;
SDValue FAddOp1, MulOp0, MulOp1;
- auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj,
- &IsVectorAllNegativeZero,
+ auto GetCFmulFrom = [&MulOp0, &MulOp1, &IsConj, &IsVectorAllNegativeZero,
&HasNoSignedZero](SDValue N) -> bool {
if (!N.hasOneUse() || N.getOpcode() != ISD::BITCAST)
return false;
>From cef9fa06466668d700403d6daf0f14213e5a2f23 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 12 Nov 2025 14:35:23 +0100
Subject: [PATCH 6/7] Add warning on using fp-contract on x86
---
llvm/tools/llc/llc.cpp | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp
index dc2f878830863..92906b44e0818 100644
--- a/llvm/tools/llc/llc.cpp
+++ b/llvm/tools/llc/llc.cpp
@@ -604,6 +604,12 @@ static int compileModule(char **argv, LLVMContext &Context,
InputFilename);
}
+ if (TheTriple.isX86() &&
+ codegen::getFuseFPOps() != FPOpFusion::FPOpFusionMode::Standard)
+ WithColor::warning(errs(), argv[0])
+ << "X86 backend ignores --fp-contract setting; use IR fast-math "
+ "flags instead.";
+
Options.BinutilsVersion =
TargetMachine::parseBinutilsVersion(BinutilsVersion);
Options.MCOptions.ShowMCEncoding = ShowMCEncoding;
>From 52fd57bbf4107f152ea9e9a746913a0ea74441e3 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 12 Nov 2025 15:20:12 +0100
Subject: [PATCH 7/7] Add test, fix last test using fp-contract=fast
---
.../CodeGen/X86/llc-fp-contract-warning.ll | 12 ++++++
llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 40 ++++++++++---------
2 files changed, 33 insertions(+), 19 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/llc-fp-contract-warning.ll
diff --git a/llvm/test/CodeGen/X86/llc-fp-contract-warning.ll b/llvm/test/CodeGen/X86/llc-fp-contract-warning.ll
new file mode 100644
index 0000000000000..2802593c733e0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/llc-fp-contract-warning.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=fast 2>&1 | grep "X86 backend ignores --fp-contract"
+
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=off 2>&1 | grep "X86 backend ignores --fp-contract"
+
+; on, as a default setting that's passed to backend when no --fp-contract option is specified, is not diagnosed.
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=on 2>&1 | grep -v "X86 backend ignores --fp-contract"
+
+define float @foo(float %f) {
+ %res = fadd float %f, %f
+ ret float %res
+}
+
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
index 18588aada145c..085d463ce07eb 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -fp-contract=fast < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
declare float @llvm.sqrt.f32(float) #2
@@ -24,17 +24,17 @@ define float @sqrt_ieee_ninf(float %f) #0 {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[VRSQRTSSr:%[0-9]+]]:fr32 = ninf afn VRSQRTSSr killed [[DEF]], [[COPY]]
- ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VRSQRTSSr:%[0-9]+]]:fr32 = ninf contract afn VRSQRTSSr killed [[DEF]], [[COPY]]
+ ; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
- ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
+ ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf contract afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY]]
; CHECK-NEXT: [[VPBROADCASTDrm:%[0-9]+]]:vr128 = VPBROADCASTDrm $rip, 1, $noreg, %const.2, $noreg :: (load (s32) from constant-pool)
@@ -46,7 +46,7 @@ define float @sqrt_ieee_ninf(float %f) #0 {
; CHECK-NEXT: [[COPY5:%[0-9]+]]:fr32 = COPY killed [[VPANDNrr]]
; CHECK-NEXT: $xmm0 = COPY [[COPY5]]
; CHECK-NEXT: RET 0, $xmm0
- %call = tail call ninf afn float @llvm.sqrt.f32(float %f)
+ %call = tail call ninf afn contract float @llvm.sqrt.f32(float %f)
ret float %call
}
@@ -73,16 +73,18 @@ define float @sqrt_daz_ninf(float %f) #1 {
; CHECK-NEXT: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
; CHECK-NEXT: [[VRSQRTSSr:%[0-9]+]]:fr32 = ninf afn VRSQRTSSr killed [[DEF]], [[COPY]]
; CHECK-NEXT: [[VMULSSrr:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VFMADD213SSr:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed [[VMULSSrr]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VADDSSrr:%[0-9]+]]:fr32 = ninf afn nofpexcept VADDSSrr killed [[VMULSSrr1]], [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK-NEXT: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load (s32) from constant-pool)
- ; CHECK-NEXT: [[VMULSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr1]], killed [[VFMADD213SSr]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr2]], implicit $mxcsr
- ; CHECK-NEXT: [[VFMADD213SSr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VFMADD213SSr [[VMULSSrr2]], [[VMULSSrr3]], [[VMOVSSrm_alt]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr3]], [[VMOVSSrm_alt1]], implicit $mxcsr
- ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr4]], killed [[VFMADD213SSr1]], implicit $mxcsr
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr5]]
+ ; CHECK-NEXT: [[VMULSSrr2:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr3:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr2]], killed [[VADDSSrr]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr4:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[COPY]], [[VMULSSrr3]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr5:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr4]], [[VMULSSrr3]], implicit $mxcsr
+ ; CHECK-NEXT: [[VADDSSrr1:%[0-9]+]]:fr32 = ninf afn nofpexcept VADDSSrr killed [[VMULSSrr5]], [[VMOVSSrm_alt]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr6:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr [[VMULSSrr4]], [[VMOVSSrm_alt1]], implicit $mxcsr
+ ; CHECK-NEXT: [[VMULSSrr7:%[0-9]+]]:fr32 = ninf afn nofpexcept VMULSSrr killed [[VMULSSrr6]], killed [[VADDSSrr1]], implicit $mxcsr
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY killed [[VMULSSrr7]]
; CHECK-NEXT: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
; CHECK-NEXT: [[VCMPSSrri:%[0-9]+]]:fr32 = nofpexcept VCMPSSrri [[COPY]], killed [[FsFLD0SS]], 0, implicit $mxcsr
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY killed [[VCMPSSrri]]
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