[llvm] AArch64: align pair-wise spills on WoS to 16-byte (PR #166902)

[Benjamin Maxwell via llvm-commits]

================
@@ -1688,6 +1703,21 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
   }
 
   bool FPAfterSVECalleeSaves = IsWindows && AFI->getSVECalleeSavedStackSize();
+  // Windows AAPCS has x9-x15 as volatile registers, x16-x17 as intra-procedural
+  // scratch, x18 as platform reserved. However, clang has extended calling
+  // convensions such as preserve_most and preserve_all which treat these as
+  // CSR. As such, the ARM64 unwind uOPs bias registers by 19. We use ARM64EC
+  // uOPs which have separate restrictions. We need to check for that.
+  //
+  // FIXME: we currently do not account for the D registers as the current LLVM
+  // support does not support spiling the D registers.
----------------
MacDue wrote:

Could you clarify this FIXME? Is this referring to the current ARM64EC support? As Spilling D-registers is supported generally. 

https://github.com/llvm/llvm-project/pull/166902