[llvm] [AArch64] Follow-up from #166926 (PR #167480)

[Sander de Smalen via llvm-commits]

================
@@ -1168,26 +1171,33 @@ bool AArch64RegisterInfo::getRegAllocationHints(
           TII->get(AArch64::getSVEPseudoMap(Def.getOpcode())).TSFlags;
 
       for (MCPhysReg R : Order) {
-        auto AddHintIfSuitable = [&](MCPhysReg R, const MachineOperand &MO) {
-          // R is a suitable register hint if there exists an operand for the
-          // instruction that is not yet allocated a register or if R matches
-          // one of the other source operands.
-          if (!VRM->hasPhys(MO.getReg()) || VRM->getPhys(MO.getReg()) == R)
+        auto AddHintIfSuitable = [&](MCPhysReg R,
+                                     const MachineOperand &MO) -> bool {
+          // R is a suitable register hint if:
+          // * R is one of the source operands.
+          // * The register allocator has not suggested any hints and one of the
+          //   instruction's source operands does not yet have a register
+          //   allocated for it.
+          if (VRM->getPhys(MO.getReg()) == R ||
+              (!VRM->hasPhys(MO.getReg()) && Hints.empty())) {
             Hints.push_back(R);
+            return true;
+          }
+          return false;
         };
 
         switch (InstFlags & AArch64::DestructiveInstTypeMask) {
         default:
           break;
         case AArch64::DestructiveTernaryCommWithRev:
-          AddHintIfSuitable(R, Def.getOperand(2));
-          AddHintIfSuitable(R, Def.getOperand(3));
-          AddHintIfSuitable(R, Def.getOperand(4));
+          AddHintIfSuitable(R, Def.getOperand(2)) ||
+              AddHintIfSuitable(R, Def.getOperand(3)) ||
+              AddHintIfSuitable(R, Def.getOperand(4));
----------------
sdesmalen-arm wrote:

This change is trying to avoid for e.g. `R = z0` adding `[z0, z0, z0]` to the list if operands 2, 3 and 4 are equal to `z0`.

It could indeed still add a duplicate hint if the same hint was added by `TargetRegisterInfo::getRegAllocationHints`, but I don't believe that's an issue. Do you?

https://github.com/llvm/llvm-project/pull/167480