[llvm] [AMDGPU] Verify dominance when rewriting spills to registers (PR #167347)

[Jay Foad via llvm-commits]

jayfoad wrote:

> When performing spill elimination in the AGPR copy rewrite pass it was possible to see spill reloads that were not dominated by any store. This caused invalid MIR to be generated where vreg uses were not dominated by defs.

I would guess that the condition you're checking for here is too strong. The MIR is not in SSA form and it's not necessary that every reload is dominated by a single spill, just that all spills together jointly dominate it. But maybe that's a harder condition to check.

https://github.com/llvm/llvm-project/pull/167347