[llvm] [AMDGPU] Analyze REG_SEQUENCE To Remove Redundant CMP Instructions (PR #167364)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+define amdgpu_ps i64 @ordertest(i64 inreg %val0) {
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arsenm wrote:

What does the MIR look like at this point? 

https://github.com/llvm/llvm-project/pull/167364