[llvm] [DAG] Fold (umin (sub a b) a) -> (usubo a b); (select usubo.1 a usubo.0) (PR #161651)

[Matt Arsenault via llvm-commits]

================
@@ -6219,6 +6219,24 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
                                         SDLoc(N), VT, N0, N1))
     return SD;
 
+  if (TLI.isOperationLegalOrCustom(ISD::USUBO, VT)) {
----------------
arsenm wrote:

```suggestion
  if (TLI.isOperationLegalOrCustom(ISD::USUBO, VT) &&
     !TLI.isOperationLegalOrCustom(ISD::UMIN, VT)) {
```

For AMDGPU there is legal min so it's better to leave that unbroken. Introducing the condition registers is a minor loss 

https://github.com/llvm/llvm-project/pull/161651