[llvm] [WIP][RISCV] tt-ascalon-d8 vector scheduling (PR #167066)

[Min-Yih Hsu via llvm-commits]

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@@ -316,10 +388,244 @@ def : ReadAdvance<ReadSHXADD32, 0>;
 def : ReadAdvance<ReadSingleBit, 0>;
 def : ReadAdvance<ReadSingleBitImm, 0>;
 
+//===----------------------------------------------------------------------===//
+// Vector
+
+// Configuration-Setting Instructions
+let Latency = 1 in {
+def : WriteRes<WriteVSETVLI, [AscalonV]>;
+def : WriteRes<WriteVSETIVLI, [AscalonV]>;
+}
+let Latency = 2 in {
+def : WriteRes<WriteVSETVL, [AscalonV]>;
+}
+
+// Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+  defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+  defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+  let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
----------------
mshockwave wrote:

just realized this is an out-of-order core: AcquireAtCycles is only _meaningfully_ used by in-order scheduling in MachineScheduler. When doing in-order scheduling, MachineScheduler maintains a virtual timeline for each resource to keep track of their reservation / consumption -- e.g. resource X is reserved from cycle A to cycle B -- "A" and "B" in this case are AcquireAtCycle and ReleaseAtCycles, respectively. MachineScheduler doesn't do that for out-of-order cores, in which case they only care about the _quantity_ of occupancy, namely, `(ReleaseAtCycles - AcquireAtCycles)`. In other words, writing
```
AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles]
```
for out-of-order cores has the same effect as writing
```
ReleaseAtCycles = [1, !sub(Cycles, 1)]
```
w.r.t MachineScheduler.

https://github.com/llvm/llvm-project/pull/167066