[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Brox Chen via llvm-commits]

================
@@ -730,14 +730,11 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
     }
   }
 
-  // Rework once the VS_16 register class is updated to include proper
-  // 16-bit SGPRs instead of 32-bit ones.
-  if (Old.getSubReg() == AMDGPU::lo16 && TRI->isSGPRReg(*MRI, New->getReg()))
-    Old.setSubReg(AMDGPU::NoSubRegister);
----------------
broxigarchen wrote:

I believe this is to handle case like:
```
%1:vgpr32 = COPY %0:sreg32
%3:vgpr16 = inst_true16 %1.lo16:vgpr32
```
fold to
```
%3:vgpr16 = inst_true16 %0:sreg32
```
since inst_true16 can take both vgpr16 or sreg32 for 16bit operands.

However I run a quick test and seems the this case is not added to the FoldCandidate and thus not triggered. Maybe we should fix this? @Sisyph to help commenting on this

https://github.com/llvm/llvm-project/pull/151033