[llvm] [AMDGPU] Convert flat scratch SS->SV in FI elimination (PR #166979)
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 10 03:37:01 PST 2025
================
@@ -2981,8 +2981,42 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
: RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
MI, false, 0, !UseSGPR);
- // TODO: for flat scratch another attempt can be made with a VGPR index
- // if no SGPRs can be scavenged.
+ // Fallback: If we need an SGPR but cannot scavenge one and there is no
+ // frame register, try to convert the flat-scratch instruction to use a
+ // VGPR index (SS -> SV) and materialize the offset in a VGPR.
+ if (!TmpSReg && !FrameReg && TII->isFLATScratch(*MI)) {
+ // Reuse an existing VGPR temp if available, otherwise scavenge one.
+ Register VTmp = (!UseSGPR && TmpReg)
+ ? TmpReg
+ : RS->scavengeRegisterBackwards(
+ AMDGPU::VGPR_32RegClass, MI, false, 0);
+ if (VTmp) {
+ // Put the large offset into a VGPR and zero the immediate offset.
+ BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), VTmp)
+ .addImm(Offset);
+
+ unsigned Opc = MI->getOpcode();
+ int NewOpc = AMDGPU::getFlatScratchInstSVfromSS(Opc);
+ if (NewOpc != -1) {
+ int OldSAddrIdx =
+ AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
+ int NewVAddrIdx =
+ AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vaddr);
+ if (OldSAddrIdx == NewVAddrIdx && OldSAddrIdx >= 0) {
----------------
rovka wrote:
Should this be an assert instead?
https://github.com/llvm/llvm-project/pull/166979
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