[llvm] [TableGen] Use "using" instead of "typedef" (NFC) (PR #167168)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 8 11:00:02 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tablegen
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
Identified with modernize-use-using.
---
Patch is 26.10 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/167168.diff
23 Files Affected:
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+5-5)
- (modified) llvm/utils/TableGen/AsmWriterEmitter.cpp (+3-3)
- (modified) llvm/utils/TableGen/Basic/SequenceToOffsetTable.h (+2-2)
- (modified) llvm/utils/TableGen/CodeGenMapTable.cpp (+3-3)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (+3-3)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.h (+3-3)
- (modified) llvm/utils/TableGen/Common/CodeGenHwModes.h (+1-1)
- (modified) llvm/utils/TableGen/Common/CodeGenInstruction.h (+2-2)
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+3-4)
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+13-14)
- (modified) llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h (+5-5)
- (modified) llvm/utils/TableGen/Common/InfoByHwMode.cpp (+1-1)
- (modified) llvm/utils/TableGen/Common/InfoByHwMode.h (+4-4)
- (modified) llvm/utils/TableGen/FastISelEmitter.cpp (+7-7)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+3-3)
- (modified) llvm/utils/TableGen/OptionParserEmitter.cpp (+4-4)
- (modified) llvm/utils/TableGen/RegisterBankEmitter.cpp (+1-1)
- (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+5-5)
- (modified) llvm/utils/TableGen/SearchableTableEmitter.cpp (+1-1)
- (modified) llvm/utils/TableGen/X86DisassemblerTables.cpp (+2-2)
- (modified) llvm/utils/TableGen/X86DisassemblerTables.h (+1-1)
- (modified) llvm/utils/TableGen/X86FoldTablesEmitter.cpp (+2-3)
- (modified) llvm/utils/TableGen/X86InstrMappingEmitter.cpp (+4-4)
``````````diff
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 9f18a11c236c0..63c9c3bfff169 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -141,7 +141,7 @@ class AsmMatcherInfo;
// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
// can even affect compiler output (at least seen in diagnostics produced when
// all matches fail). So we use a type that sorts them consistently.
-typedef std::set<const Record *, LessRecordByID> RegisterSet;
+using RegisterSet = std::set<const Record *, LessRecordByID>;
class AsmMatcherEmitter {
const RecordKeeper &Records;
@@ -779,8 +779,8 @@ class AsmMatcherInfo {
std::vector<OperandMatchEntry> OperandMatchInfo;
/// Map of Register records to their class information.
- typedef std::map<const Record *, ClassInfo *, LessRecordByID>
- RegisterClassesTy;
+ using RegisterClassesTy =
+ std::map<const Record *, ClassInfo *, LessRecordByID>;
RegisterClassesTy RegisterClasses;
/// Map of Predicate records to their subtarget information.
@@ -1275,7 +1275,7 @@ void AsmMatcherInfo::buildRegisterClasses(
const auto &Registers = Target.getRegBank().getRegisters();
auto &RegClassList = Target.getRegBank().getRegClasses();
- typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
+ using RegisterSetSet = std::set<RegisterSet, LessRegisterSet>;
// The register sets used for matching.
RegisterSetSet RegisterSets;
@@ -1515,7 +1515,7 @@ AsmMatcherInfo::AsmMatcherInfo(const Record *asmParser,
void AsmMatcherInfo::buildOperandMatchInfo() {
/// Map containing a mask with all operands indices that can be found for
/// that class inside a instruction.
- typedef std::map<ClassInfo *, unsigned, deref<std::less<>>> OpClassMaskTy;
+ using OpClassMaskTy = std::map<ClassInfo *, unsigned, deref<std::less<>>>;
OpClassMaskTy OpClassMask;
bool CallCustomParserForAllOperands =
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index c8c6c23bea014..8901ecb7210a7 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -814,7 +814,7 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
namespace {
struct AliasPriorityComparator {
- typedef std::pair<CodeGenInstAlias, int> ValueType;
+ using ValueType = std::pair<CodeGenInstAlias, int>;
bool operator()(const ValueType &LHS, const ValueType &RHS) const {
if (LHS.second == RHS.second) {
// We don't actually care about the order, but for consistency it
@@ -845,8 +845,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
// Create a map from the qualified name to a list of potential matches.
- typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
- AliasWithPriority;
+ using AliasWithPriority =
+ std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>;
std::map<std::string, AliasWithPriority> AliasMap;
for (const Record *R : Records.getAllDerivedDefinitions("InstAlias")) {
int Priority = R->getValueAsInt("EmitPriority");
diff --git a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
index 8da6fbef0672e..761ef1fcf12fe 100644
--- a/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
+++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
@@ -44,7 +44,7 @@ inline void printChar(raw_ostream &OS, char C) {
/// @tparam Less A stable comparator for SeqT elements.
template <typename SeqT, typename Less = std::less<typename SeqT::value_type>>
class SequenceToOffsetTable {
- typedef typename SeqT::value_type ElemT;
+ using ElemT = typename SeqT::value_type;
// Define a comparator for SeqT that sorts a suffix immediately before a
// sequence with that suffix.
@@ -58,7 +58,7 @@ class SequenceToOffsetTable {
// Keep sequences ordered according to SeqLess so suffixes are easy to find.
// Map each sequence to its offset in the table.
- typedef std::map<SeqT, unsigned, SeqLess> SeqMap;
+ using SeqMap = std::map<SeqT, unsigned, SeqLess>;
// Sequences added so far, with suffixes removed.
SeqMap Seqs;
diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp
index 90f0a2ac8c268..e5025784d304d 100644
--- a/llvm/utils/TableGen/CodeGenMapTable.cpp
+++ b/llvm/utils/TableGen/CodeGenMapTable.cpp
@@ -84,9 +84,9 @@
#include "llvm/TableGen/Record.h"
using namespace llvm;
-typedef std::map<std::string, std::vector<const Record *>> InstrRelMapTy;
-typedef std::map<std::vector<const Init *>, std::vector<const Record *>>
- RowInstrMapTy;
+using InstrRelMapTy = std::map<std::string, std::vector<const Record *>>;
+using RowInstrMapTy =
+ std::map<std::vector<const Init *>, std::vector<const Record *>>;
namespace {
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 8076ce2486f56..34355d5d6b743 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -776,7 +776,7 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) {
if (B.empty())
Changed |= EnforceAny(B);
- typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet;
+ using TypeSizeSet = SmallSet<TypeSize, 2, TypeSizeComparator>;
auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool {
return !Sizes.contains(T.getSizeInBits());
@@ -4129,7 +4129,7 @@ void CodeGenDAGPatterns::ParseInstructions() {
}
}
-typedef std::pair<TreePatternNode *, unsigned> NameRecord;
+using NameRecord = std::pair<TreePatternNode *, unsigned>;
static void FindNames(TreePatternNode &P,
std::map<StringRef, NameRecord> &Names,
@@ -4590,7 +4590,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
}
/// Dependent variable map for CodeGenDAGPattern variant generation
-typedef StringMap<int> DepVarMap;
+using DepVarMap = StringMap<int>;
static void FindDepVarsOf(TreePatternNode &N, DepVarMap &DepMap) {
if (N.isLeaf()) {
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 2ed8d1376b045..aa9a0a442424d 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -349,7 +349,7 @@ struct TypeInfer {
};
/// Set type used to track multiply used variables in patterns
-typedef StringSet<> MultipleUseVarSet;
+using MultipleUseVarSet = StringSet<>;
/// SDTypeConstraint - This is a discriminated union of constraints,
/// corresponding to the SDTypeConstraint tablegen class in Target.td.
@@ -1217,13 +1217,13 @@ class CodeGenDAGPatterns {
iterator_range<pf_iterator> ptfs() const { return PatternFragments; }
// Patterns to match information.
- typedef std::vector<PatternToMatch>::const_iterator ptm_iterator;
+ using ptm_iterator = std::vector<PatternToMatch>::const_iterator;
ptm_iterator ptm_begin() const { return PatternsToMatch.begin(); }
ptm_iterator ptm_end() const { return PatternsToMatch.end(); }
iterator_range<ptm_iterator> ptms() const { return PatternsToMatch; }
/// Parse the Pattern for an instruction, and insert the result in DAGInsts.
- typedef std::map<const Record *, DAGInstruction, LessRecordByID> DAGInstMap;
+ using DAGInstMap = std::map<const Record *, DAGInstruction, LessRecordByID>;
void parseInstructionPattern(CodeGenInstruction &CGI, const ListInit *Pattern,
DAGInstMap &DAGInsts);
diff --git a/llvm/utils/TableGen/Common/CodeGenHwModes.h b/llvm/utils/TableGen/Common/CodeGenHwModes.h
index 5e1b31ae39e43..55062b6ebeb35 100644
--- a/llvm/utils/TableGen/Common/CodeGenHwModes.h
+++ b/llvm/utils/TableGen/Common/CodeGenHwModes.h
@@ -36,7 +36,7 @@ struct HwMode {
struct HwModeSelect {
HwModeSelect(const Record *R, CodeGenHwModes &CGH);
- typedef std::pair<unsigned, const Record *> PairType;
+ using PairType = std::pair<unsigned, const Record *>;
std::vector<PairType> Items;
void dump() const;
};
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index ed0bfa7098eb7..72958375ab298 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -158,8 +158,8 @@ class CGIOperandList {
OperandInfo &back() { return OperandList.back(); }
const OperandInfo &back() const { return OperandList.back(); }
- typedef std::vector<OperandInfo>::iterator iterator;
- typedef std::vector<OperandInfo>::const_iterator const_iterator;
+ using iterator = std::vector<OperandInfo>::iterator;
+ using const_iterator = std::vector<OperandInfo>::const_iterator;
iterator begin() { return OperandList.begin(); }
const_iterator begin() const { return OperandList.begin(); }
iterator end() { return OperandList.end(); }
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 2eb94b7e92674..2f0ff3f59c47c 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2163,7 +2163,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks(
RegUnits.count(), LaneBitmask::getAll());
// Iterate through SubRegisters.
- typedef CodeGenRegister::SubRegMap SubRegMap;
+ using SubRegMap = CodeGenRegister::SubRegMap;
const SubRegMap &SubRegs = Register.getSubRegs();
for (auto [SubRegIndex, SubReg] : SubRegs) {
// Ignore non-leaf subregisters, their lane masks are fully covered by
@@ -2282,9 +2282,8 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
//
void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
- typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
- deref<std::less<>>>
- SubReg2SetMap;
+ using SubReg2SetMap = std::map<const CodeGenSubRegIndex *,
+ CodeGenRegister::Vec, deref<std::less<>>>;
// Compute the set of registers supporting each SubRegIndex.
SubReg2SetMap SRSets;
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 89dac125e3d15..c02d04b648534 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -93,9 +93,8 @@ class CodeGenSubRegIndex {
std::string getQualifiedName() const;
// Map of composite subreg indices.
- typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
- deref<std::less<>>>
- CompMap;
+ using CompMap =
+ std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, deref<std::less<>>>;
// Returns the subreg index that results from composing this with Idx.
// Returns NULL if this and Idx don't compose.
@@ -180,8 +179,8 @@ class CodeGenRegister {
bool Constant = false;
// Map SubRegIndex -> Register.
- typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>
- SubRegMap;
+ using SubRegMap =
+ std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>;
CodeGenRegister(const Record *R, unsigned Enum);
@@ -220,7 +219,7 @@ class CodeGenRegister {
return SubReg2Idx.lookup(Reg);
}
- typedef std::vector<const CodeGenRegister *> SuperRegList;
+ using SuperRegList = std::vector<const CodeGenRegister *>;
// Get the list of super-registers in topological order, small to large.
// This is valid after computeSubRegs visits all registers during RegBank
@@ -248,8 +247,8 @@ class CodeGenRegister {
}
// List of register units in ascending order.
- typedef SparseBitVector<> RegUnitList;
- typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
+ using RegUnitList = SparseBitVector<>;
+ using RegUnitLaneMaskList = SmallVector<LaneBitmask, 16>;
// How many entries in RegUnitList are native?
RegUnitList NativeRegUnits;
@@ -281,7 +280,7 @@ class CodeGenRegister {
unsigned getWeight(const CodeGenRegBank &RegBank) const;
// Canonically ordered set.
- typedef std::vector<const CodeGenRegister *> Vec;
+ using Vec = std::vector<const CodeGenRegister *>;
private:
bool SubRegsComplete;
@@ -590,7 +589,7 @@ struct RegUnit {
// Each RegUnitSet is a sorted vector with a name.
struct RegUnitSet {
- typedef std::vector<unsigned>::const_iterator iterator;
+ using iterator = std::vector<unsigned>::const_iterator;
std::string Name;
std::vector<unsigned> Units;
@@ -602,7 +601,7 @@ struct RegUnitSet {
// Base vector for identifying TopoSigs. The contents uniquely identify a
// TopoSig, only computeSuperRegs needs to know how.
-typedef SmallVector<unsigned, 16> TopoSigId;
+using TopoSigId = SmallVector<unsigned, 16>;
// CodeGenRegBank - Represent a target's registers and the relations between
// them.
@@ -621,8 +620,8 @@ class CodeGenRegBank {
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
- typedef std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *>
- ConcatIdxMap;
+ using ConcatIdxMap =
+ std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *>;
ConcatIdxMap ConcatIdx;
// Registers.
@@ -639,7 +638,7 @@ class CodeGenRegBank {
// Register classes.
std::list<CodeGenRegisterClass> RegClasses;
DenseMap<const Record *, CodeGenRegisterClass *> Def2RC;
- typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *> RCKeyMap;
+ using RCKeyMap = std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *>;
RCKeyMap Key2RC;
// Register categories.
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 84dfca46dfbfa..d71fdb450e1a9 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -528,10 +528,10 @@ class RuleMatcher : public Matcher {
ArrayRef<SMLoc> SrcLoc;
- typedef std::tuple<const Record *, unsigned, unsigned>
- DefinedComplexPatternSubOperand;
- typedef StringMap<DefinedComplexPatternSubOperand>
- DefinedComplexPatternSubOperandMap;
+ using DefinedComplexPatternSubOperand =
+ std::tuple<const Record *, unsigned, unsigned>;
+ using DefinedComplexPatternSubOperandMap =
+ StringMap<DefinedComplexPatternSubOperand>;
/// A map of Symbolic Names to ComplexPattern sub-operands.
DefinedComplexPatternSubOperandMap ComplexSubOperands;
/// A map used to for multiple referenced error check of ComplexSubOperand.
@@ -1775,7 +1775,7 @@ class OneUsePredicateMatcher : public InstructionPredicateMatcher {
/// * Has an nsw/nuw flag or doesn't.
class InstructionMatcher final : public PredicateListMatcher<PredicateMatcher> {
protected:
- typedef std::vector<std::unique_ptr<OperandMatcher>> OperandVec;
+ using OperandVec = std::vector<std::unique_ptr<OperandMatcher>>;
RuleMatcher &Rule;
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
index 2b3155cace9f3..a16fdbb58e788 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
@@ -174,7 +174,7 @@ bool RegSizeInfoByHwMode::hasStricterSpillThan(
}
void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
- typedef decltype(Map)::value_type PairType;
+ using PairType = decltype(Map)::value_type;
std::vector<const PairType *> Pairs;
for (const auto &P : Map)
Pairs.push_back(&P);
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h
index c730b7397c173..ef688a6f6b3d1 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.h
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.h
@@ -87,10 +87,10 @@ void union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B,
}
template <typename InfoT> struct InfoByHwMode {
- typedef std::map<unsigned, InfoT> MapType;
- typedef typename MapType::value_type PairType;
- typedef typename MapType::iterator iterator;
- typedef typename MapType::const_iterator const_iterator;
+ using MapType = std::map<unsigned, InfoT>;
+ using PairType = typename MapType::value_type;
+ using iterator = typename MapType::iterator;
+ using const_iterator = typename MapType::const_iterator;
InfoByHwMode() = default;
InfoByHwMode(const MapType &M) : Map(M) {}
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index c4dbb148c72c1..ed05af05572c2 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -71,7 +71,7 @@ class ImmPredicateSet {
const TreePredicateFn &getPredicate(unsigned Idx) { return PredsByName[Idx]; }
- typedef std::vector<TreePredicateFn>::const_iterator iterator;
+ using iterator = std::vector<TreePredicateFn>::const_iterator;
iterator begin() const { return PredsByName.begin(); }
iterator end() const { return PredsByName.end(); }
};
@@ -366,12 +366,12 @@ struct OperandsSignature {
class FastISelMap {
// A multimap is needed instead of a "plain" map because the key is
// the instruction's complexity (an int) and they are not unique.
- typedef std::multimap<int, InstructionMemo> PredMap;
- typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
- typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
- typedef std::map<StringRef, TypeRetPredMap> OpcodeTypeRetPredMap;
- typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
- OperandsOpcodeTypeRetPredMap;
+ using PredMap = std::multimap<int, InstructionMemo>;
+ using RetPredMap = std::map<MVT::SimpleValueType, PredMap>;
+ using TypeRetPredMap = std::map<MVT::SimpleValueType, RetPredMap>;
+ using OpcodeTypeRetPredMap = std::map<StringRef, TypeRetPredMap>;
+ using OperandsOpcodeTypeRetPredMap =
+ std::map<OperandsSignature, OpcodeTypeRetPredMap>;
OperandsOpcodeTypeRetPredMap SimplePatterns;
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index e725de1d9f15f..ee3cd8c20f8e7 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -68,9 +68,9 @@ class InstrInfoEmitter {
void emitEnums(raw_ostream &OS,
ArrayRef<const CodeGenInstruction *> NumberedInstructions);
- typedef std::vector<std::string> OperandInfoTy;
- typedef std::vector<OperandInfoTy> OperandInfoListTy;
- typedef std::map<OperandInfoTy, unsigned> OperandInfoMapTy;
+ using OperandInfoTy = std::vector<std::string>;
+ using OperandInfoListTy = std::vector<OperandInfoTy>;
+ using OperandInfoMapTy = std::map<OperandInfoTy, unsigned>;
/// Generate member functions in the target-specific GenInstrInfo class.
///
diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp
index 48ae1a0a92b1c..e2440c110f9f4 100644
--- a/llvm/utils/TableGen/OptionParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptionParserEmitter.cpp
@@ -266,8 +266,8 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
emitSourceFileHeader("Option Parsing Definitions", OS);
// Generate prefix groups.
- typedef SmallVector<SmallString<2>, 2> PrefixKeyT;
- typedef std::map<PrefixKeyT, unsigned> PrefixesT;
+ using PrefixKeyT = SmallVector<SmallString<2>, 2>;
+ using PrefixesT = std::map<PrefixKeyT, unsigned>;
PrefixesT Prefixes;
Prefixes.try_emplace(PrefixKeyT(), 0);
for (const Record &R : llvm::make_pointee_range(Opts)) {
@@ -277,8 +277,8 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
}
// Generate sub command groups.
- typedef SmallVector<StringRef, 2> SubCommandKeyT;
- typedef std::map<SubCommandKeyT, unsigned> SubCommandIDsT;
+ using SubCommandKeyT = SmallVector<StringRef, 2>;
+ using SubCommandIDsT = std::map<SubCommandKeyT, unsigned>;
SubCommandIDsT SubCommandIDs;
auto PrintSubCommandIdsOffset =...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/167168
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