[llvm] [WebAssembly][FastISel] Bail out on meeting non-integer type in selectTrunc (PR #167165)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-webassembly

Author: Hongyu Chen (XChy)

<details>
<summary>Changes</summary>

Fixes https://github.com/llvm/llvm-project/issues/165589
With `simd128` enabled, we may meet vector type truncation in FastISel. To respect #<!-- -->138479, this patch merely bails out on non-integer IR types, though I prefer bailing out for all non-simple types as most targets (X86, AArch64) do.

---
Full diff: https://github.com/llvm/llvm-project/pull/167165.diff


2 Files Affected:

- (modified) llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp (+7-2) 
- (added) llvm/test/CodeGen/WebAssembly/fast-isel-simd128.ll (+22) 


``````````diff
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index 66ed8b078b808..503d4850459cb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -988,11 +988,16 @@ bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
 bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
   const auto *Trunc = cast<TruncInst>(I);
 
-  Register Reg = getRegForValue(Trunc->getOperand(0));
+  const Value *Op = Trunc->getOperand(0);
+  Register Reg = getRegForValue(Op);
   if (Reg == 0)
     return false;
 
-  unsigned FromBitWidth = Trunc->getOperand(0)->getType()->getIntegerBitWidth();
+  // Bail out on meeting non-integer types.
+  if (!Op->getType()->isIntegerTy() || !Trunc->getType()->isIntegerTy())
+    return false;
+
+  unsigned FromBitWidth = Op->getType()->getIntegerBitWidth();
   unsigned ToBitWidth = Trunc->getType()->getIntegerBitWidth();
 
   if (ToBitWidth <= 32 && (32 < FromBitWidth && FromBitWidth <= 64)) {
diff --git a/llvm/test/CodeGen/WebAssembly/fast-isel-simd128.ll b/llvm/test/CodeGen/WebAssembly/fast-isel-simd128.ll
new file mode 100644
index 0000000000000..aefadec3e3fc5
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/fast-isel-simd128.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -fast-isel -fast-isel-abort=0 -mattr=+simd128 -verify-machineinstrs | FileCheck %s
+
+target triple = "wasm32-unknown-wasi"
+
+define i8 @pr165438(<4 x i32> %0) {
+; CHECK-LABEL: pr165438:
+; CHECK:         .functype pr165438 (v128) -> (i32)
+; CHECK-NEXT:  # %bb.0: # %entry
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i8x16.shuffle 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    i8x16.extract_lane_u 0
+; CHECK-NEXT:    # fallthrough-return
+entry:
+  %conv = trunc <4 x i32> %0 to <4 x i8>
+  br label %cond.true
+
+cond.true:                                        ; preds = %entry
+  %vecext = extractelement <4 x i8> %conv, i32 0
+  ret i8 %vecext
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/167165