[llvm] [DAGCombiner, NVPTX] Port 'rem' custom combine from NVPTX to generic combiner (PR #167147)

[Matt Arsenault via llvm-commits]

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@@ -900,6 +900,41 @@ namespace {
                          ISD::NodeType ExtType);
   };
 
+/// Generic remainder optimization : Folds a remainder operation (A % B) by reusing the computed quotient (A / B).
+static SDValue PerformREMCombineGeneric(SDNode *N, DAGCombiner &DC,
+                                        CodeGenOptLevel OptLevel) {
+  assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
+
+  // Don't do anything at less than -O2.
+  if (OptLevel < CodeGenOptLevel::Default)
+    return SDValue();
+
+  SelectionDAG &DAG = DC.getDAG();
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
+  bool IsSigned = N->getOpcode() == ISD::SREM;
+  unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
+
+  const SDValue &Num = N->getOperand(0);
+  const SDValue &Den = N->getOperand(1);
+  
+  AttributeList Attr = DC.getDAG().getMachineFunction().getFunction().getAttributes();
+  if (DC.getDAG().getTargetLoweringInfo().isIntDivCheap(N->getValueType(0), Attr))
+    return SDValue();
+
+  for (const SDNode *U : Num->users()) {
+    if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
+        U->getOperand(1) == Den) {
+      // Num % Den -> Num - (Num / Den) * Den
+      return DAG.getNode(ISD::SUB, DL, VT, Num,
+                         DAG.getNode(ISD::MUL, DL, VT,
+                                     DAG.getNode(DivOpc, DL, VT, Num, Den),
+                                     Den));
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arsenm wrote:

Use temporary variables to reduce ugly line wrap 

https://github.com/llvm/llvm-project/pull/167147